The kink effect of gate-all-around (GAA) MOSFET has been experimentally validated by our GAA devices fabricated on a void embedded silicon-on-insulator (VESOI) substrate. In this VESOI GAA device, a consistent and favorable decrease in subthreshold swing (SS) is observed as $V_{mathrm { d}}$ increases, which has rarely been reported in devices with other gate structures. In particular, the SS of the device reaches the minimum ~0.1mV/dec with no discernable hysteresis window at $V_{mathrm { d}} {=} 4.5$ V under ambient condition. Further device simulation strongly confirms the unique role of the GAA controllability over the hysteresis-free kink process. These findings contribute to a better understanding of kink behaviors within GAA device for potential application.
{"title":"Subthreshold Kink Effect in Gate-All-Around MOSFETs Based on Void Embedded Silicon on Insulator Technology","authors":"Yuxin Liu;Qiang Liu;Jin Chen;Zhiqiang Mu;Xing Wei;Wenjie Yu","doi":"10.1109/JEDS.2024.3478750","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3478750","url":null,"abstract":"The kink effect of gate-all-around (GAA) MOSFET has been experimentally validated by our GAA devices fabricated on a void embedded silicon-on-insulator (VESOI) substrate. In this VESOI GAA device, a consistent and favorable decrease in subthreshold swing (SS) is observed as \u0000<inline-formula> <tex-math>$V_{mathrm { d}}$ </tex-math></inline-formula>\u0000 increases, which has rarely been reported in devices with other gate structures. In particular, the SS of the device reaches the minimum ~0.1mV/dec with no discernable hysteresis window at \u0000<inline-formula> <tex-math>$V_{mathrm { d}} {=} 4.5$ </tex-math></inline-formula>\u0000V under ambient condition. Further device simulation strongly confirms the unique role of the GAA controllability over the hysteresis-free kink process. These findings contribute to a better understanding of kink behaviors within GAA device for potential application.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"941-947"},"PeriodicalIF":2.0,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10714381","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A closed-form, analytical, and unified model for the surface potential from source to drain in nanowire (NW) gate-all-around (GAA) tunneling field effect transistors (TFETs) is proposed and validated. Foremost, the correctness of the dual modulation effect in GAA-TFETs is demonstrated. Building on that, the model comprehensively considers the effects of the channel depletion region, drain depletion region, and channel inversion charges. Furthermore, a compact current model for GAA-TFETs, based on the derived surface potential expression, is presented, with a discussion on ambipolar conduction—an essential factor for device model integrity. The model’s accuracy and flexibility are validated through TCAD simulations and measurement data from NW-GAA-TFETs, yielding promising results.
{"title":"Surface-Potential-Based Drain Current Model of Gate-All-Around Tunneling FETs","authors":"Zhanhang Chen;Haoliang Shan;Ziyi Ding;Xia Wu;Xiaolin Cen;Xiaoyu Ma;Wanling Deng;Junkai Huang","doi":"10.1109/JEDS.2024.3477928","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3477928","url":null,"abstract":"A closed-form, analytical, and unified model for the surface potential from source to drain in nanowire (NW) gate-all-around (GAA) tunneling field effect transistors (TFETs) is proposed and validated. Foremost, the correctness of the dual modulation effect in GAA-TFETs is demonstrated. Building on that, the model comprehensively considers the effects of the channel depletion region, drain depletion region, and channel inversion charges. Furthermore, a compact current model for GAA-TFETs, based on the derived surface potential expression, is presented, with a discussion on ambipolar conduction—an essential factor for device model integrity. The model’s accuracy and flexibility are validated through TCAD simulations and measurement data from NW-GAA-TFETs, yielding promising results.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"948-955"},"PeriodicalIF":2.0,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10713252","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-07DOI: 10.1109/JEDS.2024.3475513
Magaly Ramírez-Como;Monica M. Valdez-Mata;Angel Sacramento;José L. Casas-Espínola;Luis Reséndiz;Lluis F. Marsal
This study investigates the impact of incorporating graphite nanoparticles (GNPs) into poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) as hybrid hole transport layer (HTL) in non-fullerene organic solar cells (NF-OSCs) based on PBDB-T-2F:BTP-4CL. The concentration of GNPs in the PEDOT:PSS layer was varied to investigate their impact on the overall device behavior. The PCE initially increased with the GNPs concentration up to 5% v/v, reaching a maximum enhancement of 6.43%, which was attributed to the increased JSC. Current-voltage measurements and Mott-Schottky analysis through capacitance-voltage characteristics were conducted to evaluate the behavior of the charge recombination and built-in potential due to the concentration variation of the GNPs into PEDOT:PSS. This study illustrates the potential of GNPs to improve OSC performance through enhanced light absorption, reduced recombination losses, and improved charge carrier transport, indicating promising prospects for GNPs on interface layers in OSCs.
{"title":"Utilization of Graphite Nanoparticles as a Hybrid Hole Transport Layer in Non-Fullerene Organic Solar Cells","authors":"Magaly Ramírez-Como;Monica M. Valdez-Mata;Angel Sacramento;José L. Casas-Espínola;Luis Reséndiz;Lluis F. Marsal","doi":"10.1109/JEDS.2024.3475513","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3475513","url":null,"abstract":"This study investigates the impact of incorporating graphite nanoparticles (GNPs) into poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) as hybrid hole transport layer (HTL) in non-fullerene organic solar cells (NF-OSCs) based on PBDB-T-2F:BTP-4CL. The concentration of GNPs in the PEDOT:PSS layer was varied to investigate their impact on the overall device behavior. The PCE initially increased with the GNPs concentration up to 5% v/v, reaching a maximum enhancement of 6.43%, which was attributed to the increased JSC. Current-voltage measurements and Mott-Schottky analysis through capacitance-voltage characteristics were conducted to evaluate the behavior of the charge recombination and built-in potential due to the concentration variation of the GNPs into PEDOT:PSS. This study illustrates the potential of GNPs to improve OSC performance through enhanced light absorption, reduced recombination losses, and improved charge carrier transport, indicating promising prospects for GNPs on interface layers in OSCs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"1044-1050"},"PeriodicalIF":2.0,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10706788","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142912374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-07DOI: 10.1109/JEDS.2024.3475289
Ao Zhang;Jianjun Gao
An improved EEHEMT nonlinear model with noise model has been developed in this paper. Empirical formulas of bias dependent noise model parameters are given. A four-stage 120–160 GHz monolithic low-noise amplifier (LNA) fabricated with the 70nm InAlAs/InGaAs/InP HEMT technology. The simulated results of S-parameters and noise figure show the good agreement with measured data to verify the accuracy of the proposed model.
{"title":"HEMT Noise Modeling for D Band Low Noise Amplifier Design","authors":"Ao Zhang;Jianjun Gao","doi":"10.1109/JEDS.2024.3475289","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3475289","url":null,"abstract":"An improved EEHEMT nonlinear model with noise model has been developed in this paper. Empirical formulas of bias dependent noise model parameters are given. A four-stage 120–160 GHz monolithic low-noise amplifier (LNA) fabricated with the 70nm InAlAs/InGaAs/InP HEMT technology. The simulated results of S-parameters and noise figure show the good agreement with measured data to verify the accuracy of the proposed model.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"928-933"},"PeriodicalIF":2.0,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10706073","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142452734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-04DOI: 10.1109/JEDS.2024.3474291
Minxi Cai;Wei Zhong;Bei Liu;Piaorong Xu;Jing Cao
A DC model is proposed for amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) applicable to various active layer thicknesses. With the back surface potential and its coupling with the front surface potential being considered, an explicit potential solution is developed. Then, the analytical drain current and physical definition of threshold voltage are derived based on a non-chargesheet expression of free charge density. It is verified that in the previous models for AOS TFTs, typically ignoring the back surface potential and the active layer thickness effects could result in obvious deviations in the values of parameters during the characterization of DC performance, especially for scaled devices with low channel thicknesses. By comparing with numerical calculations and experimental data, this model is validated to be more suitable for AOS TFTs with decreased dimensions, which could give more realistic distributions of the density of states in the channel during parameter extraction.
本文提出了适用于各种有源层厚度的非晶氧化物半导体（AOS）薄膜晶体管（TFT）的直流模型。考虑到后表面电势及其与前表面电势的耦合，建立了一个显式电势解决方案。然后，根据自由电荷密度的非电荷片表达式推导出分析漏极电流和阈值电压的物理定义。结果证明，在以往的 AOS TFT 模型中，通常忽略背面电势和有源层厚度效应会导致直流性能表征过程中的参数值出现明显偏差，特别是对于沟道厚度较低的缩放器件。通过与数值计算和实验数据的比较，验证了该模型更适用于尺寸减小的 AOS TFT，在参数提取过程中能给出更真实的沟道内态密度分布。
{"title":"A Physics-Based Compact DC Model for AOS TFTs Considering Effects of Active Layer Thickness Variation","authors":"Minxi Cai;Wei Zhong;Bei Liu;Piaorong Xu;Jing Cao","doi":"10.1109/JEDS.2024.3474291","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3474291","url":null,"abstract":"A DC model is proposed for amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) applicable to various active layer thicknesses. With the back surface potential and its coupling with the front surface potential being considered, an explicit potential solution is developed. Then, the analytical drain current and physical definition of threshold voltage are derived based on a non-chargesheet expression of free charge density. It is verified that in the previous models for AOS TFTs, typically ignoring the back surface potential and the active layer thickness effects could result in obvious deviations in the values of parameters during the characterization of DC performance, especially for scaled devices with low channel thicknesses. By comparing with numerical calculations and experimental data, this model is validated to be more suitable for AOS TFTs with decreased dimensions, which could give more realistic distributions of the density of states in the channel during parameter extraction.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"919-927"},"PeriodicalIF":2.0,"publicationDate":"2024-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10705102","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142442958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-01DOI: 10.1109/JEDS.2024.3471999
Eunseok Oh;Hyungcheol Shin
Random telegraph noise (RTN) shifts the threshold voltage (Vt) of 3D NAND flash memory cells, making it a key factor of the device malfunction. The aim of this study is to predict the distribution of RTN induced ${mathrm { V}}_{mathrm { t}}$ shift in 3D NAND flash memory. Artificial neural network (ANN)-based machine learning (ML) is used for this prediction. With 2000 samples, ANN is trained and tested to predict the ${mathrm { V}}_{mathrm { t}}$ shift of random cells with high reliability. Furthermore, ANN is applied to predict the tendency of RTN-induced ${mathrm { V}}_{mathrm { t}}$ shift in scaled 3D NAND. Compared to prior works which has required far more measurements or simulations, the predictions are shown to shorten the time spent to obtain the distribution. Based on these predictions, the dependency of the decay constant on cell variation is investigated, which is a most critical parameter in analyzing the RTN distribution. This indicates that it is possible to apply ANN-based ML to predict various characteristics of 3D NAND flash memory in a much shorter time and to develop numerical models of related parameters.
{"title":"Prediction of Random Telegraph Noise-Induced Threshold Voltage Shift and Its Scaling Dependency Using Machine Learning","authors":"Eunseok Oh;Hyungcheol Shin","doi":"10.1109/JEDS.2024.3471999","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3471999","url":null,"abstract":"Random telegraph noise (RTN) shifts the threshold voltage (Vt) of 3D NAND flash memory cells, making it a key factor of the device malfunction. The aim of this study is to predict the distribution of RTN induced \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { t}}$ </tex-math></inline-formula>\u0000 shift in 3D NAND flash memory. Artificial neural network (ANN)-based machine learning (ML) is used for this prediction. With 2000 samples, ANN is trained and tested to predict the \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { t}}$ </tex-math></inline-formula>\u0000 shift of random cells with high reliability. Furthermore, ANN is applied to predict the tendency of RTN-induced \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { t}}$ </tex-math></inline-formula>\u0000 shift in scaled 3D NAND. Compared to prior works which has required far more measurements or simulations, the predictions are shown to shorten the time spent to obtain the distribution. Based on these predictions, the dependency of the decay constant on cell variation is investigated, which is a most critical parameter in analyzing the RTN distribution. This indicates that it is possible to apply ANN-based ML to predict various characteristics of 3D NAND flash memory in a much shorter time and to develop numerical models of related parameters.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"934-940"},"PeriodicalIF":2.0,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10702511","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-30DOI: 10.1109/JEDS.2024.3469917
Junha Suk;Yohan Kim;Jungho Do;Garoom Kim;Woojin Rim;Sanghoon Baek;Seiseung Yoon;Soyoung Kim
In this paper, we propose a process-aware analytical gate resistance model for nanosheet field-effect transistors (NSFETs). The proposed NSFET gate resistance is modeled by applying the distributed resistance coefficient, which can be used when current flows vertically and horizontally. By predicting the direction of current flow, the resistance components are approximated in series with parallel connection of divided segments. The proposed model can reflect changes in structural parameters, making it possible to predict the scaling trend of NSFETs. This is validated through TCAD simulation results. The proposed model can be implemented in general compact models such as the Berkeley short channel IGFET model (BSIM)-common multi-gate (CMG) and can be used to predict circuit performance more accurately.
{"title":"A Process-Aware Analytical Gate Resistance Model for Nanosheet Field-Effect Transistors","authors":"Junha Suk;Yohan Kim;Jungho Do;Garoom Kim;Woojin Rim;Sanghoon Baek;Seiseung Yoon;Soyoung Kim","doi":"10.1109/JEDS.2024.3469917","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3469917","url":null,"abstract":"In this paper, we propose a process-aware analytical gate resistance model for nanosheet field-effect transistors (NSFETs). The proposed NSFET gate resistance is modeled by applying the distributed resistance coefficient, which can be used when current flows vertically and horizontally. By predicting the direction of current flow, the resistance components are approximated in series with parallel connection of divided segments. The proposed model can reflect changes in structural parameters, making it possible to predict the scaling trend of NSFETs. This is validated through TCAD simulation results. The proposed model can be implemented in general compact models such as the Berkeley short channel IGFET model (BSIM)-common multi-gate (CMG) and can be used to predict circuit performance more accurately.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"898-904"},"PeriodicalIF":2.0,"publicationDate":"2024-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10699326","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142408862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-27DOI: 10.1109/JEDS.2024.3469398
Nalin Vilochan Mishra;Aditya Sankar Medury
The ability of Ultra-Thin-Body (UTB) MOS devices to enable channel length scaling can only be realistically assessed by accurately taking key physical effects such as Quantum Confinement effects (QCEs) and Short channel effects (SCEs) into account. QCEs can accurately be considered only through a full band structure-based approach, which tends to be computationally inefficient, particularly at higher channel thicknesses, and is further exacerbated when required to be used to calculate 2-D channel electrostatics. Therefore, in this work, we propose a methodology to efficiently simulate the channel electrostatics of a UTB Double Gate MOSFET by solving the 1-D band structure with the 2-D Poisson’s equation self consistently, determined by using the $sp^{3}d^{5}s^{*}$ semi-empirical tight-binding approach only over those k-points that are likely to have a significant effect on the electrostatics. By showing that determining the 1-D Band structure at the source-channel junction is adequate to accurately determine the 2-D channel electrostatics, we show that this approach remains computationally tractable even at higher channel lengths. By following this approach, we obtain the 2-D profile of important device parameters such as electron density and channel potential, which, in turn, enables the determination of the thermionic current density and source-to-drain tunneling current density for a wide range of device parameters using Tsu-Esaki and WKB formalism respectively. Furthermore, the effect of phonon scattering, which is likely to manifest at longer channel lengths, is also incorporated in the drain current calculation, thus making this approach widely applicable.
{"title":"Computationally Efficient Band Structure-Based Approach for Accurately Determining Electrostatics and Source-to-Drain Tunneling Current in UTB MOSFETs","authors":"Nalin Vilochan Mishra;Aditya Sankar Medury","doi":"10.1109/JEDS.2024.3469398","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3469398","url":null,"abstract":"The ability of Ultra-Thin-Body (UTB) MOS devices to enable channel length scaling can only be realistically assessed by accurately taking key physical effects such as Quantum Confinement effects (QCEs) and Short channel effects (SCEs) into account. QCEs can accurately be considered only through a full band structure-based approach, which tends to be computationally inefficient, particularly at higher channel thicknesses, and is further exacerbated when required to be used to calculate 2-D channel electrostatics. Therefore, in this work, we propose a methodology to efficiently simulate the channel electrostatics of a UTB Double Gate MOSFET by solving the 1-D band structure with the 2-D Poisson’s equation self consistently, determined by using the \u0000<inline-formula> <tex-math>$sp^{3}d^{5}s^{*}$ </tex-math></inline-formula>\u0000 semi-empirical tight-binding approach only over those k-points that are likely to have a significant effect on the electrostatics. By showing that determining the 1-D Band structure at the source-channel junction is adequate to accurately determine the 2-D channel electrostatics, we show that this approach remains computationally tractable even at higher channel lengths. By following this approach, we obtain the 2-D profile of important device parameters such as electron density and channel potential, which, in turn, enables the determination of the thermionic current density and source-to-drain tunneling current density for a wide range of device parameters using Tsu-Esaki and WKB formalism respectively. Furthermore, the effect of phonon scattering, which is likely to manifest at longer channel lengths, is also incorporated in the drain current calculation, thus making this approach widely applicable.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"881-888"},"PeriodicalIF":2.0,"publicationDate":"2024-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10697110","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142383489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-26DOI: 10.1109/JEDS.2024.3468300
Jinyeong Lee;Jaewook Jeong
In this paper, the photoluminescence characteristics of solution-processed amorphous ZnO and related compounds of InZnO and GaZnO thin films were comparatively analyzed. Depending on the molarity of the precursor solution, PL emission peaks ranging from 382.4 nm to 384.8 nm were observed for the ZnO thin films. The PL emission peaks were closely related to the surface morphology of the thin films, which were clearly observed when isolated, nano-sized particles of quantum dot structure were present, leading to quantum confinement effect in the ZnO and GaZnO thin films. When uniform thin films formed, the PL emission peaks disappeared due to the increase of electrical and morphological connectivity, which reveals that the analysis of PL emission peak can be used to evaluate the film quality and the performance of thin-film transistors (TFTs) in solution-processed oxide-based materials.
{"title":"Correlation Between Quantum Confinement Effect and Characteristics of Thin-Film Transistors in Solution-Processed Oxide-Based Thin-Films","authors":"Jinyeong Lee;Jaewook Jeong","doi":"10.1109/JEDS.2024.3468300","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3468300","url":null,"abstract":"In this paper, the photoluminescence characteristics of solution-processed amorphous ZnO and related compounds of InZnO and GaZnO thin films were comparatively analyzed. Depending on the molarity of the precursor solution, PL emission peaks ranging from 382.4 nm to 384.8 nm were observed for the ZnO thin films. The PL emission peaks were closely related to the surface morphology of the thin films, which were clearly observed when isolated, nano-sized particles of quantum dot structure were present, leading to quantum confinement effect in the ZnO and GaZnO thin films. When uniform thin films formed, the PL emission peaks disappeared due to the increase of electrical and morphological connectivity, which reveals that the analysis of PL emission peak can be used to evaluate the film quality and the performance of thin-film transistors (TFTs) in solution-processed oxide-based materials.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"912-918"},"PeriodicalIF":2.0,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10695762","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142442957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The device performance of indium zinc oxide (IZO) thin-film transistors (TFTs) is optimized through process optimizations. By jointly adjusting the annealing condition, the channel thickness and the sputtering atmosphere, the roughness and oxygen vacancies (Vos) are precisely regulated. The optimized IZO TFTs can achieve the highest field effect mobility of ~71.8 cm2/Vs with a threshold voltage of ~-0.6 V. Reliability of IZO TFTs under positive/negative bias stress is also examined. The interface quality and the Vo are two key factors influencing the device performance and reliability, confirmed by X-ray photoelectron spectroscopy and atomic force microscopy analysis.
{"title":"Performance Enhancement of Indium Zinc Oxide Thin-Film Transistors Through Process Optimizations","authors":"Mingjun Zhang;Jinyang Huang;Zihan Wang;Paramasivam Balasubramanian;Yan Yan;Ye Zhou;Su-Ting Han;Lei Lu;Meng Zhang","doi":"10.1109/JEDS.2024.3466956","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3466956","url":null,"abstract":"The device performance of indium zinc oxide (IZO) thin-film transistors (TFTs) is optimized through process optimizations. By jointly adjusting the annealing condition, the channel thickness and the sputtering atmosphere, the roughness and oxygen vacancies (Vos) are precisely regulated. The optimized IZO TFTs can achieve the highest field effect mobility of ~71.8 cm2/Vs with a threshold voltage of ~-0.6 V. Reliability of IZO TFTs under positive/negative bias stress is also examined. The interface quality and the Vo are two key factors influencing the device performance and reliability, confirmed by X-ray photoelectron spectroscopy and atomic force microscopy analysis.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"868-874"},"PeriodicalIF":2.0,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10690260","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142383447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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