4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) are beginning to be installed in electric vehicles (EVs), and the demand for reliability as well as chip performance is increasing. Generally, multiple chips are connected in parallel. Although SiC MOSFETs have a smaller temperature dependence of on-resistance <inline-formula> <tex-math>$(R_{mathrm { on}})$ </tex-math></inline-formula> than Si MOSFETs, they are prone to current imbalance due to the negative temperature dependence of the threshold voltage <inline-formula> <tex-math>$(V_{mathrm { th}})$ </tex-math></inline-formula>, which is also affected by the dispersion of <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula>, and is said to be a challenge for module stability and reliability <xref>[1]</xref>, <xref>[2]</xref>, <xref>[3]</xref>. To solve this problem, appropriate chip classification, addition of inductance, and devising a new gate driving method are being considered <xref>[4]</xref>, <xref>[5]</xref>, <xref>[6]</xref>. However, from the perspective of chip suppliers, ensuring uniformity of <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula> is the top priority. So far, the high electron trap density at the MOS interface of SiC MOSFETs has been a major obstacle to improving performance. Post oxidation annealing (POA) technology after gate oxidation has improved channel mobility by passivating electron traps <xref>[7]</xref>, and the channel resistance has been significantly reduced by increasing the channel density through the application of trench-type gates with sidewalls made of the crystal planes of {1-100} or {11-20} with the low electron trap density <xref>[8]</xref>, <xref>[9]</xref>, <xref>[10]</xref>. However, since the electron trap density is strongly dependent on the crystal plane orientation <xref>[11]</xref>, <xref>[12]</xref>, the interface charge density will vary if the crystal orientation of the MOS interface is misaligned. As a result, the angle misalignment of the trench sidewalls causes variations in <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula>. In response to this, we have developed a V-shaped trench MOSFET (VMOSFET) with sidewalls made of {0-33-8} planes, which have the smallest electron trap density <xref>[13]</xref>, <xref>[14]</xref>, <xref>[15]</xref>, <xref>[16]</xref>. Since V-shaped trenches are formed by a thermo-chemical etching in a chlorine gas ambient <xref>[17]</xref>, <xref>[18]</xref>, the crystal planes are naturally exposed according to the chemical properties of 4H-SiC, the crystal orientation of the MOS interface is not essentially misaligned. Therefore, it is possible to manufacture chips with small variations in <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula> and good reproducibility. In this article, we introduce the unique device structures and manufacturing processes that support the performance and reliability of the
{"title":"Key Technologies Supporting High Performance and Reliability of SiC VMOSFET","authors":"Takeyoshi Masuda;Yoshinori Hara;Tomoki Ikeda;Kosuke Uchida;Yu Saito;Shin Harada;Tomoaki Hatayama;Jun Wada;Toru Hiyoshi;Hirofumi Yamamoto;Masaki Furumai;Takao Kiyama;Heiji Watanabe","doi":"10.1109/JEDS.2025.3614628","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3614628","url":null,"abstract":"4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) are beginning to be installed in electric vehicles (EVs), and the demand for reliability as well as chip performance is increasing. Generally, multiple chips are connected in parallel. Although SiC MOSFETs have a smaller temperature dependence of on-resistance <inline-formula> <tex-math>$(R_{mathrm { on}})$ </tex-math></inline-formula> than Si MOSFETs, they are prone to current imbalance due to the negative temperature dependence of the threshold voltage <inline-formula> <tex-math>$(V_{mathrm { th}})$ </tex-math></inline-formula>, which is also affected by the dispersion of <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula>, and is said to be a challenge for module stability and reliability <xref>[1]</xref>, <xref>[2]</xref>, <xref>[3]</xref>. To solve this problem, appropriate chip classification, addition of inductance, and devising a new gate driving method are being considered <xref>[4]</xref>, <xref>[5]</xref>, <xref>[6]</xref>. However, from the perspective of chip suppliers, ensuring uniformity of <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula> is the top priority. So far, the high electron trap density at the MOS interface of SiC MOSFETs has been a major obstacle to improving performance. Post oxidation annealing (POA) technology after gate oxidation has improved channel mobility by passivating electron traps <xref>[7]</xref>, and the channel resistance has been significantly reduced by increasing the channel density through the application of trench-type gates with sidewalls made of the crystal planes of {1-100} or {11-20} with the low electron trap density <xref>[8]</xref>, <xref>[9]</xref>, <xref>[10]</xref>. However, since the electron trap density is strongly dependent on the crystal plane orientation <xref>[11]</xref>, <xref>[12]</xref>, the interface charge density will vary if the crystal orientation of the MOS interface is misaligned. As a result, the angle misalignment of the trench sidewalls causes variations in <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula>. In response to this, we have developed a V-shaped trench MOSFET (VMOSFET) with sidewalls made of {0-33-8} planes, which have the smallest electron trap density <xref>[13]</xref>, <xref>[14]</xref>, <xref>[15]</xref>, <xref>[16]</xref>. Since V-shaped trenches are formed by a thermo-chemical etching in a chlorine gas ambient <xref>[17]</xref>, <xref>[18]</xref>, the crystal planes are naturally exposed according to the chemical properties of 4H-SiC, the crystal orientation of the MOS interface is not essentially misaligned. Therefore, it is possible to manufacture chips with small variations in <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula> and good reproducibility. In this article, we introduce the unique device structures and manufacturing processes that support the performance and reliability of the","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1267-1275"},"PeriodicalIF":2.4,"publicationDate":"2025-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11182284","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work uncovers a temperature-dependent relationship between gate leakage current ($mathrm{I}_{mathrm{G}}$ ) and threshold voltage shift ($Delta mathrm{V}_{mathrm{TH}}$ ) through an evaluation combining deep level transient spectroscopy (DLTS) measurements, $mathrm{I}_{mathrm{G}}$ testing, and assessments of $mathrm{V}_{mathrm{TH}}$ instability. Analysis across a temperature range of 80 K to 440 K of p-GaN gate defects on device characteristics. These findings indicate that the same type of gate defects simultaneously affects both gate leakage and $mathrm{V}_{mathrm{TH}}$ instability. Specifically, defects release holes during positive gate stress. During low-bias $mathrm{V}_{text {TH }}$ measurement, the persistent negative charge from defects, due to slow hole re-trapping, enhances the depletion of the two-dimensional electron gas (2DEG) at the AlGaN/GaN interface, reducing 2DEG density and causing a positive $Delta mathrm{V}_{mathrm{TH}}$ . Furthermore, high-temperature gate bias (HTGB) stress significantly increases the concentration of relevant defects within the p-GaN gate, leading to a marked rise in both $mathrm{I}_{mathrm{G}}$ and $Delta mathrm{V}_{mathrm{TH}}$ . Notably, the $mathrm{I}_{mathrm{G}} / Delta mathrm{V}_{mathrm{TH}}$ ratio remains consistent even after HTGB stress. These observations provide valuable insights into the relationship between gate defects and the performance of p-GaN gate HEMT.
{"title":"Study on the Relationship Between Threshold Voltage Instability and Gate Leakage Current in p-GaN HEMTs","authors":"Yifan Cui;Yang Jiang;Yutian Gan;Qiaoyu Hu;Qing Wang;Hongyu Yu","doi":"10.1109/JEDS.2025.3603890","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3603890","url":null,"abstract":"This work uncovers a temperature-dependent relationship between gate leakage current (<inline-formula> <tex-math>$mathrm{I}_{mathrm{G}}$ </tex-math></inline-formula>) and threshold voltage shift (<inline-formula> <tex-math>$Delta mathrm{V}_{mathrm{TH}}$ </tex-math></inline-formula>) through an evaluation combining deep level transient spectroscopy (DLTS) measurements, <inline-formula> <tex-math>$mathrm{I}_{mathrm{G}}$ </tex-math></inline-formula> testing, and assessments of <inline-formula> <tex-math>$mathrm{V}_{mathrm{TH}}$ </tex-math></inline-formula> instability. Analysis across a temperature range of 80 K to 440 K of p-GaN gate defects on device characteristics. These findings indicate that the same type of gate defects simultaneously affects both gate leakage and <inline-formula> <tex-math>$mathrm{V}_{mathrm{TH}}$ </tex-math></inline-formula> instability. Specifically, defects release holes during positive gate stress. During low-bias <inline-formula> <tex-math>$mathrm{V}_{text {TH }}$ </tex-math></inline-formula> measurement, the persistent negative charge from defects, due to slow hole re-trapping, enhances the depletion of the two-dimensional electron gas (2DEG) at the AlGaN/GaN interface, reducing 2DEG density and causing a positive <inline-formula> <tex-math>$Delta mathrm{V}_{mathrm{TH}}$ </tex-math></inline-formula>. Furthermore, high-temperature gate bias (HTGB) stress significantly increases the concentration of relevant defects within the p-GaN gate, leading to a marked rise in both <inline-formula> <tex-math>$mathrm{I}_{mathrm{G}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$Delta mathrm{V}_{mathrm{TH}}$ </tex-math></inline-formula>. Notably, the <inline-formula> <tex-math>$mathrm{I}_{mathrm{G}} / Delta mathrm{V}_{mathrm{TH}}$ </tex-math></inline-formula> ratio remains consistent even after HTGB stress. These observations provide valuable insights into the relationship between gate defects and the performance of p-GaN gate HEMT.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1018-1025"},"PeriodicalIF":2.4,"publicationDate":"2025-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11148282","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145110192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-28DOI: 10.1109/JEDS.2025.3603559
Satoshi Fujii;Soma Shimabukuro;Akira Uedono
The miniaturization of Si-MOS-FET logic integrated circuits necessitates the precise control of electron and hole densities through high-concentration impurity doping to realize transistors within the 2 nm technology node. Among the various thermal treatment techniques, microwave annealing (MWA) has emerged as a promising method for forming high-concentration active layers, offering advantages such as rapid processing and potential nonthermal effects. However, existing MWA systems suffer from interference and standing-wave effects because of their multimode cavity design, which makes it challenging to understand the underlying mechanisms. This study investigated the fundamental heating mechanisms of MWA, focusing on both the electric and magnetic field contributions. The role of Joule heating was examined, and the presence of nonthermal microwave effects was explored by applying MWA to Si substrates implanted with phosphorus or boron and comparing the results with those of conventional rapid thermal processing. The experimental evaluations included sheet resistance measurements, impurity distribution analysis, and defect assessments using slow-energy positron annihilation spectroscopy. The findings indicate that MWA enables the effective activation of implanted impurities at low temperatures, reduces defect formation, and minimizes impurity diffusion, highlighting its potential as a low-temperature processing technique for fabricating advanced semiconductor devices.
{"title":"Mechanistic Insights Into Microwave Annealing for Lattice Defect Recovery","authors":"Satoshi Fujii;Soma Shimabukuro;Akira Uedono","doi":"10.1109/JEDS.2025.3603559","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3603559","url":null,"abstract":"The miniaturization of Si-MOS-FET logic integrated circuits necessitates the precise control of electron and hole densities through high-concentration impurity doping to realize transistors within the 2 nm technology node. Among the various thermal treatment techniques, microwave annealing (MWA) has emerged as a promising method for forming high-concentration active layers, offering advantages such as rapid processing and potential nonthermal effects. However, existing MWA systems suffer from interference and standing-wave effects because of their multimode cavity design, which makes it challenging to understand the underlying mechanisms. This study investigated the fundamental heating mechanisms of MWA, focusing on both the electric and magnetic field contributions. The role of Joule heating was examined, and the presence of nonthermal microwave effects was explored by applying MWA to Si substrates implanted with phosphorus or boron and comparing the results with those of conventional rapid thermal processing. The experimental evaluations included sheet resistance measurements, impurity distribution analysis, and defect assessments using slow-energy positron annihilation spectroscopy. The findings indicate that MWA enables the effective activation of implanted impurities at low temperatures, reduces defect formation, and minimizes impurity diffusion, highlighting its potential as a low-temperature processing technique for fabricating advanced semiconductor devices.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1258-1266"},"PeriodicalIF":2.4,"publicationDate":"2025-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11143163","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-27DOI: 10.1109/JEDS.2025.3603203
A. Uedono;R. Tanaka;S. Takashima;K. Ueno;M. Edo;K. Shima;S. F. Chichibu;J. Uzuhashi;T. Ohkubo;S. Ishibashi;K. Sierakowski;M. Bockowski
Annealing behaviors of vacancy-type defects in Mg and N-implanted GaN were studied by positron annihilation. The major defect species in as-implanted samples was identified as Ga-vacancy (VGa)-type defects. For Mg-implanted GaN with sequential N-implantation after annealing above 1000°C, the defect species were vacancy clusters such as (VGaVN)3. Due to the downward shift of the Fermi level position resulting from a partial activation of Mg, the charge states of defects tended to become positive. For N-implanted GaN, the size of the vacancy cluster started to decrease above 1200°C annealing, which was attributed to recombinations between VNs coupled with VGas and excess N atoms. The impact of sequential N-implantations on vacancies in Mg-implanted GaN was found to be most pronounced when the ratio of the concentration of N to that of Mg was three.
{"title":"Characterization of Vacancy-Type Defects in Mg- and N-Implanted GaN by Using a Monoenergetic Positron Beam","authors":"A. Uedono;R. Tanaka;S. Takashima;K. Ueno;M. Edo;K. Shima;S. F. Chichibu;J. Uzuhashi;T. Ohkubo;S. Ishibashi;K. Sierakowski;M. Bockowski","doi":"10.1109/JEDS.2025.3603203","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3603203","url":null,"abstract":"Annealing behaviors of vacancy-type defects in Mg and N-implanted GaN were studied by positron annihilation. The major defect species in as-implanted samples was identified as Ga-vacancy (VGa)-type defects. For Mg-implanted GaN with sequential N-implantation after annealing above 1000°C, the defect species were vacancy clusters such as (VGaVN)3. Due to the downward shift of the Fermi level position resulting from a partial activation of Mg, the charge states of defects tended to become positive. For N-implanted GaN, the size of the vacancy cluster started to decrease above 1200°C annealing, which was attributed to recombinations between VNs coupled with VGas and excess N atoms. The impact of sequential N-implantations on vacancies in Mg-implanted GaN was found to be most pronounced when the ratio of the concentration of N to that of Mg was three.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1252-1257"},"PeriodicalIF":2.4,"publicationDate":"2025-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11142782","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper introduces the deposition of seed layers using a soaking technique to deposit dielectric layers on transition metal dichalcogenides (TMDs). This method addresses the bottleneck caused by the lack of dangling bonds in two-dimensional materials, which hinders the adsorption of precursors during the ALD process. We utilize the Hafnium soak technique, which can facilitate depositing a gate dielectric onto TMDs exhibiting smooth film characteristics and outstanding physical properties. We fabricate dual-gate devices using TMDs with an equivalent oxide thickness (EOT) of 1 nm and a subthreshold swing (S.S.) of 94 mV/dec. Additionally, the soaking technique promotes growth on both the top and back sides of two-dimensional materials, facilitating the development of gate-all-around (GAA) field-effect transistors.
{"title":"Low Temperature HfO₂ Interface Engineering in Dual-Gate and Gate-All-Around MoS₂ Transistors","authors":"Po-Heng Pao;Cheng-Yi Lin;Heng-Tung Hsu;Chao-Hsin Chien","doi":"10.1109/JEDS.2025.3600006","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3600006","url":null,"abstract":"This paper introduces the deposition of seed layers using a soaking technique to deposit dielectric layers on transition metal dichalcogenides (TMDs). This method addresses the bottleneck caused by the lack of dangling bonds in two-dimensional materials, which hinders the adsorption of precursors during the ALD process. We utilize the Hafnium soak technique, which can facilitate depositing a gate dielectric onto TMDs exhibiting smooth film characteristics and outstanding physical properties. We fabricate dual-gate devices using TMDs with an equivalent oxide thickness (EOT) of 1 nm and a subthreshold swing (S.S.) of 94 mV/dec. Additionally, the soaking technique promotes growth on both the top and back sides of two-dimensional materials, facilitating the development of gate-all-around (GAA) field-effect transistors.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1006-1009"},"PeriodicalIF":2.4,"publicationDate":"2025-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11129037","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145011290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-14DOI: 10.1109/JEDS.2025.3598941
Kaiyuan Lai;Yurong Liu;Ming Li;Dantong Wang;Yifan Li;Ruohe Yao;Kuiwei Geng;Weijian Liu
High-performance oxide semiconductor thin-film transistors (TFTs) are fabricated by forming a homojunction-structured channel layer with double-layer In-doped ZnO (IZO) with different In contents. The a-I0.9ZO/a-I0.5ZO TFTs exhibit a field-effect mobility ($mu_{mathrm{FE}}$ ) of $31.5 mathrm{~cm}^2 / mathrm{V} cdot mathrm{s}$ , an on-off current ratio ($I_{text {on }} / I_{text {off }}$ ) of $2 times 10^9$ , a subthreshold swing (SS) of 78 mV/decade, and a threshold voltage ($V_{text {th }}$ ) of 1.3 V. The $mu_{mathrm{FE}}$ is 2 times higher than that of the single-layer a-I0.5ZO TFT, which is attributed to the formation of the quasi two-dimensional electron gas (q-2DEG) due to the existence of the conduction band offset at the a-I0.9ZO/a-I0.5ZO homojunction interface, thus weakening the electron scattering. Moreover, the electrical properties of the bilayer-channel IZO TFTs were further enhanced by using CF4-plasma back-channel treatment and an Al2O3 thin film as back-channel passivation layer (BPL). The device exhibits a high $mu_{mathrm{FE}}$ of $50.4 mathrm{~cm}^2 / mathrm{V} cdot mathrm{s}$ , a high $mathrm{I}_{mathrm{on}} / mathrm{I}_{text {off }}$ of $6 times 10^9$ , and a low SS of 65 mV/decade. The threshold voltage shifts ($Delta V_{text {th }}$ ) were only -0.21 V and 0.29 V when the device was subjected to positive and negative gate-bias stresses for 10,000 s, respectively. The involving mechanism of the enhancement of device performance was elucidated in detail based on ultraviolet photoelectron spectroscopy (UPS), UV-visible spectroscopy, X-ray photoelectron spectroscopy (XPS), and capacitance-voltage (C-V) profiling technique analyses.
{"title":"Enhanced Mobility and Stability of Amorphous IZO TFTs With Homojunction Formation and Back-Channel Engineering","authors":"Kaiyuan Lai;Yurong Liu;Ming Li;Dantong Wang;Yifan Li;Ruohe Yao;Kuiwei Geng;Weijian Liu","doi":"10.1109/JEDS.2025.3598941","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3598941","url":null,"abstract":"High-performance oxide semiconductor thin-film transistors (TFTs) are fabricated by forming a homojunction-structured channel layer with double-layer In-doped ZnO (IZO) with different In contents. The a-I0.9ZO/a-I0.5ZO TFTs exhibit a field-effect mobility (<inline-formula> <tex-math>$mu_{mathrm{FE}}$ </tex-math></inline-formula>) of <inline-formula> <tex-math>$31.5 mathrm{~cm}^2 / mathrm{V} cdot mathrm{s}$ </tex-math></inline-formula>, an on-off current ratio (<inline-formula> <tex-math>$I_{text {on }} / I_{text {off }}$ </tex-math></inline-formula>) of <inline-formula> <tex-math>$2 times 10^9$ </tex-math></inline-formula>, a subthreshold swing (SS) of 78 mV/decade, and a threshold voltage (<inline-formula> <tex-math>$V_{text {th }}$ </tex-math></inline-formula>) of 1.3 V. The <inline-formula> <tex-math>$mu_{mathrm{FE}}$ </tex-math></inline-formula> is 2 times higher than that of the single-layer a-I0.5ZO TFT, which is attributed to the formation of the quasi two-dimensional electron gas (q-2DEG) due to the existence of the conduction band offset at the a-I0.9ZO/a-I0.5ZO homojunction interface, thus weakening the electron scattering. Moreover, the electrical properties of the bilayer-channel IZO TFTs were further enhanced by using CF4-plasma back-channel treatment and an Al2O3 thin film as back-channel passivation layer (BPL). The device exhibits a high <inline-formula> <tex-math>$mu_{mathrm{FE}}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$50.4 mathrm{~cm}^2 / mathrm{V} cdot mathrm{s}$ </tex-math></inline-formula>, a high <inline-formula> <tex-math>$mathrm{I}_{mathrm{on}} / mathrm{I}_{text {off }}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$6 times 10^9$ </tex-math></inline-formula>, and a low SS of 65 mV/decade. The threshold voltage shifts (<inline-formula> <tex-math>$Delta V_{text {th }}$ </tex-math></inline-formula>) were only -0.21 V and 0.29 V when the device was subjected to positive and negative gate-bias stresses for 10,000 s, respectively. The involving mechanism of the enhancement of device performance was elucidated in detail based on ultraviolet photoelectron spectroscopy (UPS), UV-visible spectroscopy, X-ray photoelectron spectroscopy (XPS), and capacitance-voltage (C-V) profiling technique analyses.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"997-1005"},"PeriodicalIF":2.4,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11124539","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For the first time, this study presents two novel vertical FET (VFET) structures and conducts a quantitative analysis to assess the competitiveness of VFET in comparison to two types of horizontal FET (HFET) which are nanosheet FET (NSFET) and forksheet FET (FSFET) targeting Angstrom nodes. The conventional VFET (VFETCON) design exhibits a larger footprint than FSFET, delivering an inferior performance even when optimized for gate length. By contrast, the novel fork-shaped channel VFET (VFETFS) demonstrates a 10.5% reduction in the effective area compared to VFETCON, achieving a smaller footprint than FSFET with a large contact poly pitch (CPP). Additionally, $mathrm { VFET_{FS}}$ offers enhanced performance over $mathrm { VFET_{CON}}$ due to reduced capacitance. However, $mathrm { VFET_{FS}}$ shows more effective area and has a significantly lower drive current (Ion) than FSFET with a small CPP. Strategies to expand the silicide area effectively improve $mathrm { I_{on}}$ by reducing parasitic resistance, enabling NFET $mathrm { VFET_{FS}}$ to outperform FSFET. However, for PFET, $mathrm { VFET_{FS}}$ employing enlarged silicide areas exhibits lower performance compared with FSFET owing to the more substantial impact of performance degradation under non-stress conditions. The secondary device architecture, $mathrm { VFET_{FS}}$ with back-side contact (VFETBSC), further decreases the footprint, significantly lowers parasitic RC, and shows great heat dissipation when it has a large BSC area. $mathrm { VFET_{BSC}}$ requires a smaller effective area than FSFET with a 42 nm CPP, and its average performance for N/PFET surpasses that of FSFET.
{"title":"Vertical FET Optimization at Angstrom Nodes: A Comparative Study With Horizontal FET","authors":"Junjong Lee;Jinsu Jeong;Seunghwan Lee;Sanguk Lee;Yonghwan Ahn;Minchan Kim;Gunryeol Cho;Sunmin Yeou;Rock-Hyun Baek","doi":"10.1109/JEDS.2025.3599105","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3599105","url":null,"abstract":"For the first time, this study presents two novel vertical FET (VFET) structures and conducts a quantitative analysis to assess the competitiveness of VFET in comparison to two types of horizontal FET (HFET) which are nanosheet FET (NSFET) and forksheet FET (FSFET) targeting Angstrom nodes. The conventional VFET (VFETCON) design exhibits a larger footprint than FSFET, delivering an inferior performance even when optimized for gate length. By contrast, the novel fork-shaped channel VFET (VFETFS) demonstrates a 10.5% reduction in the effective area compared to VFETCON, achieving a smaller footprint than FSFET with a large contact poly pitch (CPP). Additionally, <inline-formula> <tex-math>$mathrm { VFET_{FS}}$ </tex-math></inline-formula> offers enhanced performance over <inline-formula> <tex-math>$mathrm { VFET_{CON}}$ </tex-math></inline-formula> due to reduced capacitance. However, <inline-formula> <tex-math>$mathrm { VFET_{FS}}$ </tex-math></inline-formula> shows more effective area and has a significantly lower drive current (Ion) than FSFET with a small CPP. Strategies to expand the silicide area effectively improve <inline-formula> <tex-math>$mathrm { I_{on}}$ </tex-math></inline-formula> by reducing parasitic resistance, enabling NFET <inline-formula> <tex-math>$mathrm { VFET_{FS}}$ </tex-math></inline-formula> to outperform FSFET. However, for PFET, <inline-formula> <tex-math>$mathrm { VFET_{FS}}$ </tex-math></inline-formula> employing enlarged silicide areas exhibits lower performance compared with FSFET owing to the more substantial impact of performance degradation under non-stress conditions. The secondary device architecture, <inline-formula> <tex-math>$mathrm { VFET_{FS}}$ </tex-math></inline-formula> with back-side contact (VFETBSC), further decreases the footprint, significantly lowers parasitic RC, and shows great heat dissipation when it has a large BSC area. <inline-formula> <tex-math>$mathrm { VFET_{BSC}}$ </tex-math></inline-formula> requires a smaller effective area than FSFET with a 42 nm CPP, and its average performance for N/PFET surpasses that of FSFET.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1010-1017"},"PeriodicalIF":2.4,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11124538","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144998226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The reliability of flexible p-type low temperature poly-silicon thin film transistors (TFTs) under sole illumination stress was investigated. As the TFT was exposed to illumination, the transfer characteristic curves of the TFTs shifted positively, accompanied by an increase in the off-state current. Through altering the wavelength and intensity of the light, the degradation mechanism for TFTs under illumination stresses can be attributed to photoexcited carriers and residual hydrogen diffusion from the Si3N4 layer to air, leading to a forward shift in the threshold voltage. Moreover, TFTs exposed to the air for an extended period can also effectively remove residual hydrogen in the silicon nitride layer, thereby effectively suppressing photoinduced degradation of the device and improving its reliability.
{"title":"Threshold Voltage Shift of Flexible P-Type Poly-Silicon Thin Film Transistors Under Illumination Stress","authors":"Weipeng Ji;Huaisheng Wang;Mingxiang Wang;Dongli Zhang;Nannan Lv;Qi Shan","doi":"10.1109/JEDS.2025.3595808","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3595808","url":null,"abstract":"The reliability of flexible p-type low temperature poly-silicon thin film transistors (TFTs) under sole illumination stress was investigated. As the TFT was exposed to illumination, the transfer characteristic curves of the TFTs shifted positively, accompanied by an increase in the off-state current. Through altering the wavelength and intensity of the light, the degradation mechanism for TFTs under illumination stresses can be attributed to photoexcited carriers and residual hydrogen diffusion from the Si3N4 layer to air, leading to a forward shift in the threshold voltage. Moreover, TFTs exposed to the air for an extended period can also effectively remove residual hydrogen in the silicon nitride layer, thereby effectively suppressing photoinduced degradation of the device and improving its reliability.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"969-975"},"PeriodicalIF":2.4,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11112689","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144880438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-04DOI: 10.1109/JEDS.2025.3595614
Haechan Choi;Hyungcheol Shin
We introduce a compact model for characterizing the transient program operation of Gate-All-Around (GAA) Barrier-Engineered charge-trapping NAND flash (BE-CTNF) memory, especially in the FN-tunneling regime. Differing from prior models, our approach involves the calculation of threshold voltage shift attributed to each trapping layer, taking into account GAA structure of the cell and, at the same time, electron trapping within the oxide-nitride-oxide (ONO) tunneling layer. We validated our model through a comprehensive analysis of various physical parameters, with calibration to the results from the 3-D TCAD simulation.
{"title":"A Compact Model for Program Operation of Gate-All-Around Barrier-Engineered Charge-Trapping NAND Flash Memory in the FN-Tunneling Regime","authors":"Haechan Choi;Hyungcheol Shin","doi":"10.1109/JEDS.2025.3595614","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3595614","url":null,"abstract":"We introduce a compact model for characterizing the transient program operation of Gate-All-Around (GAA) Barrier-Engineered charge-trapping NAND flash (BE-CTNF) memory, especially in the FN-tunneling regime. Differing from prior models, our approach involves the calculation of threshold voltage shift attributed to each trapping layer, taking into account GAA structure of the cell and, at the same time, electron trapping within the oxide-nitride-oxide (ONO) tunneling layer. We validated our model through a comprehensive analysis of various physical parameters, with calibration to the results from the 3-D TCAD simulation.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1237-1242"},"PeriodicalIF":2.4,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11112690","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study investigates the frequency-dependent AC source-drain impedance (ZDS) in p-type junctionless gate-all-around (JLGAA) MOSFETs, and compares it to the DC source-drain resistance (RDS) under various biasing and stress conditions. The analysis focuses on how RDS and ZDS respond to different gate voltages, providing insight into their influence on device performance. While RDS is extracted from the ohmic region of conventional ID-VD measurements, ZDS is obtained directly using impedance analysis to capture frequency-dependent behavior. Results reveal that during turn-on, RDS is slightly lower than ZDS, although ZDS retains a mainly resistive profile. However, after reliability stress and near the quasi turn-off regime, a more pronounced divergence between RDS and ZDS is observed. This is attributed to reduced channel conductivity and increasing frequency-dependent effects. At higher reverse gate bias, ZDS exhibits noticeable capacitive behavior due to enhanced channel depletion, and this effect becomes more significant as the channel length increases. These findings highlight the critical role of ZDS in assessing the dynamic performance of JLGAA FETs. Unlike static RDS characterization, frequency-sensitive impedance measurements offer deeper insight into AC behavior, supporting more accurate modeling and optimization under time-varying or transient operating conditions.
{"title":"AC Impedance Compared to DC Characterization for Source-Drain Resistance in Junctionless Gate-All-Around MOSFETs","authors":"Hung-Hsi Chen;Ching-Lun Wang;Yao-Jen Lee;Wen-Teng Chang","doi":"10.1109/JEDS.2025.3595171","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3595171","url":null,"abstract":"This study investigates the frequency-dependent AC source-drain impedance (ZDS) in p-type junctionless gate-all-around (JLGAA) MOSFETs, and compares it to the DC source-drain resistance (RDS) under various biasing and stress conditions. The analysis focuses on how RDS and ZDS respond to different gate voltages, providing insight into their influence on device performance. While RDS is extracted from the ohmic region of conventional ID-VD measurements, ZDS is obtained directly using impedance analysis to capture frequency-dependent behavior. Results reveal that during turn-on, RDS is slightly lower than ZDS, although ZDS retains a mainly resistive profile. However, after reliability stress and near the quasi turn-off regime, a more pronounced divergence between RDS and ZDS is observed. This is attributed to reduced channel conductivity and increasing frequency-dependent effects. At higher reverse gate bias, ZDS exhibits noticeable capacitive behavior due to enhanced channel depletion, and this effect becomes more significant as the channel length increases. These findings highlight the critical role of ZDS in assessing the dynamic performance of JLGAA FETs. Unlike static RDS characterization, frequency-sensitive impedance measurements offer deeper insight into AC behavior, supporting more accurate modeling and optimization under time-varying or transient operating conditions.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"963-968"},"PeriodicalIF":2.4,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11111677","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144867644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：