The use of the plasma-enhanced atomic layer deposition (ALD) technique for the deposition of HfO2-based ferroelectrics has received attention in recent years primarily due to wake-up free operation. However, these studies have primarily focused on metal-ferroelectric-metal (MFM) structures. In this work, we investigate the characteristics of ferroelectric field-effect transistors (FEFETs) in which the ferroelectric Hf0.5Zr0.5O2 (HZO) gate stack is deposited using the plasma-enhanced atomic layer deposition (PEALD) technique. We observe that PEALD FEFET requires a higher write voltage for the same memory window compared to an equivalent FEFET with thermal ALD (THALD)-grown HZO. The increase in write voltage in PEALD FEFET occurs primarily due to the increase of the interfacial oxide layer using the plasma process. In addition, we observe that the SiO2 interfacial layer underneath the ferroelectric (FE) HZO layer eliminates the wake-up behavior in both THALD and PEALD FEFETs.
{"title":"Plasma-Enhanced Atomic Layer Deposition-Based Ferroelectric Field-Effect Transistors","authors":"Chinsung Park;Prasanna Venkat Ravindran;Dipjyoti Das;Priyankka Gundlapudi Ravikumar;Chengyang Zhang;Nashrah Afroze;Lance Fernandes;Yu Hsin Kuo;Jae Hur;Hang Chen;Mengkun Tian;Winston Chern;Shimeng Yu;Asif Islam Khan","doi":"10.1109/JEDS.2024.3434598","DOIUrl":"10.1109/JEDS.2024.3434598","url":null,"abstract":"The use of the plasma-enhanced atomic layer deposition (ALD) technique for the deposition of HfO2-based ferroelectrics has received attention in recent years primarily due to wake-up free operation. However, these studies have primarily focused on metal-ferroelectric-metal (MFM) structures. In this work, we investigate the characteristics of ferroelectric field-effect transistors (FEFETs) in which the ferroelectric Hf0.5Zr0.5O2 (HZO) gate stack is deposited using the plasma-enhanced atomic layer deposition (PEALD) technique. We observe that PEALD FEFET requires a higher write voltage for the same memory window compared to an equivalent FEFET with thermal ALD (THALD)-grown HZO. The increase in write voltage in PEALD FEFET occurs primarily due to the increase of the interfacial oxide layer using the plasma process. In addition, we observe that the SiO2 interfacial layer underneath the ferroelectric (FE) HZO layer eliminates the wake-up behavior in both THALD and PEALD FEFETs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10612817","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141867524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a high-performance and low-HCI (Hot carrier injection) degradation LDMOS (Lateral double diffused metal oxide semiconductor) device is introduced. It consists of an additional mini LOCOS (Local oxidation of silicon) field plate combined with a mini STI (Shallow trench isolation) field plate without an additional complex fabrication process. A series of devices have been fabricated, and the field plate corner profile is optimized. The proposed hybrid FP(Field plate) can effectively reduce the electric field peak, and the BV (Breakdown voltage) achieves as high as 78.9V while the ${R}_{{on}{,}{sp}}$ (Specific on-resistance) is as low as $69.1~{{mathrm { m}}Omega cdot }{mm}^{2}$ , which is 65.8% improved compared with conventional transistors. Meanwhile, the hybrid FP device owns much better HCI (Hot carrier injection) degradation performance on ${R}_{on,sp}$ , threshold voltage ${V}_{T}$ , and gate-drain capacitance ${C}_{GD}$ . The degradation of ${R}_{{on}{,}{sp}}$ is only 8.6% under ${I}_{d}$ mode stress while it is as high as 15.8% for the conventional devices. At on-state, ${C}_{GD}$ degradation is only 9.1% while it is nearly 59.9% in the traditional device. At high voltage application regions, the device exhibits nearly 0% ${C}_{GD}$ degradation while it is as high as 43.8% in the traditional device. The results indicate the device’s robustness in both DC (Direct current) applications and RF (Radio frequency) applications.
{"title":"A High-Performance and Low HCI Degradation LDMOS Device With a Hybrid Field Plate","authors":"Shaoxin Yu;Rongsheng Chen;Weiheng Shao;Weiming Yu;Xiaoyan Zhao;Zheng Chen;Weizhong Shan;Jenhao Cheng","doi":"10.1109/JEDS.2024.3433442","DOIUrl":"10.1109/JEDS.2024.3433442","url":null,"abstract":"In this paper, a high-performance and low-HCI (Hot carrier injection) degradation LDMOS (Lateral double diffused metal oxide semiconductor) device is introduced. It consists of an additional mini LOCOS (Local oxidation of silicon) field plate combined with a mini STI (Shallow trench isolation) field plate without an additional complex fabrication process. A series of devices have been fabricated, and the field plate corner profile is optimized. The proposed hybrid FP(Field plate) can effectively reduce the electric field peak, and the BV (Breakdown voltage) achieves as high as 78.9V while the \u0000<inline-formula> <tex-math>${R}_{{on}{,}{sp}}$ </tex-math></inline-formula>\u0000 (Specific on-resistance) is as low as \u0000<inline-formula> <tex-math>$69.1~{{mathrm { m}}Omega cdot }{mm}^{2}$ </tex-math></inline-formula>\u0000, which is 65.8% improved compared with conventional transistors. Meanwhile, the hybrid FP device owns much better HCI (Hot carrier injection) degradation performance on \u0000<inline-formula> <tex-math>${R}_{on,sp}$ </tex-math></inline-formula>\u0000, threshold voltage \u0000<inline-formula> <tex-math>${V}_{T}$ </tex-math></inline-formula>\u0000, and gate-drain capacitance \u0000<inline-formula> <tex-math>${C}_{GD}$ </tex-math></inline-formula>\u0000. The degradation of \u0000<inline-formula> <tex-math>${R}_{{on}{,}{sp}}$ </tex-math></inline-formula>\u0000 is only 8.6% under \u0000<inline-formula> <tex-math>${I}_{d}$ </tex-math></inline-formula>\u0000 mode stress while it is as high as 15.8% for the conventional devices. At on-state, \u0000<inline-formula> <tex-math>${C}_{GD}$ </tex-math></inline-formula>\u0000 degradation is only 9.1% while it is nearly 59.9% in the traditional device. At high voltage application regions, the device exhibits nearly 0% \u0000<inline-formula> <tex-math>${C}_{GD}$ </tex-math></inline-formula>\u0000 degradation while it is as high as 43.8% in the traditional device. The results indicate the device’s robustness in both DC (Direct current) applications and RF (Radio frequency) applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10609835","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141780663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-24DOI: 10.1109/JEDS.2024.3432971
Andreas Fuchsberger;Lukas Wind;Daniele Nazzari;Alexandra Dobler;Johannes Aberl;Enrique Prado Navarrete;Moritz Brehm;Lilian Vogl;Peter Schweizer;Sebastian Lellig;Xavier Maeder;Masiar Sistani;Walter M. Weber
A promising approach to advance electronics beyond static operations is to enhance state-ofthe- art systems by the functional diversification of transistors. Here, we experimentally demonstrate that an ultra-thin Ge channel implemented on a Si on insulator platform enables run-time switchable symmetric pand n-type field-effect transistor operability as well as the prominent feature of distinct room-temperature negative differential resistance. Temperature dependent bias spectroscopy is utilized to map electronic transport in these so called negative differential resistance mode reconfigurable transistors. Thereof, a profound understanding of the involved transport physics and electrostatic gating mechanisms is obtained and evaluated. Further, we show that a multi-gate negative differential resistance reconfigurable transistor can effectively replace a cascode of negative differential resistance devices, contributing to a smaller area footprint, and reduced latency of critical paths. Notably, the experimentally obtained multi-heterojunction transistors constitute the first chip-scale platform that combines efficient polarity control as well as sizeand energy-efficient room-temperature negative differential resistance, providing an inherent component of emerging neuromorphic computing.
通过晶体管的功能多样化来增强最先进的系统，是推动电子技术超越静态操作的一种可行方法。在这里，我们通过实验证明，在绝缘体上的硅平台上实现的超薄 Ge 沟道可以实现运行时可切换的对称 pand n 型场效应晶体管的可操作性，以及明显的室温负差分电阻的突出特点。利用随温度变化的偏压光谱绘制了这些所谓负差分电阻模式可重构晶体管中的电子传输图。由此，我们获得并评估了对相关传输物理学和静电门控机制的深刻理解。此外，我们还表明，多栅极负差分电阻可重构晶体管可以有效取代负差分电阻器件级联，从而缩小面积占用，并降低关键路径的延迟。值得注意的是，实验中获得的多异质结晶体管构成了第一个芯片级平台，它结合了高效极性控制以及尺寸和能效的室温负差分电阻，为新兴的神经形态计算提供了一个固有的组件。
{"title":"A Reconfigurable Ge Transistor Functionally Diversified by Negative Differential Resistance","authors":"Andreas Fuchsberger;Lukas Wind;Daniele Nazzari;Alexandra Dobler;Johannes Aberl;Enrique Prado Navarrete;Moritz Brehm;Lilian Vogl;Peter Schweizer;Sebastian Lellig;Xavier Maeder;Masiar Sistani;Walter M. Weber","doi":"10.1109/JEDS.2024.3432971","DOIUrl":"10.1109/JEDS.2024.3432971","url":null,"abstract":"A promising approach to advance electronics beyond static operations is to enhance state-ofthe- art systems by the functional diversification of transistors. Here, we experimentally demonstrate that an ultra-thin Ge channel implemented on a Si on insulator platform enables run-time switchable symmetric pand n-type field-effect transistor operability as well as the prominent feature of distinct room-temperature negative differential resistance. Temperature dependent bias spectroscopy is utilized to map electronic transport in these so called negative differential resistance mode reconfigurable transistors. Thereof, a profound understanding of the involved transport physics and electrostatic gating mechanisms is obtained and evaluated. Further, we show that a multi-gate negative differential resistance reconfigurable transistor can effectively replace a cascode of negative differential resistance devices, contributing to a smaller area footprint, and reduced latency of critical paths. Notably, the experimentally obtained multi-heterojunction transistors constitute the first chip-scale platform that combines efficient polarity control as well as sizeand energy-efficient room-temperature negative differential resistance, providing an inherent component of emerging neuromorphic computing.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10608155","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141780664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-22DOI: 10.1109/JEDS.2024.3432783
Shaocheng Li;Shu Yang;Zhao Han;Weibing Hao;Kuang Sheng;Guangwei Xu;Shibing Long
Abstract Selective-area p-type doping has been regarded as one of the primary challenges in vertical GaN junction-based power devices. Nickel oxide (NiO), serving as a natural p-type semiconductor without the requirement for sophisticated activation and enabling adjustable charge concentration, is potentially feasible to form pn hetero-junction in GaN power devices. In this work, a vertical GaN Schottky barrier diode (SBD) featuring hybrid p-NiO junction termination extension (HP-JTE) with fluorine (F)-implanted buried layer (FIBL) has been demonstrated. With FIBL incorporated underneath p-NiO in the termination region, the reverse leakage current can be effectively reduced by approximately 3 orders of magnitude. By virtue of photon emission microscopy measurements, it has also been verified that the light emission and leakage current through p-NiO termination region can be effectively suppressed by FIBL. Thanks to the HP-JTE structure as well as the nearly ideal Schottky interface, the vertical GaN SBD exhibits a high current swing of $sim 10^{13}$ , a low ideality factor of $sim 1.02$ , a low differential $R_{O N}$ of $sim 0.89 mathrm{~m} Omega cdot mathrm{cm}^2$ , a low forward voltage drop of $sim 0.8 mathrm{~V}$ (defined at $100 mathrm{~A} / mathrm{cm}^2$ ), and a breakdown voltage of $sim 780 mathrm{~V}$ (defined at $0.1 mathrm{~A} / mathrm{cm}^2$ ). The characterizations and findings in this work can provide valuable insights into the p-NiO/GaN hetero-junction-based power devices.
{"title":"Vertical GaN Schottky Barrier Diode With Hybrid P-NiO Junction Termination Extension","authors":"Shaocheng Li;Shu Yang;Zhao Han;Weibing Hao;Kuang Sheng;Guangwei Xu;Shibing Long","doi":"10.1109/JEDS.2024.3432783","DOIUrl":"10.1109/JEDS.2024.3432783","url":null,"abstract":"Abstract Selective-area p-type doping has been regarded as one of the primary challenges in vertical GaN junction-based power devices. Nickel oxide (NiO), serving as a natural p-type semiconductor without the requirement for sophisticated activation and enabling adjustable charge concentration, is potentially feasible to form pn hetero-junction in GaN power devices. In this work, a vertical GaN Schottky barrier diode (SBD) featuring hybrid p-NiO junction termination extension (HP-JTE) with fluorine (F)-implanted buried layer (FIBL) has been demonstrated. With FIBL incorporated underneath p-NiO in the termination region, the reverse leakage current can be effectively reduced by approximately 3 orders of magnitude. By virtue of photon emission microscopy measurements, it has also been verified that the light emission and leakage current through p-NiO termination region can be effectively suppressed by FIBL. Thanks to the HP-JTE structure as well as the nearly ideal Schottky interface, the vertical GaN SBD exhibits a high current swing of \u0000<inline-formula> <tex-math>$sim 10^{13}$ </tex-math></inline-formula>\u0000, a low ideality factor of \u0000<inline-formula> <tex-math>$sim 1.02$ </tex-math></inline-formula>\u0000, a low differential \u0000<inline-formula> <tex-math>$R_{O N}$ </tex-math></inline-formula>\u0000 of \u0000<inline-formula> <tex-math>$sim 0.89 mathrm{~m} Omega cdot mathrm{cm}^2$ </tex-math></inline-formula>\u0000, a low forward voltage drop of \u0000<inline-formula> <tex-math>$sim 0.8 mathrm{~V}$ </tex-math></inline-formula>\u0000 (defined at \u0000<inline-formula> <tex-math>$100 mathrm{~A} / mathrm{cm}^2$ </tex-math></inline-formula>\u0000), and a breakdown voltage of \u0000<inline-formula> <tex-math>$sim 780 mathrm{~V}$ </tex-math></inline-formula>\u0000 (defined at \u0000<inline-formula> <tex-math>$0.1 mathrm{~A} / mathrm{cm}^2$ </tex-math></inline-formula>\u0000). The characterizations and findings in this work can provide valuable insights into the p-NiO/GaN hetero-junction-based power devices.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10606442","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141786314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents an extensive characterization of the low-frequency noise (LFN) at room temperature (RT) and cryogenic temperature (4.2K) of 40-nm bulk-CMOS transistors. The noise is measured over a wide range of bias conditions and geometries to generate a comprehensive overview of LFN in this technology. While the RT results are in-line with the literature and the foundry models, the cryogenic behavior diverges in many aspects. These deviations include changes with respect to RT in magnitude and bias dependence that are conditional on transistor type and geometry, and even an additional systematic Lorentzian feature that is common among individual devices. Furthermore, we find the scaling of the average LFN with the area and its variability to be similar between RT and 4.2K, with the cryogenic scaling reported systematically for the first time. The findings suggest that, as no consistent decrease of LFN at lower temperatures is observed while the white noise is reduced, the impact of LFN for precision analog design at cryogenic temperatures gains a more predominant role.
{"title":"Cryogenic Characterization of Low-Frequency Noise in 40-nm CMOS","authors":"Gerd Kiene;Sadık İlik;Luigi Mastrodomenico;Masoud Babaie;Fabio Sebastiano","doi":"10.1109/JEDS.2024.3432283","DOIUrl":"10.1109/JEDS.2024.3432283","url":null,"abstract":"This paper presents an extensive characterization of the low-frequency noise (LFN) at room temperature (RT) and cryogenic temperature (4.2K) of 40-nm bulk-CMOS transistors. The noise is measured over a wide range of bias conditions and geometries to generate a comprehensive overview of LFN in this technology. While the RT results are in-line with the literature and the foundry models, the cryogenic behavior diverges in many aspects. These deviations include changes with respect to RT in magnitude and bias dependence that are conditional on transistor type and geometry, and even an additional systematic Lorentzian feature that is common among individual devices. Furthermore, we find the scaling of the average LFN with the area and its variability to be similar between RT and 4.2K, with the cryogenic scaling reported systematically for the first time. The findings suggest that, as no consistent decrease of LFN at lower temperatures is observed while the white noise is reduced, the impact of LFN for precision analog design at cryogenic temperatures gains a more predominant role.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10606256","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141780666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-18DOI: 10.1109/JEDS.2024.3431289
Jie Luo;Yanyu Yang;Gangping Yan;Chuqiao Niu;Yunjiao Bao;Yupeng Lu;Zhengying Jiao;Jinjuan Xiang;Guilei Wang;Gaobo Xu;Huaxiang Yin;Chao Zhao;Jun Luo
Amorphous oxide semiconductor-thin film transistors (AOS-TFTs) have attracted considerable attention due to their impressive performance in various applications. However, there is a limited amount of study available on the reliability of AOS-TFTs. This work investigates the endurance and reliability mechanisms of Indium Gallium Zinc Oxide (IGZO) and Indium Tin Oxide (ITO) TFTs. The devices underwent a range of test conditions to evaluate their endurance properties. The study utilized Zero-Bias Endurance Tests (ZBET) to examine the fluctuating behaviors of threshold voltage, revealing valuable insights into the causes of electrical instability. The study highlights the crucial importance of electron depletion and restoration dynamics in affecting the reliability of TFTs. Additionally, the study found differences in the performance of IGZO-TFTs and ITO-TFTs, suggesting that the differing features of the materials have a significant impact on the endurance and reliability of TFTs.
{"title":"The Endurance and Reliability Mechanisms Investigation of InGaZnO and InSnO Thin Film Transistors","authors":"Jie Luo;Yanyu Yang;Gangping Yan;Chuqiao Niu;Yunjiao Bao;Yupeng Lu;Zhengying Jiao;Jinjuan Xiang;Guilei Wang;Gaobo Xu;Huaxiang Yin;Chao Zhao;Jun Luo","doi":"10.1109/JEDS.2024.3431289","DOIUrl":"10.1109/JEDS.2024.3431289","url":null,"abstract":"Amorphous oxide semiconductor-thin film transistors (AOS-TFTs) have attracted considerable attention due to their impressive performance in various applications. However, there is a limited amount of study available on the reliability of AOS-TFTs. This work investigates the endurance and reliability mechanisms of Indium Gallium Zinc Oxide (IGZO) and Indium Tin Oxide (ITO) TFTs. The devices underwent a range of test conditions to evaluate their endurance properties. The study utilized Zero-Bias Endurance Tests (ZBET) to examine the fluctuating behaviors of threshold voltage, revealing valuable insights into the causes of electrical instability. The study highlights the crucial importance of electron depletion and restoration dynamics in affecting the reliability of TFTs. Additionally, the study found differences in the performance of IGZO-TFTs and ITO-TFTs, suggesting that the differing features of the materials have a significant impact on the endurance and reliability of TFTs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10604821","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141738247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The impacts of retrograde counter doping (RCD) profiles on low frequency noise (LFN) of buried channel (BC) PMOSFETs were investigated. RCD profiles were formed using heavy ion implantation. The RCD profile reduced LFN by more than 50%. The origin of LFN reduction in the RCD device was investigated using TCAD simulation. It was found that both RCD profile itself and the polarity of Si surface contributed to the deeper channel position and larger energy barrier between Si surface and channel position.
{"title":"Reduction of Low Frequency Noise of Buried Channel PMOSFETs With Retrograde Counter Doping Profiles","authors":"Shuntaro Fujii;Toshiro Sakamoto;Soichi Morita;Tsutomu Miyazaki","doi":"10.1109/JEDS.2024.3430308","DOIUrl":"10.1109/JEDS.2024.3430308","url":null,"abstract":"The impacts of retrograde counter doping (RCD) profiles on low frequency noise (LFN) of buried channel (BC) PMOSFETs were investigated. RCD profiles were formed using heavy ion implantation. The RCD profile reduced LFN by more than 50%. The origin of LFN reduction in the RCD device was investigated using TCAD simulation. It was found that both RCD profile itself and the polarity of Si surface contributed to the deeper channel position and larger energy barrier between Si surface and channel position.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10601688","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141738342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-15DOI: 10.1109/JEDS.2024.3428969
Yatexu Patel;Pouya Valizadeh
In this manuscript, we have investigated the impact of the scaling of the gate-source length (LGS) and gate length (LG) on the output characterises and gate-transconductance (Gm) linearity of metallic-face InAlN/AlN/GaN heterostructure field effect transistors (HFETs) having fin structures only under the gate and those having them stretched from source to drain. Evidence for both device types suggests that the downscaling of LGS and LG augments the electron velocity in the source-access region, as a result of which the higher carrier density under the gated-channel improves the maximum drain-current density but not necessarily the $G_{m}$ linearity of the device. It is shown that the devices having a planar and longer source access region are exhibiting relatively improved gate-transconductance linearity. This is suggested to be due to their almost constant source access resistance (Rs). In addition, the downscaling of the LG is observed to have a positive influence on device linearity. This observation could be due to the larger exposure to the drain-induced barrier lowering (DIBL) and the resulting rush of the carriers from the source access region to the gated-channel, leading to the suppression of the increasing $R_{s}$ at higher drain currents.
在本手稿中，我们研究了栅源长度（LGS）和栅极长度（LG）的缩放对仅在栅极下具有鳍状结构的金属面 InAlN/AlN/GaN 异质结构场效应晶体管（HFET）的输出特性和栅极电感（Gm）线性的影响。这两种器件类型的证据表明，LGS 和 LG 的缩减提高了源极接入区的电子速度，因此栅极沟道下更高的载流子密度提高了器件的最大漏极电流密度，但不一定提高了器件的 $G_{m}$ 线性度。研究表明，具有平面和较长源接入区的器件的栅极-电导线性度相对较高。这是因为它们的源接入电阻 (Rs) 几乎恒定。此外，还观察到 LG 的缩小对器件线性度产生了积极影响。这一现象可能是由于更大程度地暴露于漏极致势垒降低（DIBL），以及由此导致的载流子从源极接入区涌向栅极沟道，从而抑制了在更高漏极电流下不断增加的 $R_{s}$。
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Pub Date : 2024-07-11DOI: 10.1109/JEDS.2024.3425989
{"title":"Bridging the Data Gap in Photovoltaics with Synthetic Data Generation","authors":"","doi":"10.1109/JEDS.2024.3425989","DOIUrl":"10.1109/JEDS.2024.3425989","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10596105","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141608881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-05DOI: 10.1109/JEDS.2024.3424545
Wenyang Zhang;Li Lu;Chenfei Li;Weijie Jiang;Wenzhao Wang;Xingqiang Liu;Ablat Abliz;Da Wan
Herein, highly stable nitrogen (N) doped amorphous indium gallium tin oxide (a-IGTO) thinfilm transistors (TFTs) are prepared and the effects of N-doping are investigated. Compared with undoped a-IGTO TFTs, a-IGTO TFTs with 6 min N plasma treatment exhibit superior bias stress stability and a threshold voltages ( $V_{mathrm {th}}$ ) closer to 0 V with almost no decline in mobility. In particular, the positive/negative bias stress threshold shift of N-doped a-IGTO TFTs is substantially reduced in both dark and light environment. The X-ray photoelectron spectroscopy analysis (XPS) and low frequency noise (LFN) are employed to study the mechanism of N-doping in a-IGTO TFTs. The XPS results indicate that appropriate amount of N-doping could enhance the bias stress stability and control the $V_{mathrm {th}}$ efficiently by passivating the defects such as oxygen vacancy in a-IGTO films. The LFN results illustrate that the average interfacial trap density could be reduced by N-doping. Overall, the strategy presented here is effective for preparing a-IGTO TFTs with enhanced stability for potential applications in future optoelectronic displays.
本文制备了高度稳定的氮（N）掺杂非晶铟镓锡氧化物（a-IGTO）薄膜晶体管（TFT），并研究了氮掺杂的影响。与未掺杂的 a-IGTO TFT 相比，经过 6 分钟 N 等离子体处理的 a-IGTO TFT 具有优异的偏压稳定性，阈值电压（$V_{mathrm {th}}$ ）接近 0 V，且迁移率几乎没有下降。特别是，掺杂 N 的 a-IGTO TFT 的正/负偏压阈值偏移在黑暗和光明环境中都大幅降低。X 射线光电子能谱分析（XPS）和低频噪声（LFN）被用来研究 a-IGTO TFT 中 N 掺杂的机理。XPS 结果表明，通过钝化 a-IGTO 薄膜中的氧空位等缺陷，适量的 N 掺杂可以增强偏压稳定性并有效控制 $V_{mmathrm {th}}$。LFN 结果表明，N 掺杂可以降低平均界面陷阱密度。总之，本文介绍的策略能有效制备出稳定性更强的 a-IGTO TFT，有望应用于未来的光电显示领域。
{"title":"Study of Highly Stable Nitrogen-Doped a-InGaSnO Thin-Film Transistors","authors":"Wenyang Zhang;Li Lu;Chenfei Li;Weijie Jiang;Wenzhao Wang;Xingqiang Liu;Ablat Abliz;Da Wan","doi":"10.1109/JEDS.2024.3424545","DOIUrl":"10.1109/JEDS.2024.3424545","url":null,"abstract":"Herein, highly stable nitrogen (N) doped amorphous indium gallium tin oxide (a-IGTO) thinfilm transistors (TFTs) are prepared and the effects of N-doping are investigated. Compared with undoped a-IGTO TFTs, a-IGTO TFTs with 6 min N plasma treatment exhibit superior bias stress stability and a threshold voltages (\u0000<inline-formula> <tex-math>$V_{mathrm {th}}$ </tex-math></inline-formula>\u0000) closer to 0 V with almost no decline in mobility. In particular, the positive/negative bias stress threshold shift of N-doped a-IGTO TFTs is substantially reduced in both dark and light environment. The X-ray photoelectron spectroscopy analysis (XPS) and low frequency noise (LFN) are employed to study the mechanism of N-doping in a-IGTO TFTs. The XPS results indicate that appropriate amount of N-doping could enhance the bias stress stability and control the \u0000<inline-formula> <tex-math>$V_{mathrm {th}}$ </tex-math></inline-formula>\u0000 efficiently by passivating the defects such as oxygen vacancy in a-IGTO films. The LFN results illustrate that the average interfacial trap density could be reduced by N-doping. Overall, the strategy presented here is effective for preparing a-IGTO TFTs with enhanced stability for potential applications in future optoelectronic displays.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10587190","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141572389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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