Pub Date : 2025-11-04DOI: 10.1109/JEDS.2025.3628873
Mohammad Masum Billah;Minkyu Chun;Md Delwar Hossain Chowdhury;Jin Jang;Moath Alathbah
We report the effect of secondary gate bias (both the top gate voltage, ${mathrm { V}}_{mathrm {TG}}{({mathrm { V}})}$ and bottom gate voltage ${mathrm { V}}_{mathrm {BG}}{({mathrm { V}}})$ on the temperature-dependent density of state (DOS) estimation in dual gate (DG) amorphous indium gallium zinc oxide (a−IGZO) thin-film transistors (TFTs). The measured transfer characteristics exhibit a negative shift with increasing secondary gate bias from 0 V to 15 V, which can be explained as the Fermi energy $({mathrm { E}}_{mathrm { F}})$ shift towards the conduction band $({mathrm { E}}_{mathrm { C}})$ edge. The extracted Meyer-Neldel energy $({mathrm { E}}_{mathrm {MN}})$ from temperature-dependent transfer characteristics of a−IGZO TFTs shows two trends depending on activation energy $({mathrm { E}}_{mathrm { A}})$ ; normal ${mathrm { E}}_{mathrm {MN}}~({mathrm { E}}_{mathrm { A}}{gt 0.1 {mathrm { eV}}})$ and inverse ${mathrm { E}}_{mathrm {MN}}~({mathrm { E}}_{mathrm { A}}{lt 0.1 {mathrm { eV}}})$ . The secondary gate bias-independent normal ${mathrm { E}}_{mathrm {MN}}{ sim 41}$ meV can be explained as the statistical shift of ${mathrm { E}}_{mathrm { F}}$ below${ }{mathrm { E}}_{mathrm { C}}$ , whereas, secondary gate bias-dependent inverse ${mathrm { E}}_{mathrm {MN}}$ increases with increasing secondary gate voltage (0 V to 15 V) and appears to be due to the increased contact resistance at source/drain regions, which is confirmed by TCAD simulation. The density of tail states as a function of energy (E) is obtained from the MN rule as ${sim }{3.2 times 10}^{19}$ $bullet $ $ ~{{mathrm { exp}}(- {mathrm { E}}/}{mathrm { W}}_{mathrm { T}})$ with ${mathrm { V}}_{mathrm {TG}}$ , ${sim }{5.4 times 10}^{19}$ $bullet $ $ ~{{mathrm { exp}}(- {mathrm { E}}/}{mathrm { W}}_{mathrm { T}})$ with ${mathrm { V}}_{mathrm {BG}}$ , and a tail state slope
{"title":"Extraction of Density of State of Dual Gate Amorphous In-Ga-Zn-O Transistors From Meyer-Neldel (MN) Analysis","authors":"Mohammad Masum Billah;Minkyu Chun;Md Delwar Hossain Chowdhury;Jin Jang;Moath Alathbah","doi":"10.1109/JEDS.2025.3628873","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3628873","url":null,"abstract":"We report the effect of secondary gate bias (both the top gate voltage, <inline-formula> <tex-math>${mathrm { V}}_{mathrm {TG}}{({mathrm { V}})}$ </tex-math></inline-formula> and bottom gate voltage <inline-formula> <tex-math>${mathrm { V}}_{mathrm {BG}}{({mathrm { V}}})$ </tex-math></inline-formula> on the temperature-dependent density of state (DOS) estimation in dual gate (DG) amorphous indium gallium zinc oxide (a−IGZO) thin-film transistors (TFTs). The measured transfer characteristics exhibit a negative shift with increasing secondary gate bias from 0 V to 15 V, which can be explained as the Fermi energy <inline-formula> <tex-math>$({mathrm { E}}_{mathrm { F}})$ </tex-math></inline-formula> shift towards the conduction band <inline-formula> <tex-math>$({mathrm { E}}_{mathrm { C}})$ </tex-math></inline-formula> edge. The extracted Meyer-Neldel energy <inline-formula> <tex-math>$({mathrm { E}}_{mathrm {MN}})$ </tex-math></inline-formula> from temperature-dependent transfer characteristics of a−IGZO TFTs shows two trends depending on activation energy <inline-formula> <tex-math>$({mathrm { E}}_{mathrm { A}})$ </tex-math></inline-formula>; normal <inline-formula> <tex-math>${mathrm { E}}_{mathrm {MN}}~({mathrm { E}}_{mathrm { A}}{gt 0.1 {mathrm { eV}}})$ </tex-math></inline-formula> and inverse <inline-formula> <tex-math>${mathrm { E}}_{mathrm {MN}}~({mathrm { E}}_{mathrm { A}}{lt 0.1 {mathrm { eV}}})$ </tex-math></inline-formula>. The secondary gate bias-independent normal <inline-formula> <tex-math>${mathrm { E}}_{mathrm {MN}}{ sim 41}$ </tex-math></inline-formula> meV can be explained as the statistical shift of <inline-formula> <tex-math>${mathrm { E}}_{mathrm { F}}$ </tex-math></inline-formula> below<inline-formula> <tex-math>${ }{mathrm { E}}_{mathrm { C}}$ </tex-math></inline-formula>, whereas, secondary gate bias-dependent inverse <inline-formula> <tex-math>${mathrm { E}}_{mathrm {MN}}$ </tex-math></inline-formula> increases with increasing secondary gate voltage (0 V to 15 V) and appears to be due to the increased contact resistance at source/drain regions, which is confirmed by TCAD simulation. The density of tail states as a function of energy (E) is obtained from the MN rule as <inline-formula> <tex-math>${sim }{3.2 times 10}^{19}$ </tex-math></inline-formula><inline-formula> <tex-math>$bullet $ </tex-math></inline-formula><inline-formula> <tex-math>$ ~{{mathrm { exp}}(- {mathrm { E}}/}{mathrm { W}}_{mathrm { T}})$ </tex-math></inline-formula> with <inline-formula> <tex-math>${mathrm { V}}_{mathrm {TG}}$ </tex-math></inline-formula>, <inline-formula> <tex-math>${sim }{5.4 times 10}^{19}$ </tex-math></inline-formula><inline-formula> <tex-math>$bullet $ </tex-math></inline-formula><inline-formula> <tex-math>$ ~{{mathrm { exp}}(- {mathrm { E}}/}{mathrm { W}}_{mathrm { T}})$ </tex-math></inline-formula> with <inline-formula> <tex-math>${mathrm { V}}_{mathrm {BG}}$ </tex-math></inline-formula>, and a tail state slope <inline-formula> <t","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1125-1132"},"PeriodicalIF":2.4,"publicationDate":"2025-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11224921","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Atomic layer deposition (ALD) In2O3 is a promising candidate channel material for the back-end of line (BEOL) transistors due to its numerous advantages. However, its application is limited by the degenerative doping of the channel caused by the deposition of top-gate (TG) dielectrics. In this study, we utilized mild (the temperature remains < 150 ° C through gate-stack fabrication steps) ozone-based treatment to improve the interfacial properties of In2O3, resulting in high stability during HfO2 deposition. Our ozone-based In2O3 TG transistors have a high on current (Ion) ${=}284~mu $ A/$mu $ m, a low Subthreshold Swing (SS) = 63 mV/dec at V${_{text {d}}}{=}1$ V for L${_{text {ch}}}{=}1~mu $ m. Additionally, high field-effect mobility $(mu _{mathrm { FE}}){=}120$ cm2V−1s−1, small threshold voltage (VT) shift = –63 mV under positive stress voltage = 2 V, and VT shift = −88 mV from 25 ° C to 125 ° C are also achieved, demonstrating the great potential of ozone-based treatment for future In2O3 TG transistors.
{"title":"High Mobility and Robust Top-Gate In₂O₃ Thin Film Transistor by Ozone-Based Treatment","authors":"Ching-Shuan Huang;Tung-Cheng Shih;Che-Chi Shih;Wu-Wei Tsai;Chien-Wei Chen;Yu-Hsuan Yu;Wei-Yen Woon;Chao-Hsin Chien","doi":"10.1109/JEDS.2025.3627495","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3627495","url":null,"abstract":"Atomic layer deposition (ALD) In2O3 is a promising candidate channel material for the back-end of line (BEOL) transistors due to its numerous advantages. However, its application is limited by the degenerative doping of the channel caused by the deposition of top-gate (TG) dielectrics. In this study, we utilized mild (the temperature remains < 150 ° C through gate-stack fabrication steps) ozone-based treatment to improve the interfacial properties of In2O3, resulting in high stability during HfO2 deposition. Our ozone-based In2O3 TG transistors have a high on current (Ion) <inline-formula> <tex-math>${=}284~mu $ </tex-math></inline-formula>A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, a low Subthreshold Swing (SS) = 63 mV/dec at V<inline-formula> <tex-math>${_{text {d}}}{=}1$ </tex-math></inline-formula> V for L<inline-formula> <tex-math>${_{text {ch}}}{=}1~mu $ </tex-math></inline-formula>m. Additionally, high field-effect mobility <inline-formula> <tex-math>$(mu _{mathrm { FE}}){=}120$ </tex-math></inline-formula> cm2V−1s−1, small threshold voltage (VT) shift = –63 mV under positive stress voltage = 2 V, and VT shift = −88 mV from 25 ° C to 125 ° C are also achieved, demonstrating the great potential of ozone-based treatment for future In2O3 TG transistors.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1112-1119"},"PeriodicalIF":2.4,"publicationDate":"2025-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11222119","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-30DOI: 10.1109/JEDS.2025.3627211
Y. T. Zheng;H. L. Zhu;Y. K. Zhang;W. L. Liu;Q. Wang;X. Y. Chen;P. H. Sun;K. Q. Zhao;S. S. Lu;Y. D;B. H. Wang;J. B. Liu;G. B. Bai;Q. F. Jiang;X. B. He;J. Luo
We present dual Vertical C-Shaped-Channel Nanosheet Field-Effect Transistors (dVCNFETs), with a novel integration process aimed at advancing the scalability and performance of future CMOS technologies. The proposed method leverages epitaxial Si/SiGe/Si layers, enabling precise control over gate length and channel thickness. By incorporating spacer image transfer (SIT) and bidirectional cross-etching (BCE) techniques, dual-channel structures are formed with self-aligned high-k metal gates (HKMG). The dVCNFETs demonstrate impressive electrical performance with an on-state current (Idsat) of $442~mu $ A/$mu $ m, sub-threshold slope (SS) of 61.64 mV/dec, and a high Ion/Ioff ratio of $1.19times 10^{8}$ , showcasing superior short-channel control and device scalability. This integration technique, which could fabricate multiple channels, compatible with state-of-the-art CMOS fabrication processes, holds significant potential for high-density integrated circuits and future advanced logic applications.
{"title":"Fabrication of Dual Vertical C-Shaped-Channel Nanosheet FETs via a Novel Integration Process for High-Density, Scalable CMOS Applications","authors":"Y. T. Zheng;H. L. Zhu;Y. K. Zhang;W. L. Liu;Q. Wang;X. Y. Chen;P. H. Sun;K. Q. Zhao;S. S. Lu;Y. D;B. H. Wang;J. B. Liu;G. B. Bai;Q. F. Jiang;X. B. He;J. Luo","doi":"10.1109/JEDS.2025.3627211","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3627211","url":null,"abstract":"We present dual Vertical C-Shaped-Channel Nanosheet Field-Effect Transistors (dVCNFETs), with a novel integration process aimed at advancing the scalability and performance of future CMOS technologies. The proposed method leverages epitaxial Si/SiGe/Si layers, enabling precise control over gate length and channel thickness. By incorporating spacer image transfer (SIT) and bidirectional cross-etching (BCE) techniques, dual-channel structures are formed with self-aligned high-k metal gates (HKMG). The dVCNFETs demonstrate impressive electrical performance with an on-state current (Idsat) of <inline-formula> <tex-math>$442~mu $ </tex-math></inline-formula>A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, sub-threshold slope (SS) of 61.64 mV/dec, and a high Ion/Ioff ratio of <inline-formula> <tex-math>$1.19times 10^{8}$ </tex-math></inline-formula>, showcasing superior short-channel control and device scalability. This integration technique, which could fabricate multiple channels, compatible with state-of-the-art CMOS fabrication processes, holds significant potential for high-density integrated circuits and future advanced logic applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1133-1137"},"PeriodicalIF":2.4,"publicationDate":"2025-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11222666","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145560722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
1.2 kV 4H-SiC MOSFETs with linear, hexagonal, square, and ladder topological layouts were designed with uniform design rules and fabricated simultaneously on the same wafer. These devices were then diced and packaged to conduct a comprehensive analysis between their static and dynamic electrical characteristics. 3D TCAD simulations for each device type were also conducted to further elucidate the trends observed with the experimental data. The ladder and hexagonal MOSFET designs both demonstrated the greatest improvement in specific on-resistance (Ron,sp) with no degradation in the breakdown voltage. However, 3D simulations of the blocking characteristics reveal that the maximum electric field in the oxide and 4H-SiC are greater in the hexagonal design due to the corner in the JFET region. Furthermore, the MOSFET with the ladder design demonstrates superior switching characteristics compared to the hexagonal design due to its large increase in channel density and minimal increase in JFET density, with a (FOM[Ciss/Crss]) 2x greater than the Nominal MOSFET, where Ciss is the input capacitance and Cgd is the reverse transfer capacitance.
{"title":"Comprehensive Experimental and Simulation Study of Six 1.2 kV SiC MOSFET Layout Topologies","authors":"Skylar deBoer;Seung Yup Jang;Adam Morgan;Woongje Sung","doi":"10.1109/JEDS.2025.3624282","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3624282","url":null,"abstract":"1.2 kV 4H-SiC MOSFETs with linear, hexagonal, square, and ladder topological layouts were designed with uniform design rules and fabricated simultaneously on the same wafer. These devices were then diced and packaged to conduct a comprehensive analysis between their static and dynamic electrical characteristics. 3D TCAD simulations for each device type were also conducted to further elucidate the trends observed with the experimental data. The ladder and hexagonal MOSFET designs both demonstrated the greatest improvement in specific on-resistance (Ron,sp) with no degradation in the breakdown voltage. However, 3D simulations of the blocking characteristics reveal that the maximum electric field in the oxide and 4H-SiC are greater in the hexagonal design due to the corner in the JFET region. Furthermore, the MOSFET with the ladder design demonstrates superior switching characteristics compared to the hexagonal design due to its large increase in channel density and minimal increase in JFET density, with a (FOM[Ciss/Crss]) 2x greater than the Nominal MOSFET, where Ciss is the input capacitance and Cgd is the reverse transfer capacitance.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1103-1111"},"PeriodicalIF":2.4,"publicationDate":"2025-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11214226","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We investigate the leakage current density–voltage (J–V) characteristics and gettering behavior of metallic impurities using a pn-junction diode fabricated with hydrocarbon (C3H5)-molecular-ion-implanted epitaxial silicon wafer. The pn-junction diode with C3H5 molecular ion implantation reduced the reverse leakage current. Additionally, metallic impurities such as Cu, Fe, and Au, identified by Deep level transient spectroscopy (DLTS) analysis, and oxygen dissolved in the silicon substrate were gettered in the C3H5-molecular-ion-implanted region. Furthermore, it became clear that the gettering behavior of metallic impurities and oxygen competes with one another during the pn-junction fabrication process. These findings suggest that lowering the oxygen concentration in silicon substrates improves the gettering capacity of metallic impurities.
{"title":"Metallic Impurity Gettering Behavior of Hydrocarbon-Molecular-Ion-Implanted Epitaxial Silicon Wafer During the pn-Junction Diode Fabrication Process","authors":"Sho Nagatomo;Takeshi Kadono;Ryo Hirose;Koji Kobayashi;Shun Sasaki;Kazunari Kurita","doi":"10.1109/JEDS.2025.3624795","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3624795","url":null,"abstract":"We investigate the leakage current density–voltage (J–V) characteristics and gettering behavior of metallic impurities using a pn-junction diode fabricated with hydrocarbon (C3H5)-molecular-ion-implanted epitaxial silicon wafer. The pn-junction diode with C3H5 molecular ion implantation reduced the reverse leakage current. Additionally, metallic impurities such as Cu, Fe, and Au, identified by Deep level transient spectroscopy (DLTS) analysis, and oxygen dissolved in the silicon substrate were gettered in the C3H5-molecular-ion-implanted region. Furthermore, it became clear that the gettering behavior of metallic impurities and oxygen competes with one another during the pn-junction fabrication process. These findings suggest that lowering the oxygen concentration in silicon substrates improves the gettering capacity of metallic impurities.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1282-1287"},"PeriodicalIF":2.4,"publicationDate":"2025-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11215678","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-22DOI: 10.1109/JEDS.2025.3624015
Bertwin Bilgrim Otto Seibertz;Bernd Szyszka
This work investigates the capability of direct current (DC) excited hollow cathode gas flow sputtering (GFS) to contribute to the synthesis of high performing thin films for micro electronic applications. Therefore, high-k tantalum oxide (TaOx) was deposited by reactive GFS onto heavily doped silicon and characterized in metal-insulator-semiconductor capacitors. The influence of substrate bias conditions on material properties like density, microstructure, dielectric constant, breakdown voltage and leakage current is studied. TaOx deposited unbiased exhibits columnar growth, leading to high leakage currents and insufficient isolation. The oxygen flow only had small influence on this behavior. By adding substrate bias, additional energy is provided to the growing films. Direct current (DC) bias lead only to minor improvements. Applying pulsed DC bias significantly improved layer properties. For 15V pulsed DC bias as deposited, ultra smooth TaOx achieved a dielectric constant in the order of 30, breakdown field strength above 5 MV/cm-1 and leakage currents in the order of 10−8 A/cm-2. Increasing the bias voltage decreased the performance of the films. The breakdown voltage shifts towards smaller values, and the leakage current at 2 MV/cm-1 increases. The density seems to be unaffected, however the surface morphology becomes rougher.
本文研究了直流（DC）激励空心阴极气体流溅射（GFS）在微电子应用中合成高性能薄膜的能力。因此，利用反应性GFS将高钾氧化钽（TaOx）沉积在重掺杂硅上，并在金属-绝缘体-半导体电容器中进行表征。研究了衬底偏置条件对材料密度、微观结构、介电常数、击穿电压和漏电流等性能的影响。TaOx无偏沉积呈现柱状生长，导致高泄漏电流和隔离不足。氧气流量对这一行为的影响很小。通过增加衬底偏压，可以为生长中的薄膜提供额外的能量。直流电（DC）的偏置只导致了微小的改进。施加脉冲直流偏压显著改善了层的性能。对于沉积的15V脉冲直流偏置，超光滑TaOx的介电常数约为30，击穿场强高于5 MV/cm-1，泄漏电流约为10−8 a /cm-2。增加偏置电压会降低薄膜的性能。击穿电压向更小的值移动，2 MV/cm-1的泄漏电流增大。密度似乎不受影响，但表面形貌变得粗糙。
{"title":"Deposition of High-k Tantalum Oxide by DC Hollow Cathode Gas Flow Sputtering and the Influence of DC and Pulsed DC Substrate Bias","authors":"Bertwin Bilgrim Otto Seibertz;Bernd Szyszka","doi":"10.1109/JEDS.2025.3624015","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3624015","url":null,"abstract":"This work investigates the capability of direct current (DC) excited hollow cathode gas flow sputtering (GFS) to contribute to the synthesis of high performing thin films for micro electronic applications. Therefore, high-k tantalum oxide (TaOx) was deposited by reactive GFS onto heavily doped silicon and characterized in metal-insulator-semiconductor capacitors. The influence of substrate bias conditions on material properties like density, microstructure, dielectric constant, breakdown voltage and leakage current is studied. TaOx deposited unbiased exhibits columnar growth, leading to high leakage currents and insufficient isolation. The oxygen flow only had small influence on this behavior. By adding substrate bias, additional energy is provided to the growing films. Direct current (DC) bias lead only to minor improvements. Applying pulsed DC bias significantly improved layer properties. For 15V pulsed DC bias as deposited, ultra smooth TaOx achieved a dielectric constant in the order of 30, breakdown field strength above 5 MV/cm-1 and leakage currents in the order of 10−8 A/cm-2. Increasing the bias voltage decreased the performance of the films. The breakdown voltage shifts towards smaller values, and the leakage current at 2 MV/cm-1 increases. The density seems to be unaffected, however the surface morphology becomes rougher.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1088-1097"},"PeriodicalIF":2.4,"publicationDate":"2025-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11214222","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In recent years, h-BN has emerged as a promising candidate for direct thermal neutron detection due to its compactness, efficiency, and radiation resistance, offering an attractive solution for long-term safety monitoring in harsh environments such as nuclear reactors. In this research, a high-performance thermal neutron detector was prepared using h-BN single crystals synthesized via the metal flux method. The detector demonstrates a leakage current as low as 112 pA and a stable specific capacitance of 158 pF/cm2 at a bias voltage of 100 V, ensuring low-noise operation. Simulation results indicated that the products of the 10B(n, $alpha $ )7Li nuclear reaction could deposit sufficient energy within the h-BN layers; when the total thickness of h-BN was $160~mu $ m, the theoretical thermal neutron detection efficiency approached 49.5%. Beamline tests at the BL20 thermal neutron station of the China Spallation Neutron Source reveals that the actual thermal neutron detection efficiency of the detector reaches 9.9%. The thermal neutron test spectrum exhibits two prominent peaks, corresponding to the $alpha $ particles and 7Li ions produced by the nuclear reaction. These results indicate that the stacked structure significantly enhances the neutron absorption probability and promotes effective charge collection, further highlighting the great potential of metal flux grown h-BN single crystals in next-generation thermal neutron detection technologies.
近年来，h-BN因其结构紧凑、效率高、耐辐射等优点，成为直接热中子探测的理想选择，为核反应堆等恶劣环境下的长期安全监测提供了有吸引力的解决方案。本研究利用金属通量法合成的h-BN单晶制备了高性能热中子探测器。在100 V的偏置电压下，该检测器的漏电流低至112 pA，比电容稳定为158 pF/cm2，可确保低噪声工作。模拟结果表明，10B(n, $alpha $)7Li核反应产物能在h-BN层内沉积足够的能量；当h-BN总厚度为$160~mu $ m时，理论热中子探测效率接近49.5%. Beamline tests at the BL20 thermal neutron station of the China Spallation Neutron Source reveals that the actual thermal neutron detection efficiency of the detector reaches 9.9%. The thermal neutron test spectrum exhibits two prominent peaks, corresponding to the $alpha $ particles and 7Li ions produced by the nuclear reaction. These results indicate that the stacked structure significantly enhances the neutron absorption probability and promotes effective charge collection, further highlighting the great potential of metal flux grown h-BN single crystals in next-generation thermal neutron detection technologies.
{"title":"High Efficiency Thermal Neutron Detection Using Vertically Stacked h-BN Single Crystals","authors":"Deyu Wang;Dawei Guo;Ze Long;Jiajin Tai;Xiaochuan Xia;Bin Tang;Wei Jiang;Ruirui Fan;Hong Yin;Hongwei Liang","doi":"10.1109/JEDS.2025.3623794","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3623794","url":null,"abstract":"In recent years, h-BN has emerged as a promising candidate for direct thermal neutron detection due to its compactness, efficiency, and radiation resistance, offering an attractive solution for long-term safety monitoring in harsh environments such as nuclear reactors. In this research, a high-performance thermal neutron detector was prepared using h-BN single crystals synthesized via the metal flux method. The detector demonstrates a leakage current as low as 112 pA and a stable specific capacitance of 158 pF/cm2 at a bias voltage of 100 V, ensuring low-noise operation. Simulation results indicated that the products of the 10B(n, <inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>)7Li nuclear reaction could deposit sufficient energy within the h-BN layers; when the total thickness of h-BN was <inline-formula> <tex-math>$160~mu $ </tex-math></inline-formula>m, the theoretical thermal neutron detection efficiency approached 49.5%. Beamline tests at the BL20 thermal neutron station of the China Spallation Neutron Source reveals that the actual thermal neutron detection efficiency of the detector reaches 9.9%. The thermal neutron test spectrum exhibits two prominent peaks, corresponding to the <inline-formula> <tex-math>$alpha $ </tex-math></inline-formula> particles and 7Li ions produced by the nuclear reaction. These results indicate that the stacked structure significantly enhances the neutron absorption probability and promotes effective charge collection, further highlighting the great potential of metal flux grown h-BN single crystals in next-generation thermal neutron detection technologies.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1082-1087"},"PeriodicalIF":2.4,"publicationDate":"2025-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11208689","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145405312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-20DOI: 10.1109/JEDS.2025.3623692
Gyuhyeon Lee;Myeongsang Yun;Seongjae Cho;Myounggon Kang
This study proposes a method to optimize the charge transfer mechanism in synaptic devices, a practical core component of neuromorphic systems, by employing bandgap engineering (BE) with high-$k$ materials. The conventional Al2O3 blocking oxide was substituted with a single $rm HfO_{2}$ layer and a stacked HfO2/Al2O3 structure to enhance the program and erase characteristics. Simulation results indicate that the structures utilizing high-$k$ materials demonstrated a larger threshold voltage $(V_{mathrm { th}})$ shift during program operations compared with the conventional structure. This improvement is attributed to the increased electron acceleration and the reduction in equivalent oxide thickness (EOT) due to the high permittivity of high-$k$ materials. Moreover, a greater $V_{mathrm { th}}$ shift was documented during erase operations, which is explained by the band offset between the blocking oxide and the nitride trap layer. Consequently, the BE charge-trap flash device demonstrated an enhancement of 2.22 V in the memory window compared with device in the conventional structure.
{"title":"Bandgap-Engineered Side-Path Synaptic Device Utilizing High- κ Materials for Low-Power Operation","authors":"Gyuhyeon Lee;Myeongsang Yun;Seongjae Cho;Myounggon Kang","doi":"10.1109/JEDS.2025.3623692","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3623692","url":null,"abstract":"This study proposes a method to optimize the charge transfer mechanism in synaptic devices, a practical core component of neuromorphic systems, by employing bandgap engineering (BE) with high-<inline-formula> <tex-math>$k$ </tex-math></inline-formula> materials. The conventional Al2O3 blocking oxide was substituted with a single <inline-formula> <tex-math>$rm HfO_{2}$ </tex-math></inline-formula> layer and a stacked HfO2/Al2O3 structure to enhance the program and erase characteristics. Simulation results indicate that the structures utilizing high-<inline-formula> <tex-math>$k$ </tex-math></inline-formula> materials demonstrated a larger threshold voltage <inline-formula> <tex-math>$(V_{mathrm { th}})$ </tex-math></inline-formula> shift during program operations compared with the conventional structure. This improvement is attributed to the increased electron acceleration and the reduction in equivalent oxide thickness (EOT) due to the high permittivity of high-<inline-formula> <tex-math>$k$ </tex-math></inline-formula> materials. Moreover, a greater <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula> shift was documented during erase operations, which is explained by the band offset between the blocking oxide and the nitride trap layer. Consequently, the BE charge-trap flash device demonstrated an enhancement of 2.22 V in the memory window compared with device in the conventional structure.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1098-1102"},"PeriodicalIF":2.4,"publicationDate":"2025-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11208718","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The p-type doping of solid-phase crystallized molybdenum disulfide (MoS${}_{2}$ ) films deposited via radio-frequency magnetron sputtering has been achieved by nitrogen annealing accelerated by hydrogen using forming gas (3% H2/N${}_{2}$ ). The hydrogen reduces S-S and also Mo-S bondings on the PVD-MoS2 film surface formed by sulfur vapor annealing, allowing for the incorporation of nitrogen in the film and resulting in p-type doping. Based on the experimental results, the Fermi level of MoS2 film relative to valence band maximum shifted from 0.79 to 0.53 eV after forming gas annealing at 100°C. Thus, it is suggested that the nitrogen annealing accelerated by hydrogen, with careful consideration of the balance between the effects of S-S bonding reduction and nitrogen incorporation, serves as a non-destructive p-type doping method for solid-phase crystallized PVD-MoS2 films compatible with the complementary metal-oxide-semiconductor (CMOS) process.
{"title":"P-Type Doping of Solid-Phase Crystallized PVD-MoS₂ Film Using Nitrogen Annealing Accelerated by Hydrogen","authors":"Jaehyo Jang;Shinya Imai;Naoki Matsunaga;Soma Ito;Kaede Teraoka;Md Iftekharul Alam;Takuya Hoshii;Kuniyuki Kakushima;Akinobu Teramoto;Hitoshi Wakabayashi","doi":"10.1109/JEDS.2025.3619018","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3619018","url":null,"abstract":"The p-type doping of solid-phase crystallized molybdenum disulfide (MoS<inline-formula> <tex-math>${}_{2}$ </tex-math></inline-formula>) films deposited via radio-frequency magnetron sputtering has been achieved by nitrogen annealing accelerated by hydrogen using forming gas (3% H2/N<inline-formula> <tex-math>${}_{2}$ </tex-math></inline-formula>). The hydrogen reduces S-S and also Mo-S bondings on the PVD-MoS2 film surface formed by sulfur vapor annealing, allowing for the incorporation of nitrogen in the film and resulting in p-type doping. Based on the experimental results, the Fermi level of MoS2 film relative to valence band maximum shifted from 0.79 to 0.53 eV after forming gas annealing at 100°C. Thus, it is suggested that the nitrogen annealing accelerated by hydrogen, with careful consideration of the balance between the effects of S-S bonding reduction and nitrogen incorporation, serves as a non-destructive p-type doping method for solid-phase crystallized PVD-MoS2 films compatible with the complementary metal-oxide-semiconductor (CMOS) process.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1288-1298"},"PeriodicalIF":2.4,"publicationDate":"2025-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11196062","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) are beginning to be installed in electric vehicles (EVs), and the demand for reliability as well as chip performance is increasing. Generally, multiple chips are connected in parallel. Although SiC MOSFETs have a smaller temperature dependence of on-resistance <inline-formula> <tex-math>$(R_{mathrm { on}})$ </tex-math></inline-formula> than Si MOSFETs, they are prone to current imbalance due to the negative temperature dependence of the threshold voltage <inline-formula> <tex-math>$(V_{mathrm { th}})$ </tex-math></inline-formula>, which is also affected by the dispersion of <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula>, and is said to be a challenge for module stability and reliability <xref>[1]</xref>, <xref>[2]</xref>, <xref>[3]</xref>. To solve this problem, appropriate chip classification, addition of inductance, and devising a new gate driving method are being considered <xref>[4]</xref>, <xref>[5]</xref>, <xref>[6]</xref>. However, from the perspective of chip suppliers, ensuring uniformity of <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula> is the top priority. So far, the high electron trap density at the MOS interface of SiC MOSFETs has been a major obstacle to improving performance. Post oxidation annealing (POA) technology after gate oxidation has improved channel mobility by passivating electron traps <xref>[7]</xref>, and the channel resistance has been significantly reduced by increasing the channel density through the application of trench-type gates with sidewalls made of the crystal planes of {1-100} or {11-20} with the low electron trap density <xref>[8]</xref>, <xref>[9]</xref>, <xref>[10]</xref>. However, since the electron trap density is strongly dependent on the crystal plane orientation <xref>[11]</xref>, <xref>[12]</xref>, the interface charge density will vary if the crystal orientation of the MOS interface is misaligned. As a result, the angle misalignment of the trench sidewalls causes variations in <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula>. In response to this, we have developed a V-shaped trench MOSFET (VMOSFET) with sidewalls made of {0-33-8} planes, which have the smallest electron trap density <xref>[13]</xref>, <xref>[14]</xref>, <xref>[15]</xref>, <xref>[16]</xref>. Since V-shaped trenches are formed by a thermo-chemical etching in a chlorine gas ambient <xref>[17]</xref>, <xref>[18]</xref>, the crystal planes are naturally exposed according to the chemical properties of 4H-SiC, the crystal orientation of the MOS interface is not essentially misaligned. Therefore, it is possible to manufacture chips with small variations in <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula> and good reproducibility. In this article, we introduce the unique device structures and manufacturing processes that support the performance and reliability of the
{"title":"Key Technologies Supporting High Performance and Reliability of SiC VMOSFET","authors":"Takeyoshi Masuda;Yoshinori Hara;Tomoki Ikeda;Kosuke Uchida;Yu Saito;Shin Harada;Tomoaki Hatayama;Jun Wada;Toru Hiyoshi;Hirofumi Yamamoto;Masaki Furumai;Takao Kiyama;Heiji Watanabe","doi":"10.1109/JEDS.2025.3614628","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3614628","url":null,"abstract":"4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) are beginning to be installed in electric vehicles (EVs), and the demand for reliability as well as chip performance is increasing. Generally, multiple chips are connected in parallel. Although SiC MOSFETs have a smaller temperature dependence of on-resistance <inline-formula> <tex-math>$(R_{mathrm { on}})$ </tex-math></inline-formula> than Si MOSFETs, they are prone to current imbalance due to the negative temperature dependence of the threshold voltage <inline-formula> <tex-math>$(V_{mathrm { th}})$ </tex-math></inline-formula>, which is also affected by the dispersion of <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula>, and is said to be a challenge for module stability and reliability <xref>[1]</xref>, <xref>[2]</xref>, <xref>[3]</xref>. To solve this problem, appropriate chip classification, addition of inductance, and devising a new gate driving method are being considered <xref>[4]</xref>, <xref>[5]</xref>, <xref>[6]</xref>. However, from the perspective of chip suppliers, ensuring uniformity of <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula> is the top priority. So far, the high electron trap density at the MOS interface of SiC MOSFETs has been a major obstacle to improving performance. Post oxidation annealing (POA) technology after gate oxidation has improved channel mobility by passivating electron traps <xref>[7]</xref>, and the channel resistance has been significantly reduced by increasing the channel density through the application of trench-type gates with sidewalls made of the crystal planes of {1-100} or {11-20} with the low electron trap density <xref>[8]</xref>, <xref>[9]</xref>, <xref>[10]</xref>. However, since the electron trap density is strongly dependent on the crystal plane orientation <xref>[11]</xref>, <xref>[12]</xref>, the interface charge density will vary if the crystal orientation of the MOS interface is misaligned. As a result, the angle misalignment of the trench sidewalls causes variations in <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula>. In response to this, we have developed a V-shaped trench MOSFET (VMOSFET) with sidewalls made of {0-33-8} planes, which have the smallest electron trap density <xref>[13]</xref>, <xref>[14]</xref>, <xref>[15]</xref>, <xref>[16]</xref>. Since V-shaped trenches are formed by a thermo-chemical etching in a chlorine gas ambient <xref>[17]</xref>, <xref>[18]</xref>, the crystal planes are naturally exposed according to the chemical properties of 4H-SiC, the crystal orientation of the MOS interface is not essentially misaligned. Therefore, it is possible to manufacture chips with small variations in <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula> and good reproducibility. In this article, we introduce the unique device structures and manufacturing processes that support the performance and reliability of the","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1267-1275"},"PeriodicalIF":2.4,"publicationDate":"2025-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11182284","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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