Pub Date : 2025-08-14DOI: 10.1109/JEDS.2025.3598941
Kaiyuan Lai;Yurong Liu;Ming Li;Dantong Wang;Yifan Li;Ruohe Yao;Kuiwei Geng;Weijian Liu
High-performance oxide semiconductor thin-film transistors (TFTs) are fabricated by forming a homojunction-structured channel layer with double-layer In-doped ZnO (IZO) with different In contents. The a-I0.9ZO/a-I0.5ZO TFTs exhibit a field-effect mobility ($mu_{mathrm{FE}}$ ) of $31.5 mathrm{~cm}^2 / mathrm{V} cdot mathrm{s}$ , an on-off current ratio ($I_{text {on }} / I_{text {off }}$ ) of $2 times 10^9$ , a subthreshold swing (SS) of 78 mV/decade, and a threshold voltage ($V_{text {th }}$ ) of 1.3 V. The $mu_{mathrm{FE}}$ is 2 times higher than that of the single-layer a-I0.5ZO TFT, which is attributed to the formation of the quasi two-dimensional electron gas (q-2DEG) due to the existence of the conduction band offset at the a-I0.9ZO/a-I0.5ZO homojunction interface, thus weakening the electron scattering. Moreover, the electrical properties of the bilayer-channel IZO TFTs were further enhanced by using CF4-plasma back-channel treatment and an Al2O3 thin film as back-channel passivation layer (BPL). The device exhibits a high $mu_{mathrm{FE}}$ of $50.4 mathrm{~cm}^2 / mathrm{V} cdot mathrm{s}$ , a high $mathrm{I}_{mathrm{on}} / mathrm{I}_{text {off }}$ of $6 times 10^9$ , and a low SS of 65 mV/decade. The threshold voltage shifts ($Delta V_{text {th }}$ ) were only -0.21 V and 0.29 V when the device was subjected to positive and negative gate-bias stresses for 10,000 s, respectively. The involving mechanism of the enhancement of device performance was elucidated in detail based on ultraviolet photoelectron spectroscopy (UPS), UV-visible spectroscopy, X-ray photoelectron spectroscopy (XPS), and capacitance-voltage (C-V) profiling technique analyses.
{"title":"Enhanced Mobility and Stability of Amorphous IZO TFTs With Homojunction Formation and Back-Channel Engineering","authors":"Kaiyuan Lai;Yurong Liu;Ming Li;Dantong Wang;Yifan Li;Ruohe Yao;Kuiwei Geng;Weijian Liu","doi":"10.1109/JEDS.2025.3598941","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3598941","url":null,"abstract":"High-performance oxide semiconductor thin-film transistors (TFTs) are fabricated by forming a homojunction-structured channel layer with double-layer In-doped ZnO (IZO) with different In contents. The a-I0.9ZO/a-I0.5ZO TFTs exhibit a field-effect mobility (<inline-formula> <tex-math>$mu_{mathrm{FE}}$ </tex-math></inline-formula>) of <inline-formula> <tex-math>$31.5 mathrm{~cm}^2 / mathrm{V} cdot mathrm{s}$ </tex-math></inline-formula>, an on-off current ratio (<inline-formula> <tex-math>$I_{text {on }} / I_{text {off }}$ </tex-math></inline-formula>) of <inline-formula> <tex-math>$2 times 10^9$ </tex-math></inline-formula>, a subthreshold swing (SS) of 78 mV/decade, and a threshold voltage (<inline-formula> <tex-math>$V_{text {th }}$ </tex-math></inline-formula>) of 1.3 V. The <inline-formula> <tex-math>$mu_{mathrm{FE}}$ </tex-math></inline-formula> is 2 times higher than that of the single-layer a-I0.5ZO TFT, which is attributed to the formation of the quasi two-dimensional electron gas (q-2DEG) due to the existence of the conduction band offset at the a-I0.9ZO/a-I0.5ZO homojunction interface, thus weakening the electron scattering. Moreover, the electrical properties of the bilayer-channel IZO TFTs were further enhanced by using CF4-plasma back-channel treatment and an Al2O3 thin film as back-channel passivation layer (BPL). The device exhibits a high <inline-formula> <tex-math>$mu_{mathrm{FE}}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$50.4 mathrm{~cm}^2 / mathrm{V} cdot mathrm{s}$ </tex-math></inline-formula>, a high <inline-formula> <tex-math>$mathrm{I}_{mathrm{on}} / mathrm{I}_{text {off }}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$6 times 10^9$ </tex-math></inline-formula>, and a low SS of 65 mV/decade. The threshold voltage shifts (<inline-formula> <tex-math>$Delta V_{text {th }}$ </tex-math></inline-formula>) were only -0.21 V and 0.29 V when the device was subjected to positive and negative gate-bias stresses for 10,000 s, respectively. The involving mechanism of the enhancement of device performance was elucidated in detail based on ultraviolet photoelectron spectroscopy (UPS), UV-visible spectroscopy, X-ray photoelectron spectroscopy (XPS), and capacitance-voltage (C-V) profiling technique analyses.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"997-1005"},"PeriodicalIF":2.4,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11124539","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144914213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For the first time, this study presents two novel vertical FET (VFET) structures and conducts a quantitative analysis to assess the competitiveness of VFET in comparison to two types of horizontal FET (HFET) which are nanosheet FET (NSFET) and forksheet FET (FSFET) targeting Angstrom nodes. The conventional VFET (VFETCON) design exhibits a larger footprint than FSFET, delivering an inferior performance even when optimized for gate length. By contrast, the novel fork-shaped channel VFET (VFETFS) demonstrates a 10.5% reduction in the effective area compared to VFETCON, achieving a smaller footprint than FSFET with a large contact poly pitch (CPP). Additionally, $mathrm { VFET_{FS}}$ offers enhanced performance over $mathrm { VFET_{CON}}$ due to reduced capacitance. However, $mathrm { VFET_{FS}}$ shows more effective area and has a significantly lower drive current (Ion) than FSFET with a small CPP. Strategies to expand the silicide area effectively improve $mathrm { I_{on}}$ by reducing parasitic resistance, enabling NFET $mathrm { VFET_{FS}}$ to outperform FSFET. However, for PFET, $mathrm { VFET_{FS}}$ employing enlarged silicide areas exhibits lower performance compared with FSFET owing to the more substantial impact of performance degradation under non-stress conditions. The secondary device architecture, $mathrm { VFET_{FS}}$ with back-side contact (VFETBSC), further decreases the footprint, significantly lowers parasitic RC, and shows great heat dissipation when it has a large BSC area. $mathrm { VFET_{BSC}}$ requires a smaller effective area than FSFET with a 42 nm CPP, and its average performance for N/PFET surpasses that of FSFET.
{"title":"Vertical FET Optimization at Angstrom Nodes: A Comparative Study With Horizontal FET","authors":"Junjong Lee;Jinsu Jeong;Seunghwan Lee;Sanguk Lee;Yonghwan Ahn;Minchan Kim;Gunryeol Cho;Sunmin Yeou;Rock-Hyun Baek","doi":"10.1109/JEDS.2025.3599105","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3599105","url":null,"abstract":"For the first time, this study presents two novel vertical FET (VFET) structures and conducts a quantitative analysis to assess the competitiveness of VFET in comparison to two types of horizontal FET (HFET) which are nanosheet FET (NSFET) and forksheet FET (FSFET) targeting Angstrom nodes. The conventional VFET (VFETCON) design exhibits a larger footprint than FSFET, delivering an inferior performance even when optimized for gate length. By contrast, the novel fork-shaped channel VFET (VFETFS) demonstrates a 10.5% reduction in the effective area compared to VFETCON, achieving a smaller footprint than FSFET with a large contact poly pitch (CPP). Additionally, <inline-formula> <tex-math>$mathrm { VFET_{FS}}$ </tex-math></inline-formula> offers enhanced performance over <inline-formula> <tex-math>$mathrm { VFET_{CON}}$ </tex-math></inline-formula> due to reduced capacitance. However, <inline-formula> <tex-math>$mathrm { VFET_{FS}}$ </tex-math></inline-formula> shows more effective area and has a significantly lower drive current (Ion) than FSFET with a small CPP. Strategies to expand the silicide area effectively improve <inline-formula> <tex-math>$mathrm { I_{on}}$ </tex-math></inline-formula> by reducing parasitic resistance, enabling NFET <inline-formula> <tex-math>$mathrm { VFET_{FS}}$ </tex-math></inline-formula> to outperform FSFET. However, for PFET, <inline-formula> <tex-math>$mathrm { VFET_{FS}}$ </tex-math></inline-formula> employing enlarged silicide areas exhibits lower performance compared with FSFET owing to the more substantial impact of performance degradation under non-stress conditions. The secondary device architecture, <inline-formula> <tex-math>$mathrm { VFET_{FS}}$ </tex-math></inline-formula> with back-side contact (VFETBSC), further decreases the footprint, significantly lowers parasitic RC, and shows great heat dissipation when it has a large BSC area. <inline-formula> <tex-math>$mathrm { VFET_{BSC}}$ </tex-math></inline-formula> requires a smaller effective area than FSFET with a 42 nm CPP, and its average performance for N/PFET surpasses that of FSFET.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1010-1017"},"PeriodicalIF":2.4,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11124538","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144998226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The reliability of flexible p-type low temperature poly-silicon thin film transistors (TFTs) under sole illumination stress was investigated. As the TFT was exposed to illumination, the transfer characteristic curves of the TFTs shifted positively, accompanied by an increase in the off-state current. Through altering the wavelength and intensity of the light, the degradation mechanism for TFTs under illumination stresses can be attributed to photoexcited carriers and residual hydrogen diffusion from the Si3N4 layer to air, leading to a forward shift in the threshold voltage. Moreover, TFTs exposed to the air for an extended period can also effectively remove residual hydrogen in the silicon nitride layer, thereby effectively suppressing photoinduced degradation of the device and improving its reliability.
{"title":"Threshold Voltage Shift of Flexible P-Type Poly-Silicon Thin Film Transistors Under Illumination Stress","authors":"Weipeng Ji;Huaisheng Wang;Mingxiang Wang;Dongli Zhang;Nannan Lv;Qi Shan","doi":"10.1109/JEDS.2025.3595808","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3595808","url":null,"abstract":"The reliability of flexible p-type low temperature poly-silicon thin film transistors (TFTs) under sole illumination stress was investigated. As the TFT was exposed to illumination, the transfer characteristic curves of the TFTs shifted positively, accompanied by an increase in the off-state current. Through altering the wavelength and intensity of the light, the degradation mechanism for TFTs under illumination stresses can be attributed to photoexcited carriers and residual hydrogen diffusion from the Si3N4 layer to air, leading to a forward shift in the threshold voltage. Moreover, TFTs exposed to the air for an extended period can also effectively remove residual hydrogen in the silicon nitride layer, thereby effectively suppressing photoinduced degradation of the device and improving its reliability.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"969-975"},"PeriodicalIF":2.4,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11112689","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144880438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study investigates the frequency-dependent AC source-drain impedance (ZDS) in p-type junctionless gate-all-around (JLGAA) MOSFETs, and compares it to the DC source-drain resistance (RDS) under various biasing and stress conditions. The analysis focuses on how RDS and ZDS respond to different gate voltages, providing insight into their influence on device performance. While RDS is extracted from the ohmic region of conventional ID-VD measurements, ZDS is obtained directly using impedance analysis to capture frequency-dependent behavior. Results reveal that during turn-on, RDS is slightly lower than ZDS, although ZDS retains a mainly resistive profile. However, after reliability stress and near the quasi turn-off regime, a more pronounced divergence between RDS and ZDS is observed. This is attributed to reduced channel conductivity and increasing frequency-dependent effects. At higher reverse gate bias, ZDS exhibits noticeable capacitive behavior due to enhanced channel depletion, and this effect becomes more significant as the channel length increases. These findings highlight the critical role of ZDS in assessing the dynamic performance of JLGAA FETs. Unlike static RDS characterization, frequency-sensitive impedance measurements offer deeper insight into AC behavior, supporting more accurate modeling and optimization under time-varying or transient operating conditions.
{"title":"AC Impedance Compared to DC Characterization for Source-Drain Resistance in Junctionless Gate-All-Around MOSFETs","authors":"Hung-Hsi Chen;Ching-Lun Wang;Yao-Jen Lee;Wen-Teng Chang","doi":"10.1109/JEDS.2025.3595171","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3595171","url":null,"abstract":"This study investigates the frequency-dependent AC source-drain impedance (ZDS) in p-type junctionless gate-all-around (JLGAA) MOSFETs, and compares it to the DC source-drain resistance (RDS) under various biasing and stress conditions. The analysis focuses on how RDS and ZDS respond to different gate voltages, providing insight into their influence on device performance. While RDS is extracted from the ohmic region of conventional ID-VD measurements, ZDS is obtained directly using impedance analysis to capture frequency-dependent behavior. Results reveal that during turn-on, RDS is slightly lower than ZDS, although ZDS retains a mainly resistive profile. However, after reliability stress and near the quasi turn-off regime, a more pronounced divergence between RDS and ZDS is observed. This is attributed to reduced channel conductivity and increasing frequency-dependent effects. At higher reverse gate bias, ZDS exhibits noticeable capacitive behavior due to enhanced channel depletion, and this effect becomes more significant as the channel length increases. These findings highlight the critical role of ZDS in assessing the dynamic performance of JLGAA FETs. Unlike static RDS characterization, frequency-sensitive impedance measurements offer deeper insight into AC behavior, supporting more accurate modeling and optimization under time-varying or transient operating conditions.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"963-968"},"PeriodicalIF":2.4,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11111677","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144867644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper provides a comprehensive analysis of the DC and RF behavior of HBTs, spanning temperatures from 350 to 3.8 K. It underscores the necessity of detailed studies for the design of RF circuits for quantum computing, including LNAs, VCOs, and mixers, due to the absence of cryogenic models. The DC gain shows betas of 800 at room temperature (RT) and 3000 at 3.8 K. RF characterization indicates a maximum fT of 500 GHz at 3.8 K and 300 GHz at RT. The proposed figure-of-merit, (gm.fT/Ic), typically used in CMOS design, is explored across the temperature range. The study reveals a noise equivalent temperature of sub-1 K at 3.8 K with source matching. The noise behavior of Si/SiGe:C HBTs within $0.13~{mu }$ m BiCMOS technology is characterized over 293 to 4 K and 10 kHz to 12 GHz. The analysis shows a significant increase in the flicker noise coefficient, K, and corner frequency reduction at 4 K. The high frequency parameter fT reaches 500 GHz, demonstrating better performance compared to advanced CMOS nodes. This research supports the modeling of HBTs that are critical for circuits operating at cryogenic temperatures. These models are particularly beneficial for designing classical-to-quantum interfaces.
{"title":"Broadband Noise Characterization of SiGe HBTs Down to 4K","authors":"Jad Benserhir;Yating Zou;Hung-Chi Han;Yatao Peng;Edoardo Charbon","doi":"10.1109/JEDS.2025.3595576","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3595576","url":null,"abstract":"This paper provides a comprehensive analysis of the DC and RF behavior of HBTs, spanning temperatures from 350 to 3.8 K. It underscores the necessity of detailed studies for the design of RF circuits for quantum computing, including LNAs, VCOs, and mixers, due to the absence of cryogenic models. The DC gain shows betas of 800 at room temperature (RT) and 3000 at 3.8 K. RF characterization indicates a maximum fT of 500 GHz at 3.8 K and 300 GHz at RT. The proposed figure-of-merit, (gm.fT/Ic), typically used in CMOS design, is explored across the temperature range. The study reveals a noise equivalent temperature of sub-1 K at 3.8 K with source matching. The noise behavior of Si/SiGe:C HBTs within <inline-formula> <tex-math>$0.13~{mu }$ </tex-math></inline-formula>m BiCMOS technology is characterized over 293 to 4 K and 10 kHz to 12 GHz. The analysis shows a significant increase in the flicker noise coefficient, K, and corner frequency reduction at 4 K. The high frequency parameter fT reaches 500 GHz, demonstrating better performance compared to advanced CMOS nodes. This research supports the modeling of HBTs that are critical for circuits operating at cryogenic temperatures. These models are particularly beneficial for designing classical-to-quantum interfaces.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"983-996"},"PeriodicalIF":2.4,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11112660","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The aim of this study is to explore the electronic properties of the MoS2/ZnO heterostructure and their potential applications in semiconductor devices. We analyzed the impact of N/P doping on electronic properties of ZnO structures with different terminations using the Density Functional Theory-Non-Equilibrium Green’s Function (DFT-NEGF). H-passivation treatment significantly affects doping, enabling precise adjustment of interface charge distribution for improved electrical performance. Additionally, the transport properties of doped MoS2 devices have been significantly improved at different spacer lengths. Particularly under ballistic transport conditions, the current of the doped devices has increased by approximately four orders of magnitude compared to the undoped devices. These findings have important theoretical and practical implications for the design and optimization of high-performance electronic devices based on two-dimensional materials.
{"title":"Achieving N/P Doping of MoS₂ Through ZnO Interface Engineering in Heterostructures for Semiconductor Devices","authors":"Lijun Xu;Guohui Zhan;Kun Luo;Yukun Shi;Pengcong Mu;Yan Liu;Qinzhi Xu;Jiangtao Liu;Zhenhua Wu","doi":"10.1109/JEDS.2025.3594757","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3594757","url":null,"abstract":"The aim of this study is to explore the electronic properties of the MoS2/ZnO heterostructure and their potential applications in semiconductor devices. We analyzed the impact of N/P doping on electronic properties of ZnO structures with different terminations using the Density Functional Theory-Non-Equilibrium Green’s Function (DFT-NEGF). H-passivation treatment significantly affects doping, enabling precise adjustment of interface charge distribution for improved electrical performance. Additionally, the transport properties of doped MoS2 devices have been significantly improved at different spacer lengths. Particularly under ballistic transport conditions, the current of the doped devices has increased by approximately four orders of magnitude compared to the undoped devices. These findings have important theoretical and practical implications for the design and optimization of high-performance electronic devices based on two-dimensional materials.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"976-982"},"PeriodicalIF":2.4,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106822","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144880519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-01DOI: 10.1109/JEDS.2025.3594767
Zhao Li;Shaohua Zhou
In this paper, an analytical temperature-dependent I-V model of gallium nitride (GaN) highelectron- mobility transistors (HEMTs) is established by using the Gaussian function. Compared with Curtice, Angelov, and their improved models in the literature, the I-V model proposed in this paper has the characteristics of high modeling accuracy and fast modeling speed. For example, the 3rd order (Gm3) derivative modeling accuracy of the modified Curtice at -45 °C, 75 °C, and 175 °C is 13.81%, 12.09%, and 6.44%, respectively, while at the same temperature, the Gm3 modeling accuracy of the proposed I-V model is 0.77%, 0.52%, and 1.04%, respectively.
{"title":"Gaussian-Based Analytical Model for Temperature-Dependent I-V Characteristics of GaN HEMTs","authors":"Zhao Li;Shaohua Zhou","doi":"10.1109/JEDS.2025.3594767","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3594767","url":null,"abstract":"In this paper, an analytical temperature-dependent I-V model of gallium nitride (GaN) highelectron- mobility transistors (HEMTs) is established by using the Gaussian function. Compared with Curtice, Angelov, and their improved models in the literature, the I-V model proposed in this paper has the characteristics of high modeling accuracy and fast modeling speed. For example, the 3rd order (Gm3) derivative modeling accuracy of the modified Curtice at -45 °C, 75 °C, and 175 °C is 13.81%, 12.09%, and 6.44%, respectively, while at the same temperature, the Gm3 modeling accuracy of the proposed I-V model is 0.77%, 0.52%, and 1.04%, respectively.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"954-962"},"PeriodicalIF":2.4,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106827","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144867645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Editorial for the JEDS Special Issue for EDTM 2024","authors":"Nihar Ranjan Mohapatra;Shree Prakash Tiwari;Shubham Sahay;Deleep Nair;Saptarshi Das;Gauri Karve;Nagarajan Raghavan;Abu Sebastian;Tomoya Sanuki","doi":"10.1109/JEDS.2025.3564856","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3564856","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"659-660"},"PeriodicalIF":2.4,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106516","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we present self-heating (SH) characterization and modeling of 130 nm Bipolar-CMOS-DMOS (BCD) technology node multi-finger Laterally Diffused Metal-Oxide-Semiconductor (LDMOS) transistors using extensive DC and S-parameter measurements. To accurately capture the impact of SH across a wide frequency range, we use a fourth-order thermal network within the industry-standard Berkeley Short-channel IGFET (BSIM)-BULK model framework. Additionally, we analyze the frequency behavior of RF bulk multi-finger LDMOS transistors and capture parasitic effects due to substrate and gate network. Our findings provide significant insights into LDMOS transistors. In particular, increasing the finger count reduces thermal resistance (by 6.6 ° C/Watt). Understanding how thermal resistance varies with finger count allows designers to optimize LDMOS layouts and mitigate SH effects. This leads to improved thermal management and more efficient, reliable RF devices.
{"title":"Characterization and Modeling of SH in Multi-Finger RF LDMOS Transistors Using BSIM-BULK Model","authors":"Ayushi Sharma;Shivendra Singh Parihar;Anirban Kar;Weike Wang;Kimihiko Imura;Yogesh Singh Chauhan","doi":"10.1109/JEDS.2025.3593056","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3593056","url":null,"abstract":"In this work, we present self-heating (SH) characterization and modeling of 130 nm Bipolar-CMOS-DMOS (BCD) technology node multi-finger Laterally Diffused Metal-Oxide-Semiconductor (LDMOS) transistors using extensive DC and S-parameter measurements. To accurately capture the impact of SH across a wide frequency range, we use a fourth-order thermal network within the industry-standard Berkeley Short-channel IGFET (BSIM)-BULK model framework. Additionally, we analyze the frequency behavior of RF bulk multi-finger LDMOS transistors and capture parasitic effects due to substrate and gate network. Our findings provide significant insights into LDMOS transistors. In particular, increasing the finger count reduces thermal resistance (by 6.6 ° C/Watt). Understanding how thermal resistance varies with finger count allows designers to optimize LDMOS layouts and mitigate SH effects. This leads to improved thermal management and more efficient, reliable RF devices.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1243-1251"},"PeriodicalIF":2.4,"publicationDate":"2025-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11098471","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Through-silicon via (TSV) as a crucial interconnection microstructure in three-dimensional (3D) chip, have significantly enhanced device performance and reliability. However, the increasing interconnect density and operating frequency now pose substantial threats to TSVs’ thermal-mechanical and signal transmission reliability, leading to a reduction in the overall reliability of 3D chip. In this study, a novel TSV with silicon dioxide ring (SDR) structure is proposed, its anti-current leakage performance and transmission performance are proved to be superior than traditional TSV and their derivative. On the basis, the equivalent circuit model of the proposed TSV is established, and the influence of the location, height and thickness of SDR on the thermal-mechanical performance and signal integrity of the new TSV is deeply investigated through thermomechanical analysis, electromagnetic analysis and field-circuit collaborative analysis. Results show that SDR’s position, thickness, and height mainly affect TSV’s thermal stress distribution by changing the area enclosed by the SDR and the volume of the SDR itself, transverse thermal conductivity, and the heat storage capacity. A moderate increase in the distance between SDR and the Cu column can enhance insertion loss in direct current (DC) condition. The inner diameter, thickness and height of SDR have different influence mechanisms on the integrity of TSV. These findings provide valuable guidance for TSV optimization and reliability analysis.
{"title":"Silicon Dioxide Ring Innovations in TSV Structures: Analysis of Thermal-Mechanical and Signal Integrity for 3-D Chip Applications","authors":"Kaihong Hou;Zhengwei Fan;Yonggui Chen;Shufeng Zhang;Yashun Wang;Xun Chen","doi":"10.1109/JEDS.2025.3592893","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3592893","url":null,"abstract":"Through-silicon via (TSV) as a crucial interconnection microstructure in three-dimensional (3D) chip, have significantly enhanced device performance and reliability. However, the increasing interconnect density and operating frequency now pose substantial threats to TSVs’ thermal-mechanical and signal transmission reliability, leading to a reduction in the overall reliability of 3D chip. In this study, a novel TSV with silicon dioxide ring (SDR) structure is proposed, its anti-current leakage performance and transmission performance are proved to be superior than traditional TSV and their derivative. On the basis, the equivalent circuit model of the proposed TSV is established, and the influence of the location, height and thickness of SDR on the thermal-mechanical performance and signal integrity of the new TSV is deeply investigated through thermomechanical analysis, electromagnetic analysis and field-circuit collaborative analysis. Results show that SDR’s position, thickness, and height mainly affect TSV’s thermal stress distribution by changing the area enclosed by the SDR and the volume of the SDR itself, transverse thermal conductivity, and the heat storage capacity. A moderate increase in the distance between SDR and the Cu column can enhance insertion loss in direct current (DC) condition. The inner diameter, thickness and height of SDR have different influence mechanisms on the integrity of TSV. These findings provide valuable guidance for TSV optimization and reliability analysis.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"937-946"},"PeriodicalIF":2.4,"publicationDate":"2025-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11098466","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144852700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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