This study investigates the frequency-dependent AC source-drain impedance (ZDS) in p-type junctionless gate-all-around (JLGAA) MOSFETs, and compares it to the DC source-drain resistance (RDS) under various biasing and stress conditions. The analysis focuses on how RDS and ZDS respond to different gate voltages, providing insight into their influence on device performance. While RDS is extracted from the ohmic region of conventional ID-VD measurements, ZDS is obtained directly using impedance analysis to capture frequency-dependent behavior. Results reveal that during turn-on, RDS is slightly lower than ZDS, although ZDS retains a mainly resistive profile. However, after reliability stress and near the quasi turn-off regime, a more pronounced divergence between RDS and ZDS is observed. This is attributed to reduced channel conductivity and increasing frequency-dependent effects. At higher reverse gate bias, ZDS exhibits noticeable capacitive behavior due to enhanced channel depletion, and this effect becomes more significant as the channel length increases. These findings highlight the critical role of ZDS in assessing the dynamic performance of JLGAA FETs. Unlike static RDS characterization, frequency-sensitive impedance measurements offer deeper insight into AC behavior, supporting more accurate modeling and optimization under time-varying or transient operating conditions.
{"title":"AC Impedance Compared to DC Characterization for Source-Drain Resistance in Junctionless Gate-All-Around MOSFETs","authors":"Hung-Hsi Chen;Ching-Lun Wang;Yao-Jen Lee;Wen-Teng Chang","doi":"10.1109/JEDS.2025.3595171","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3595171","url":null,"abstract":"This study investigates the frequency-dependent AC source-drain impedance (ZDS) in p-type junctionless gate-all-around (JLGAA) MOSFETs, and compares it to the DC source-drain resistance (RDS) under various biasing and stress conditions. The analysis focuses on how RDS and ZDS respond to different gate voltages, providing insight into their influence on device performance. While RDS is extracted from the ohmic region of conventional ID-VD measurements, ZDS is obtained directly using impedance analysis to capture frequency-dependent behavior. Results reveal that during turn-on, RDS is slightly lower than ZDS, although ZDS retains a mainly resistive profile. However, after reliability stress and near the quasi turn-off regime, a more pronounced divergence between RDS and ZDS is observed. This is attributed to reduced channel conductivity and increasing frequency-dependent effects. At higher reverse gate bias, ZDS exhibits noticeable capacitive behavior due to enhanced channel depletion, and this effect becomes more significant as the channel length increases. These findings highlight the critical role of ZDS in assessing the dynamic performance of JLGAA FETs. Unlike static RDS characterization, frequency-sensitive impedance measurements offer deeper insight into AC behavior, supporting more accurate modeling and optimization under time-varying or transient operating conditions.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"963-968"},"PeriodicalIF":2.4,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11111677","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144867644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper provides a comprehensive analysis of the DC and RF behavior of HBTs, spanning temperatures from 350 to 3.8 K. It underscores the necessity of detailed studies for the design of RF circuits for quantum computing, including LNAs, VCOs, and mixers, due to the absence of cryogenic models. The DC gain shows betas of 800 at room temperature (RT) and 3000 at 3.8 K. RF characterization indicates a maximum fT of 500 GHz at 3.8 K and 300 GHz at RT. The proposed figure-of-merit, (gm.fT/Ic), typically used in CMOS design, is explored across the temperature range. The study reveals a noise equivalent temperature of sub-1 K at 3.8 K with source matching. The noise behavior of Si/SiGe:C HBTs within $0.13~{mu }$ m BiCMOS technology is characterized over 293 to 4 K and 10 kHz to 12 GHz. The analysis shows a significant increase in the flicker noise coefficient, K, and corner frequency reduction at 4 K. The high frequency parameter fT reaches 500 GHz, demonstrating better performance compared to advanced CMOS nodes. This research supports the modeling of HBTs that are critical for circuits operating at cryogenic temperatures. These models are particularly beneficial for designing classical-to-quantum interfaces.
{"title":"Broadband Noise Characterization of SiGe HBTs Down to 4K","authors":"Jad Benserhir;Yating Zou;Hung-Chi Han;Yatao Peng;Edoardo Charbon","doi":"10.1109/JEDS.2025.3595576","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3595576","url":null,"abstract":"This paper provides a comprehensive analysis of the DC and RF behavior of HBTs, spanning temperatures from 350 to 3.8 K. It underscores the necessity of detailed studies for the design of RF circuits for quantum computing, including LNAs, VCOs, and mixers, due to the absence of cryogenic models. The DC gain shows betas of 800 at room temperature (RT) and 3000 at 3.8 K. RF characterization indicates a maximum fT of 500 GHz at 3.8 K and 300 GHz at RT. The proposed figure-of-merit, (gm.fT/Ic), typically used in CMOS design, is explored across the temperature range. The study reveals a noise equivalent temperature of sub-1 K at 3.8 K with source matching. The noise behavior of Si/SiGe:C HBTs within <inline-formula> <tex-math>$0.13~{mu }$ </tex-math></inline-formula>m BiCMOS technology is characterized over 293 to 4 K and 10 kHz to 12 GHz. The analysis shows a significant increase in the flicker noise coefficient, K, and corner frequency reduction at 4 K. The high frequency parameter fT reaches 500 GHz, demonstrating better performance compared to advanced CMOS nodes. This research supports the modeling of HBTs that are critical for circuits operating at cryogenic temperatures. These models are particularly beneficial for designing classical-to-quantum interfaces.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"983-996"},"PeriodicalIF":2.4,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11112660","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The aim of this study is to explore the electronic properties of the MoS2/ZnO heterostructure and their potential applications in semiconductor devices. We analyzed the impact of N/P doping on electronic properties of ZnO structures with different terminations using the Density Functional Theory-Non-Equilibrium Green’s Function (DFT-NEGF). H-passivation treatment significantly affects doping, enabling precise adjustment of interface charge distribution for improved electrical performance. Additionally, the transport properties of doped MoS2 devices have been significantly improved at different spacer lengths. Particularly under ballistic transport conditions, the current of the doped devices has increased by approximately four orders of magnitude compared to the undoped devices. These findings have important theoretical and practical implications for the design and optimization of high-performance electronic devices based on two-dimensional materials.
{"title":"Achieving N/P Doping of MoS₂ Through ZnO Interface Engineering in Heterostructures for Semiconductor Devices","authors":"Lijun Xu;Guohui Zhan;Kun Luo;Yukun Shi;Pengcong Mu;Yan Liu;Qinzhi Xu;Jiangtao Liu;Zhenhua Wu","doi":"10.1109/JEDS.2025.3594757","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3594757","url":null,"abstract":"The aim of this study is to explore the electronic properties of the MoS2/ZnO heterostructure and their potential applications in semiconductor devices. We analyzed the impact of N/P doping on electronic properties of ZnO structures with different terminations using the Density Functional Theory-Non-Equilibrium Green’s Function (DFT-NEGF). H-passivation treatment significantly affects doping, enabling precise adjustment of interface charge distribution for improved electrical performance. Additionally, the transport properties of doped MoS2 devices have been significantly improved at different spacer lengths. Particularly under ballistic transport conditions, the current of the doped devices has increased by approximately four orders of magnitude compared to the undoped devices. These findings have important theoretical and practical implications for the design and optimization of high-performance electronic devices based on two-dimensional materials.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"976-982"},"PeriodicalIF":2.4,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106822","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144880519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-01DOI: 10.1109/JEDS.2025.3594767
Zhao Li;Shaohua Zhou
In this paper, an analytical temperature-dependent I-V model of gallium nitride (GaN) highelectron- mobility transistors (HEMTs) is established by using the Gaussian function. Compared with Curtice, Angelov, and their improved models in the literature, the I-V model proposed in this paper has the characteristics of high modeling accuracy and fast modeling speed. For example, the 3rd order (Gm3) derivative modeling accuracy of the modified Curtice at -45 °C, 75 °C, and 175 °C is 13.81%, 12.09%, and 6.44%, respectively, while at the same temperature, the Gm3 modeling accuracy of the proposed I-V model is 0.77%, 0.52%, and 1.04%, respectively.
{"title":"Gaussian-Based Analytical Model for Temperature-Dependent I-V Characteristics of GaN HEMTs","authors":"Zhao Li;Shaohua Zhou","doi":"10.1109/JEDS.2025.3594767","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3594767","url":null,"abstract":"In this paper, an analytical temperature-dependent I-V model of gallium nitride (GaN) highelectron- mobility transistors (HEMTs) is established by using the Gaussian function. Compared with Curtice, Angelov, and their improved models in the literature, the I-V model proposed in this paper has the characteristics of high modeling accuracy and fast modeling speed. For example, the 3rd order (Gm3) derivative modeling accuracy of the modified Curtice at -45 °C, 75 °C, and 175 °C is 13.81%, 12.09%, and 6.44%, respectively, while at the same temperature, the Gm3 modeling accuracy of the proposed I-V model is 0.77%, 0.52%, and 1.04%, respectively.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"954-962"},"PeriodicalIF":2.4,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106827","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144867645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Editorial for the JEDS Special Issue for EDTM 2024","authors":"Nihar Ranjan Mohapatra;Shree Prakash Tiwari;Shubham Sahay;Deleep Nair;Saptarshi Das;Gauri Karve;Nagarajan Raghavan;Abu Sebastian;Tomoya Sanuki","doi":"10.1109/JEDS.2025.3564856","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3564856","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"659-660"},"PeriodicalIF":2.4,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11106516","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we present self-heating (SH) characterization and modeling of 130 nm Bipolar-CMOS-DMOS (BCD) technology node multi-finger Laterally Diffused Metal-Oxide-Semiconductor (LDMOS) transistors using extensive DC and S-parameter measurements. To accurately capture the impact of SH across a wide frequency range, we use a fourth-order thermal network within the industry-standard Berkeley Short-channel IGFET (BSIM)-BULK model framework. Additionally, we analyze the frequency behavior of RF bulk multi-finger LDMOS transistors and capture parasitic effects due to substrate and gate network. Our findings provide significant insights into LDMOS transistors. In particular, increasing the finger count reduces thermal resistance (by 6.6 ° C/Watt). Understanding how thermal resistance varies with finger count allows designers to optimize LDMOS layouts and mitigate SH effects. This leads to improved thermal management and more efficient, reliable RF devices.
{"title":"Characterization and Modeling of SH in Multi-Finger RF LDMOS Transistors Using BSIM-BULK Model","authors":"Ayushi Sharma;Shivendra Singh Parihar;Anirban Kar;Weike Wang;Kimihiko Imura;Yogesh Singh Chauhan","doi":"10.1109/JEDS.2025.3593056","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3593056","url":null,"abstract":"In this work, we present self-heating (SH) characterization and modeling of 130 nm Bipolar-CMOS-DMOS (BCD) technology node multi-finger Laterally Diffused Metal-Oxide-Semiconductor (LDMOS) transistors using extensive DC and S-parameter measurements. To accurately capture the impact of SH across a wide frequency range, we use a fourth-order thermal network within the industry-standard Berkeley Short-channel IGFET (BSIM)-BULK model framework. Additionally, we analyze the frequency behavior of RF bulk multi-finger LDMOS transistors and capture parasitic effects due to substrate and gate network. Our findings provide significant insights into LDMOS transistors. In particular, increasing the finger count reduces thermal resistance (by 6.6 ° C/Watt). Understanding how thermal resistance varies with finger count allows designers to optimize LDMOS layouts and mitigate SH effects. This leads to improved thermal management and more efficient, reliable RF devices.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1243-1251"},"PeriodicalIF":2.4,"publicationDate":"2025-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11098471","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Through-silicon via (TSV) as a crucial interconnection microstructure in three-dimensional (3D) chip, have significantly enhanced device performance and reliability. However, the increasing interconnect density and operating frequency now pose substantial threats to TSVs’ thermal-mechanical and signal transmission reliability, leading to a reduction in the overall reliability of 3D chip. In this study, a novel TSV with silicon dioxide ring (SDR) structure is proposed, its anti-current leakage performance and transmission performance are proved to be superior than traditional TSV and their derivative. On the basis, the equivalent circuit model of the proposed TSV is established, and the influence of the location, height and thickness of SDR on the thermal-mechanical performance and signal integrity of the new TSV is deeply investigated through thermomechanical analysis, electromagnetic analysis and field-circuit collaborative analysis. Results show that SDR’s position, thickness, and height mainly affect TSV’s thermal stress distribution by changing the area enclosed by the SDR and the volume of the SDR itself, transverse thermal conductivity, and the heat storage capacity. A moderate increase in the distance between SDR and the Cu column can enhance insertion loss in direct current (DC) condition. The inner diameter, thickness and height of SDR have different influence mechanisms on the integrity of TSV. These findings provide valuable guidance for TSV optimization and reliability analysis.
{"title":"Silicon Dioxide Ring Innovations in TSV Structures: Analysis of Thermal-Mechanical and Signal Integrity for 3-D Chip Applications","authors":"Kaihong Hou;Zhengwei Fan;Yonggui Chen;Shufeng Zhang;Yashun Wang;Xun Chen","doi":"10.1109/JEDS.2025.3592893","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3592893","url":null,"abstract":"Through-silicon via (TSV) as a crucial interconnection microstructure in three-dimensional (3D) chip, have significantly enhanced device performance and reliability. However, the increasing interconnect density and operating frequency now pose substantial threats to TSVs’ thermal-mechanical and signal transmission reliability, leading to a reduction in the overall reliability of 3D chip. In this study, a novel TSV with silicon dioxide ring (SDR) structure is proposed, its anti-current leakage performance and transmission performance are proved to be superior than traditional TSV and their derivative. On the basis, the equivalent circuit model of the proposed TSV is established, and the influence of the location, height and thickness of SDR on the thermal-mechanical performance and signal integrity of the new TSV is deeply investigated through thermomechanical analysis, electromagnetic analysis and field-circuit collaborative analysis. Results show that SDR’s position, thickness, and height mainly affect TSV’s thermal stress distribution by changing the area enclosed by the SDR and the volume of the SDR itself, transverse thermal conductivity, and the heat storage capacity. A moderate increase in the distance between SDR and the Cu column can enhance insertion loss in direct current (DC) condition. The inner diameter, thickness and height of SDR have different influence mechanisms on the integrity of TSV. These findings provide valuable guidance for TSV optimization and reliability analysis.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"937-946"},"PeriodicalIF":2.4,"publicationDate":"2025-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11098466","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144852700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-28DOI: 10.1109/JEDS.2025.3593374
Yi Jiang;Luping Wang;Kai Chen;Rui Su;Luyu Yang;Dawei Gao;Junkang Li;Ran Cheng;Rui Zhang
This study shows a novel dual-frequency charge-pumping method, developed to quantitatively characterize the frequency response characteristics of interface traps at the HfO2/Si interface. The response frequency of the interface traps ($f_{it}$ ), or their capture/emission time, has been accurately evaluated in the range of 5-100 MHz across different energy levels by modulating the charge-pumping voltage waveforms. The analysis of $f_{it}$ provides valuable insights into the 1/f noise behavior of MOS devices, as confirmed by the observed correlation between 1/f noise and $f_{it}$ in the typical HfO2/Si n-MOSFETs. Additionally, it was found that the gate oxide traps are predominantly generated at a distance of 0.45 nm away from the HfO2/Si interface, and at an energy of 0.33 eV below conduction band minimum ($E_{c}$ ), under a PBTI stress.
{"title":"The Response Frequency of Interface Traps Using a Dual-Frequency Charge-Pumping Method and Its Correlation With 1/f Noise","authors":"Yi Jiang;Luping Wang;Kai Chen;Rui Su;Luyu Yang;Dawei Gao;Junkang Li;Ran Cheng;Rui Zhang","doi":"10.1109/JEDS.2025.3593374","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3593374","url":null,"abstract":"This study shows a novel dual-frequency charge-pumping method, developed to quantitatively characterize the frequency response characteristics of interface traps at the HfO2/Si interface. The response frequency of the interface traps (<inline-formula> <tex-math>$f_{it}$ </tex-math></inline-formula>), or their capture/emission time, has been accurately evaluated in the range of 5-100 MHz across different energy levels by modulating the charge-pumping voltage waveforms. The analysis of <inline-formula> <tex-math>$f_{it}$ </tex-math></inline-formula> provides valuable insights into the 1/f noise behavior of MOS devices, as confirmed by the observed correlation between 1/f noise and <inline-formula> <tex-math>$f_{it}$ </tex-math></inline-formula> in the typical HfO2/Si n-MOSFETs. Additionally, it was found that the gate oxide traps are predominantly generated at a distance of 0.45 nm away from the HfO2/Si interface, and at an energy of 0.33 eV below conduction band minimum (<inline-formula> <tex-math>$E_{c}$ </tex-math></inline-formula>), under a PBTI stress.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"947-953"},"PeriodicalIF":2.4,"publicationDate":"2025-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11098707","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144853509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-16DOI: 10.1109/JEDS.2025.3589680
Seongwoo Kim;Gunwook Yoon;Seungjae Baik;Myounggon Kang
In this paper, we analyze the retention characteristics of vertical NAND(V-NAND) with dimpled (convex and concave) structures considering the impact of adjacent cell states. Additionally, we assess the efficiency of the previously proposed dummy cell program (DMP) in improving retention characteristics. Our results indicate that when the adjacent cell is in the erased state, the retention characteristics of the target cell are affected by conduction band $(E_{C})$ variations due to trapped electrons. The concave structure shows the best retention characteristics, whereas the convex structure shows the most degradation. This difference becomes even more pronounced when the adjacent cell is in the programmed state. However, when DMP is applied to the convex structure, which exhibits the most degraded retention characteristics, the greatest improvement is observed due to significant changes in channel potential $(V_{ch})$ caused by the fast-programming speed.
{"title":"Retention Characteristics and DMP Efficiency in V-NAND With Dimple Structure","authors":"Seongwoo Kim;Gunwook Yoon;Seungjae Baik;Myounggon Kang","doi":"10.1109/JEDS.2025.3589680","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3589680","url":null,"abstract":"In this paper, we analyze the retention characteristics of vertical NAND(V-NAND) with dimpled (convex and concave) structures considering the impact of adjacent cell states. Additionally, we assess the efficiency of the previously proposed dummy cell program (DMP) in improving retention characteristics. Our results indicate that when the adjacent cell is in the erased state, the retention characteristics of the target cell are affected by conduction band <inline-formula> <tex-math>$(E_{C})$ </tex-math></inline-formula> variations due to trapped electrons. The concave structure shows the best retention characteristics, whereas the convex structure shows the most degradation. This difference becomes even more pronounced when the adjacent cell is in the programmed state. However, when DMP is applied to the convex structure, which exhibits the most degraded retention characteristics, the greatest improvement is observed due to significant changes in channel potential <inline-formula> <tex-math>$(V_{ch})$ </tex-math></inline-formula> caused by the fast-programming speed.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"655-658"},"PeriodicalIF":2.4,"publicationDate":"2025-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11082327","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144758208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-16DOI: 10.1109/JEDS.2025.3583305
Bin Yin;Weizhe Cui;Chuanhan Lin;Shihao Fu;Aidong Shen;Bingsheng Li
The metal/semiconductor (M/S) contact plays a crucial role in carrier collection efficiency and is a key factor in photoelectric conversion. To optimize the M/S contact of Al and $beta $ -Ga2O3, several annealing procedures were explored, including low-temperature annealing, direct Sn layer deposition, and face-to-face annealing. Among these methods, the $beta $ -Ga2O3-based solar-blind photodetector fabricated using face-to-face annealing—incorporating an ultra-thin Sn-doped high-conductivity layer—demonstrated superior performance. This device achieved an exceptionally high light-to-dark current ratio of $1.71times 10{^{{8}}}$ , with a responsivity of 14.13 A/W and a detectivity of $1.87times 10^{16}$ Jones at a 10 V bias under 255 nm irradiation ($23.75~mu $ w/cm2 light intensity). Additionally, it is capable of providing quick signal feedback, with a decay time of 2.81 ms/72.46 ms. The enhanced performance of the face-to-face annealing method is attributed to the formation of a more uniform ultra-thin Sn-doped conductive layer. This layer effectively lowers the barrier height at the M/S interface, improves carrier migration, and reduces contact resistance. These findings highlight that interface engineering through Sn-doped conductive layers is a promising strategy for optimizing the performance of $beta $ -Ga2O3-based photodetectors.
金属/半导体（M/S）接触对载流子收集效率起着至关重要的作用，是光电转换的关键因素。为了优化Al与$beta $ -Ga2O3的M/S接触，研究了低温退火、直接沉积Sn层和面对面退火等退火工艺。在这些方法中，采用面对面退火制备的$beta $ - ga2o3基太阳盲光电探测器（包含超薄掺杂锡的高导电性层）表现出优异的性能。该器件实现了极高的明暗电流比$1.71times 10{^{{8}}}$，响应率为14.13 a /W，在255 nm照射（$23.75~mu $ W /cm2光强）下，10v偏置下的探测率为$1.87times 10^{16}$ Jones。此外，它能够提供快速的信号反馈，衰减时间为2.81 ms/72.46 ms。面对面退火方法的性能增强是由于形成了更均匀的超薄掺杂锡导电层。该层有效降低了M/S界面的势垒高度，促进了载流子迁移，降低了接触电阻。这些发现突出表明，通过掺锡导电层进行界面工程是优化$beta $ - ga2o3光电探测器性能的一种很有前途的策略。
{"title":"Performance Optimization of β-Ga₂O₃-Based Solar-Blind Photodetector by Introducing an Ultra-Thin Sn-Doped High Conductivity Layer","authors":"Bin Yin;Weizhe Cui;Chuanhan Lin;Shihao Fu;Aidong Shen;Bingsheng Li","doi":"10.1109/JEDS.2025.3583305","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3583305","url":null,"abstract":"The metal/semiconductor (M/S) contact plays a crucial role in carrier collection efficiency and is a key factor in photoelectric conversion. To optimize the M/S contact of Al and <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3, several annealing procedures were explored, including low-temperature annealing, direct Sn layer deposition, and face-to-face annealing. Among these methods, the <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3-based solar-blind photodetector fabricated using face-to-face annealing—incorporating an ultra-thin Sn-doped high-conductivity layer—demonstrated superior performance. This device achieved an exceptionally high light-to-dark current ratio of <inline-formula> <tex-math>$1.71times 10{^{{8}}}$ </tex-math></inline-formula>, with a responsivity of 14.13 A/W and a detectivity of <inline-formula> <tex-math>$1.87times 10^{16}$ </tex-math></inline-formula> Jones at a 10 V bias under 255 nm irradiation (<inline-formula> <tex-math>$23.75~mu $ </tex-math></inline-formula>w/cm2 light intensity). Additionally, it is capable of providing quick signal feedback, with a decay time of 2.81 ms/72.46 ms. The enhanced performance of the face-to-face annealing method is attributed to the formation of a more uniform ultra-thin Sn-doped conductive layer. This layer effectively lowers the barrier height at the M/S interface, improves carrier migration, and reduces contact resistance. These findings highlight that interface engineering through Sn-doped conductive layers is a promising strategy for optimizing the performance of <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3-based photodetectors.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"577-581"},"PeriodicalIF":2.0,"publicationDate":"2025-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11082297","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144687625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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