Pub Date : 2024-08-21DOI: 10.1109/JEDS.2024.3447150
Gerardo Malavena;Salvatore M. Amoroso;Andrew R. Brown;Plamen Asenov;Xi-Wei Lin;Victor Moroz;Mattia Giulianini;David Refaldi;Christian Monzio Compagnoni;Alessandro S. Spinelli
In Part II of this article we discuss the impact of a discrete treatment of traps on 3-D NAND Flash random telegraph noise (RTN). A higher RTN results when discrete traps are taken into account, that can only be explained by a stronger influence of the discrete charged traps on the current conduction, leading to more percolation. The effects are then investigated as a function of the cell parameters, showing that a continuous model for traps cannot reproduce the correct dependence.
{"title":"Discrete-Trap Effects on 3-D NAND Variability – Part II: Random Telegraph Noise","authors":"Gerardo Malavena;Salvatore M. Amoroso;Andrew R. Brown;Plamen Asenov;Xi-Wei Lin;Victor Moroz;Mattia Giulianini;David Refaldi;Christian Monzio Compagnoni;Alessandro S. Spinelli","doi":"10.1109/JEDS.2024.3447150","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3447150","url":null,"abstract":"In Part II of this article we discuss the impact of a discrete treatment of traps on 3-D NAND Flash random telegraph noise (RTN). A higher RTN results when discrete traps are taken into account, that can only be explained by a stronger influence of the discrete charged traps on the current conduction, leading to more percolation. The effects are then investigated as a function of the cell parameters, showing that a continuous model for traps cannot reproduce the correct dependence.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10643403","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142137518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-21DOI: 10.1109/JEDS.2024.3447032
Xiaoying Tang;Zhiqiang Li;Lang Zeng;Hongwei Zhou;Xiaoxu Cheng;Zhenjie Yao
Engineers used TCAD tools for semiconductor devices modeling. However, it is computationally expensive and time-consuming for advanced devices with smaller dimensions. Therefore, this work proposes a machine learning-based device modeling algorithm to capture the complex nonlinear relationship between parameters and electrical characteristics of gate-all-around (GAA) nanowire field-effect transistors (NWFETs) from technology computer-aided design (TCAD) simulation results. This method utilizes a densely connected deep neural networks (DenseDNN), which establishes direct connections between layers in the neural networks, provides stronger feature extraction and information transmission capabilities. By incorporating cost-sensitive learning methods, the proposed model focus more on the critical data that determines device characteristics, leading to accurate prediction of key device characteristics under various parameters. Experimental results on a test dataset of 116 NWFETs demonstrate the effectiveness of this method. The DenseDNN model with cost-sensitive learning exhibits better performance than traditional deep neural networks (DNN) with various widths and depths, with a prediction error below 1.62%. Moreover, compared to TCAD simulation results, the model can speedup $10^{6}times$ .
{"title":"Device Modeling Based on Cost-Sensitive Densely Connected Deep Neural Networks","authors":"Xiaoying Tang;Zhiqiang Li;Lang Zeng;Hongwei Zhou;Xiaoxu Cheng;Zhenjie Yao","doi":"10.1109/JEDS.2024.3447032","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3447032","url":null,"abstract":"Engineers used TCAD tools for semiconductor devices modeling. However, it is computationally expensive and time-consuming for advanced devices with smaller dimensions. Therefore, this work proposes a machine learning-based device modeling algorithm to capture the complex nonlinear relationship between parameters and electrical characteristics of gate-all-around (GAA) nanowire field-effect transistors (NWFETs) from technology computer-aided design (TCAD) simulation results. This method utilizes a densely connected deep neural networks (DenseDNN), which establishes direct connections between layers in the neural networks, provides stronger feature extraction and information transmission capabilities. By incorporating cost-sensitive learning methods, the proposed model focus more on the critical data that determines device characteristics, leading to accurate prediction of key device characteristics under various parameters. Experimental results on a test dataset of 116 NWFETs demonstrate the effectiveness of this method. The DenseDNN model with cost-sensitive learning exhibits better performance than traditional deep neural networks (DNN) with various widths and depths, with a prediction error below 1.62%. Moreover, compared to TCAD simulation results, the model can speedup \u0000<inline-formula> <tex-math>$10^{6}times$ </tex-math></inline-formula>\u0000.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10643157","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142090777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-16DOI: 10.1109/JEDS.2024.3438210
Sunaina Priyadarshi;Abidur Rahaman;Mohammad Masum Billah;Sabiqun Nahar;Md. Redowan Mahmud Arnob;Jin Jang
This article intends to use a low-temperature poly-Si oxide (LTPO) level-down-shifter (LDS) to translate voltage signals with different amplitudes operating at various frequencies. The LTPO LDS is made of p-type low-temperature poly-Si and n-type a-InGaZnO thin-film transistors. The input voltage range of 2 V~10 V could be shifted to 1.2 V ~ 4.41 V output voltage. The rising and falling times are less than 400 ns at the operational frequency of 50 kHz. Also, the multiple output power supply of 6 V, 3 V, and 1.8 V for interface circuits has been possible with a single supply of 10 V. The proposed LDS shows a switching power consumption of 95.57 pW and area of 0.023 mm2.
本文旨在使用低温多晶硅氧化物（LTPO）电平降低转换器（LDS）来转换在不同频率下工作的不同幅度的电压信号。LTPO LDS 由 p 型低温多晶硅和 n 型 a-InGaZnO 薄膜晶体管组成。输入电压范围为 2 V~10 V，可转换为 1.2 V~4.41 V 的输出电压。在 50 kHz 的工作频率下，上升和下降时间小于 400 ns。此外，只需 10 V 单电源，即可为接口电路提供 6 V、3 V 和 1.8 V 的多路输出电源。
{"title":"High Speed Level-Down Shifter Using LTPO TFTs for Low Power and Interface Electronics","authors":"Sunaina Priyadarshi;Abidur Rahaman;Mohammad Masum Billah;Sabiqun Nahar;Md. Redowan Mahmud Arnob;Jin Jang","doi":"10.1109/JEDS.2024.3438210","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3438210","url":null,"abstract":"This article intends to use a low-temperature poly-Si oxide (LTPO) level-down-shifter (LDS) to translate voltage signals with different amplitudes operating at various frequencies. The LTPO LDS is made of p-type low-temperature poly-Si and n-type a-InGaZnO thin-film transistors. The input voltage range of 2 V~10 V could be shifted to 1.2 V ~ 4.41 V output voltage. The rising and falling times are less than 400 ns at the operational frequency of 50 kHz. Also, the multiple output power supply of 6 V, 3 V, and 1.8 V for interface circuits has been possible with a single supply of 10 V. The proposed LDS shows a switching power consumption of 95.57 pW and area of 0.023 mm2.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10637919","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142013206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The motivation of this study was to solve the high $rm I_{D,off}$ problem in 8 Volt N-channel MOSFET. We experimented with implanting nitrogen into LDD at various doses. As a result, $rm I_{D,off}$ increases and $rm BV_{DSS}$ decreases as the dose increases. When it exceeds 1.0E15 cm $^{-2}$ , the occurrence of tail-type $rm I_{D,off}$ and $rm BV_{DSS}$ that deviate from the normal distribution increases. Implanted nitrogen enhances the diffusion of dopants in the LDD bulk but suppresses it on the silicon surface. As a result, the depletion curvature at the LDD edge becomes a negative shape and increases the electric field. We performed the same experiment on logic MOSFETs to comprehensively analyze other electrical effects. Nitrogen improves the HCI immunity of MOSFETs but degrades for 2.5 Volt and 8 Volt MOSFETs when the dose is above 1.0E15 cm $^{-2}$ . The short-channel effect of 2.5 Volt MOSFET is insensitive to nitrogen but is suppressed in CORE MOSFET when the dose is over 1.3E15 cm $^{-2}$ . Nitrogen changes $rm I_{D,sat}$ through interactions with co-implanted species and nitrogen dose. As a result, nitrogen co-implanted with phosphorus shows a parabolic-like $rm I_{D,sat}$ trend. However, in the case of CORE MOSFET implanted with arsenic, $rm I_{D,sat}$ does not show a parabolic-like trend but increases continuously. This experiment did not find much benefit from nitrogen implantation for 2.5 Volt and 8 Volt MOSFETs. For all MOSFETs, it is recommended that the nitrogen dosage not exceed 1.0E15 cm $^{-2}$ .
{"title":"Electrical Effect of Nitrogen Implanted Into LDD of MOSFETs","authors":"Yoo Seon Song;Markus Lenski;Mohammed F. Karim;Keith Flynn;Jan Hoentschel;Carsten Peters;Jens-Uwe Sachse;Ömür Işıl Aydin;Jun Wu;Bastian Haußdörfer;Mahesh Siddabathula;Konrad Semmler;Jürgen Daleiden","doi":"10.1109/JEDS.2024.3442474","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3442474","url":null,"abstract":"The motivation of this study was to solve the high \u0000<inline-formula> <tex-math>$rm I_{D,off}$ </tex-math></inline-formula>\u0000 problem in 8 Volt N-channel MOSFET. We experimented with implanting nitrogen into LDD at various doses. As a result, \u0000<inline-formula> <tex-math>$rm I_{D,off}$ </tex-math></inline-formula>\u0000 increases and \u0000<inline-formula> <tex-math>$rm BV_{DSS}$ </tex-math></inline-formula>\u0000 decreases as the dose increases. When it exceeds 1.0E15 cm\u0000<inline-formula> <tex-math>$^{-2}$ </tex-math></inline-formula>\u0000, the occurrence of tail-type \u0000<inline-formula> <tex-math>$rm I_{D,off}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$rm BV_{DSS}$ </tex-math></inline-formula>\u0000 that deviate from the normal distribution increases. Implanted nitrogen enhances the diffusion of dopants in the LDD bulk but suppresses it on the silicon surface. As a result, the depletion curvature at the LDD edge becomes a negative shape and increases the electric field. We performed the same experiment on logic MOSFETs to comprehensively analyze other electrical effects. Nitrogen improves the HCI immunity of MOSFETs but degrades for 2.5 Volt and 8 Volt MOSFETs when the dose is above 1.0E15 cm\u0000<inline-formula> <tex-math>$^{-2}$ </tex-math></inline-formula>\u0000. The short-channel effect of 2.5 Volt MOSFET is insensitive to nitrogen but is suppressed in CORE MOSFET when the dose is over 1.3E15 cm\u0000<inline-formula> <tex-math>$^{-2}$ </tex-math></inline-formula>\u0000. Nitrogen changes \u0000<inline-formula> <tex-math>$rm I_{D,sat}$ </tex-math></inline-formula>\u0000 through interactions with co-implanted species and nitrogen dose. As a result, nitrogen co-implanted with phosphorus shows a parabolic-like \u0000<inline-formula> <tex-math>$rm I_{D,sat}$ </tex-math></inline-formula>\u0000 trend. However, in the case of CORE MOSFET implanted with arsenic, \u0000<inline-formula> <tex-math>$rm I_{D,sat}$ </tex-math></inline-formula>\u0000 does not show a parabolic-like trend but increases continuously. This experiment did not find much benefit from nitrogen implantation for 2.5 Volt and 8 Volt MOSFETs. For all MOSFETs, it is recommended that the nitrogen dosage not exceed 1.0E15 cm\u0000<inline-formula> <tex-math>$^{-2}$ </tex-math></inline-formula>\u0000.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10634165","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142090780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-08DOI: 10.1109/jeds.2024.3441389
Ziang Guo, Sergei Mistyuk, Arthur Carpenter, Charles E. Hunt
{"title":"High-Performance Germanium P-I-N Photodiodes for High-Speed, Hard X-Ray Imaging","authors":"Ziang Guo, Sergei Mistyuk, Arthur Carpenter, Charles E. Hunt","doi":"10.1109/jeds.2024.3441389","DOIUrl":"https://doi.org/10.1109/jeds.2024.3441389","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141969057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We prototyped a true analog current computing multilayer neural network (NN) chip, where multiple analog in-memory computing (AiMC) circuit blocks are connected to each other via simple analog non-linear operation circuits. The true analog current computing is achieved with the invention of an analog current rectified linear unit (ReLU) circuit of a three-stage current mirror. With the prototyped NN chip, we demonstrated that the true analog computing (1) achieves process variation compensation utilizing current driving, (2) eliminates digital-analog or analog-digital data conversion between NNs, and (3) realizes low power inference, not only in multiply-accumulate (MAC) but in ReLU operation. Through classification of Mixed National Institute of Standards and Technology dataset, the chip exhibits a low energy of 1.1 nJ/classification and an accuracy of 91.6%, achieves weight retention of five hours, much longer than dynamic random access memory, and enables 68% power reduction compared with serially connected two single-layer NN chips with analog-digital converters and digital-analog converters in between. Although periodic refresh from an external storage class memory is necessary for applications that require continuous operation exceeding five hours, our AiMC capable of MAC and non-linear operations with low power is effective in applications such as edge artificial intelligence terminals with limited power sources.
我们制作了真正的模拟电流计算多层神经网络（NN）芯片原型，其中多个模拟内存计算（AiMC）电路块通过简单的模拟非线性运算电路相互连接。三级电流镜的模拟电流整流线性单元（ReLU）电路的发明实现了真正的模拟电流计算。通过原型 NN 芯片，我们证明了真正的模拟计算：(1) 利用电流驱动实现了工艺变化补偿；(2) 消除了 NN 之间的数模或模数数据转换；(3) 实现了低功耗推理，不仅在乘法累加（MAC）中如此，在 ReLU 运算中也是如此。通过对美国国家标准与技术研究院的混合数据集进行分类，该芯片实现了 1.1 nJ/分类的低能耗和 91.6% 的准确率，重量保持时间长达 5 小时，远远超过动态随机存取存储器，与串行连接的两个单层 NN 芯片（中间带有模拟数字转换器和数字模拟转换器）相比，功耗降低了 68%。虽然对于需要连续工作超过五小时的应用来说，从外部存储类存储器定期刷新是必要的，但我们的 AiMC 能够以低功耗进行 MAC 和非线性操作，在诸如电源有限的边缘人工智能终端等应用中非常有效。
{"title":"A 1.1-nJ/Classification True Analog Current Computing on Multilayer Neural Network With Crystalline-IGZO/Si-CMOS Monolithic Stack Technology","authors":"Kazuki Tsuda;Kazuma Furutani;Yuto Yakubo;Hiromichi Godo;Yoshinori Ando;Atsutake Kosuge;Toru Nakura;Shunpei Yamazaki","doi":"10.1109/JEDS.2024.3439712","DOIUrl":"10.1109/JEDS.2024.3439712","url":null,"abstract":"We prototyped a true analog current computing multilayer neural network (NN) chip, where multiple analog in-memory computing (AiMC) circuit blocks are connected to each other via simple analog non-linear operation circuits. The true analog current computing is achieved with the invention of an analog current rectified linear unit (ReLU) circuit of a three-stage current mirror. With the prototyped NN chip, we demonstrated that the true analog computing (1) achieves process variation compensation utilizing current driving, (2) eliminates digital-analog or analog-digital data conversion between NNs, and (3) realizes low power inference, not only in multiply-accumulate (MAC) but in ReLU operation. Through classification of Mixed National Institute of Standards and Technology dataset, the chip exhibits a low energy of 1.1 nJ/classification and an accuracy of 91.6%, achieves weight retention of five hours, much longer than dynamic random access memory, and enables 68% power reduction compared with serially connected two single-layer NN chips with analog-digital converters and digital-analog converters in between. Although periodic refresh from an external storage class memory is necessary for applications that require continuous operation exceeding five hours, our AiMC capable of MAC and non-linear operations with low power is effective in applications such as edge artificial intelligence terminals with limited power sources.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10628044","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-06DOI: 10.1109/JEDS.2024.3438886
Tomoya Sanuki;Hideto Horii;Takashi Maeda
In this work, we report the fast-read storage performance of thyristor operation in 3D flash memory. By forming a pseudo N+/P/N/P+ structure with the word line (WL) bias of 3D string cells, thyristor operation with steep switching characteristics and a high on-current can be obtained. It is known that there is a strong cell-to-cell interference effect in thyristor operation, and in previous report (Horii et al., 2020), we have suggested novel WL bias conditions, referred to as the wide barrier mode, that can suppress the cell-to-cell interference effect. In order to evaluate the advantages of thyristor operation in 3D flash memory further, we report for the first time the several cell characteristics and reliability issues of thyristor operation required for the actual usage of storage products. (1) We demonstrate excellent cell characteristics of a wide programmed Vth window and sufficient program slope values in thyristor operation, which are indispensable for realizing multi-level cells. (2) Cell characteristics of thyristor operation exhibit hysteresis when sweeping in the WL direction but not in the bit line (BL) direction, which is essential for determining the read operating waveform. (3) Our proposed new WL biasing scheme to suppress the cell-to-cell interference effect is described with a more detailed dependence on adjacent cells and its effect on the on-current. We show that a high on-current can still be achieved even with highly stacked WL of approximately 100 layers. (4) In terms of reliability issues, thyristor operation exhibits a sufficient margin against read cycle stress with minimal change in the cell Vth even after 2 million read cycles. Thyristor operation can be applied to storage products even in read-intensive applications. (5) We also describe storage performance, including read latency and bandwidth, for SLC and QLC mode in memory arrays with highly stacked WL of approximately 100 layers. Thyristor operation of 3D flash memory is a strong candidate for future high-speed storage products, as it can significantly improve read latency and program throughput.
{"title":"Fast-Read Storage Performance by Thyristor Operation in 3-D Flash Memory","authors":"Tomoya Sanuki;Hideto Horii;Takashi Maeda","doi":"10.1109/JEDS.2024.3438886","DOIUrl":"10.1109/JEDS.2024.3438886","url":null,"abstract":"In this work, we report the fast-read storage performance of thyristor operation in 3D flash memory. By forming a pseudo N+/P/N/P+ structure with the word line (WL) bias of 3D string cells, thyristor operation with steep switching characteristics and a high on-current can be obtained. It is known that there is a strong cell-to-cell interference effect in thyristor operation, and in previous report (Horii et al., 2020), we have suggested novel WL bias conditions, referred to as the wide barrier mode, that can suppress the cell-to-cell interference effect. In order to evaluate the advantages of thyristor operation in 3D flash memory further, we report for the first time the several cell characteristics and reliability issues of thyristor operation required for the actual usage of storage products. (1) We demonstrate excellent cell characteristics of a wide programmed Vth window and sufficient program slope values in thyristor operation, which are indispensable for realizing multi-level cells. (2) Cell characteristics of thyristor operation exhibit hysteresis when sweeping in the WL direction but not in the bit line (BL) direction, which is essential for determining the read operating waveform. (3) Our proposed new WL biasing scheme to suppress the cell-to-cell interference effect is described with a more detailed dependence on adjacent cells and its effect on the on-current. We show that a high on-current can still be achieved even with highly stacked WL of approximately 100 layers. (4) In terms of reliability issues, thyristor operation exhibits a sufficient margin against read cycle stress with minimal change in the cell Vth even after 2 million read cycles. Thyristor operation can be applied to storage products even in read-intensive applications. (5) We also describe storage performance, including read latency and bandwidth, for SLC and QLC mode in memory arrays with highly stacked WL of approximately 100 layers. Thyristor operation of 3D flash memory is a strong candidate for future high-speed storage products, as it can significantly improve read latency and program throughput.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10624679","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-01DOI: 10.1109/JEDS.2024.3436820
Myeongsu Chae;Ho-Young Cha;Hyungtak Kim
In this work, we investigated the instability of threshold voltage (Vth) in p-GaN/AlGaN/GaN high electron mobility transistors (HEMTs) under positive gate biases and high temperatures. We reveal an abnormal temperature dependence of threshold voltage instability, suggesting that threshold voltage instability significant differences at elevated temperatures and is primarily attributed to the trapping/detrapping of charged carriers. Notably, the positive shift in threshold voltage diminished and eventually reversed at low gate bias as the temperature increased. In contrast, the negative shift intensified with increasing temperature but began to mitigate above 100°C at high gate bias due to an enhanced de-trapping process of electrons and holes. These results suggest the presence of multiple mechanisms behind the threshold voltage instability under varying thermal conditions.
{"title":"Abnormal Temperature and Bias Dependence of Threshold Voltage Instability in p-GaN/AlGaN/GaN HEMTs","authors":"Myeongsu Chae;Ho-Young Cha;Hyungtak Kim","doi":"10.1109/JEDS.2024.3436820","DOIUrl":"10.1109/JEDS.2024.3436820","url":null,"abstract":"In this work, we investigated the instability of threshold voltage (Vth) in p-GaN/AlGaN/GaN high electron mobility transistors (HEMTs) under positive gate biases and high temperatures. We reveal an abnormal temperature dependence of threshold voltage instability, suggesting that threshold voltage instability significant differences at elevated temperatures and is primarily attributed to the trapping/detrapping of charged carriers. Notably, the positive shift in threshold voltage diminished and eventually reversed at low gate bias as the temperature increased. In contrast, the negative shift intensified with increasing temperature but began to mitigate above 100°C at high gate bias due to an enhanced de-trapping process of electrons and holes. These results suggest the presence of multiple mechanisms behind the threshold voltage instability under varying thermal conditions.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10620298","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141882126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-31DOI: 10.1109/jeds.2024.3436063
Huikai Chen, Jinbin Pan, Shulong Wang, Liutao Li, Jin Huang, Shupeng Chen, Hongxia Liu
{"title":"Explicit Function Model of Electromagnetic Reliability for CMOS Inverters Under HPM Coupling Based on Physical Mechanism Analysis and Neural Network Algorithm","authors":"Huikai Chen, Jinbin Pan, Shulong Wang, Liutao Li, Jin Huang, Shupeng Chen, Hongxia Liu","doi":"10.1109/jeds.2024.3436063","DOIUrl":"https://doi.org/10.1109/jeds.2024.3436063","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141867522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We demonstrate that the shorter channel self-aligned top-gate (SA TG) coplanar indiumgallium- zinc oxide (IGZO) thin-film transistors (TFTs), with negative voltage applied to the back-gate, exhibit superior characteristics as driving transistors in organic light-emitting diode (OLED) pixels compared to their longer channel counterparts. The shorter channel IGZO TFTs (with a channel length (L) of 3 μm) biased with a back gate voltage of −3.5 V showed a larger subthreshold swing (SS = 0.21 V/dec) than the longer channel ones (with L = 5 μm, SS = 0.16 V/dec) with a similar threshold value (VTH = 0.7–0.8 V). A large SS is beneficial for controlling grayscale levels, especially at low gray levels, when IGZO TFTs are used as driving transistors in OLED pixels. Furthermore, the negatively back-gate-biased shorter channel SA TG coplanar IGZO TFTs exhibited significantly enhanced electrical stability compared to the longer channel ones under both positive gate bias and hot carrier stresses. The findings of this study are expected to be useful in expanding the utility of IGZO TFTs in OLED displays.
{"title":"Demonstration of SA TG Coplanar IGZO TFTs With Large Subthreshold Swing Using the Back-Gate Biasing Technique for AMOLED Applications","authors":"Chae-Eun Oh;Ye-Lim Han;Dong-Ho Lee;Jin-Ha Hwang;Hwan-Seok Jeong;Myeong-Ho Kim;Kyoung-Seok Son;Sunhee Lee;Sang-Hun Song;Hyuck-In Kwon","doi":"10.1109/JEDS.2024.3434613","DOIUrl":"10.1109/JEDS.2024.3434613","url":null,"abstract":"We demonstrate that the shorter channel self-aligned top-gate (SA TG) coplanar indiumgallium- zinc oxide (IGZO) thin-film transistors (TFTs), with negative voltage applied to the back-gate, exhibit superior characteristics as driving transistors in organic light-emitting diode (OLED) pixels compared to their longer channel counterparts. The shorter channel IGZO TFTs (with a channel length (L) of 3 μm) biased with a back gate voltage of −3.5 V showed a larger subthreshold swing (SS = 0.21 V/dec) than the longer channel ones (with L = 5 μm, SS = 0.16 V/dec) with a similar threshold value (VTH = 0.7–0.8 V). A large SS is beneficial for controlling grayscale levels, especially at low gray levels, when IGZO TFTs are used as driving transistors in OLED pixels. Furthermore, the negatively back-gate-biased shorter channel SA TG coplanar IGZO TFTs exhibited significantly enhanced electrical stability compared to the longer channel ones under both positive gate bias and hot carrier stresses. The findings of this study are expected to be useful in expanding the utility of IGZO TFTs in OLED displays.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10612771","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141867462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：