The ballistic transport behaviors of SOI nMOSFETs with NiSi metal source/drain (S/D) have been investigated. It is found that the suppression of Schottky barrier height for holes results in an improvement of carrier injection velocity (vinj), attributable to the increased electrical field at the source edge. As a result, the electron injection velocity (vinj) of $1.77times 10{^{{7}}}$ cm/s has been realized at the lateral electrical field of 1 MV/cm for the SOI nMOSFETs with a S/D Schottky barrier height of 0.71 eV. These results suggest that the metal S/D structure is feasible to boost the performance of ultimately scaled SOI devices.
{"title":"Impact of the Schottky Barrier Height on the Carrier Velocity Overshoot Behaviors in SOI nMOSFETs With Metal Source/Drain","authors":"Rui Su;Yan Jing;Xinyi Zhang;Yi Jiang;Dawei Gao;Walter Schwarzenbach;Bich-Yen Nguyen;Junkang Li;John Robertson;Rui Zhang","doi":"10.1109/JEDS.2025.3569242","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3569242","url":null,"abstract":"The ballistic transport behaviors of SOI nMOSFETs with NiSi metal source/drain (S/D) have been investigated. It is found that the suppression of Schottky barrier height for holes results in an improvement of carrier injection velocity (vinj), attributable to the increased electrical field at the source edge. As a result, the electron injection velocity (vinj) of <inline-formula> <tex-math>$1.77times 10{^{{7}}}$ </tex-math></inline-formula> cm/s has been realized at the lateral electrical field of 1 MV/cm for the SOI nMOSFETs with a S/D Schottky barrier height of 0.71 eV. These results suggest that the metal S/D structure is feasible to boost the performance of ultimately scaled SOI devices.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"464-470"},"PeriodicalIF":2.0,"publicationDate":"2025-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11005719","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-14DOI: 10.1109/JEDS.2025.3551313
Hsien-Chin Chiu;Chong-Rong Huang;Chia-Han Lin;Chia-Hao Yu;Hsuan-Ling Kao;Shinn-Yn Lin;Barry Lin
$0.5~mu $ m enhancement-mode (E-mode) p-GaN $Gamma $ -gate RF HEMT with engineered Mg doping profile in p-GaN layer was studied for high power amplifier application. With high/low Mg doping profile design in p-GaN, the traditional Ti/p-GaN Schottky gate behavior can be transformed to ohmic-gate after 550°C 3 minutes post-gate annealing. The ohmic-gate design of p-GaN HEMT can minimize poole-frenkel (PF) emission thus the flicker noise and current collapse (C.C) can be improved. A better gate-to-channel modulation ability is also obtained due to precipitous C-VG curve of low Mg ($1times 10{^{{19}}}$ cm-3) doping concentration p-GaN layer. The fabricated device achieves a threshold voltage (VTH) of +1.1 V, and shows a low on-resistance (RON) of $1.8~Omega cdot $ mm and an off-state breakdown voltage of 206 V. With the engineered Mg doping profile design, a 70% PAE is achieved together with an output power density of 1W/mm at VDS of 10V.
$0.5~mu $ 研究了在p-GaN层中掺杂工程Mg谱线的m增强模式（e模式）p-GaN $Gamma $门射频HEMT在高功率放大器中的应用。在p-GaN中采用高/低Mg掺杂设计，经过550℃3分钟的栅极退火后，传统的Ti/p-GaN肖特基栅极行为可以转变为欧姆栅极。p-GaN HEMT的欧姆栅极设计可以最大限度地减少池-峰峰（PF）发射，从而改善闪变噪声和电流崩溃（C.C）。由于低Mg （$1times 10{^{{19}}}$ cm-3）掺杂浓度的p-GaN层具有陡峭的C-VG曲线，因此具有较好的门到通道调制能力。该器件的阈值电压（VTH）为+1.1 V，导通电阻（RON）低至$1.8~Omega cdot $ mm，断态击穿电压为206v。采用工程Mg掺杂剖面设计，70% PAE is achieved together with an output power density of 1W/mm at VDS of 10V.
{"title":"High Power Added Efficiency Enhancement-Mode Γ-Gate RF HEMT With High/Low p-GaN Doping Profile","authors":"Hsien-Chin Chiu;Chong-Rong Huang;Chia-Han Lin;Chia-Hao Yu;Hsuan-Ling Kao;Shinn-Yn Lin;Barry Lin","doi":"10.1109/JEDS.2025.3551313","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3551313","url":null,"abstract":"<inline-formula> <tex-math>$0.5~mu $ </tex-math></inline-formula>m enhancement-mode (E-mode) p-GaN <inline-formula> <tex-math>$Gamma $ </tex-math></inline-formula>-gate RF HEMT with engineered Mg doping profile in p-GaN layer was studied for high power amplifier application. With high/low Mg doping profile design in p-GaN, the traditional Ti/p-GaN Schottky gate behavior can be transformed to ohmic-gate after 550°C 3 minutes post-gate annealing. The ohmic-gate design of p-GaN HEMT can minimize poole-frenkel (PF) emission thus the flicker noise and current collapse (C.C) can be improved. A better gate-to-channel modulation ability is also obtained due to precipitous C-VG curve of low Mg (<inline-formula> <tex-math>$1times 10{^{{19}}}$ </tex-math></inline-formula>cm-3) doping concentration p-GaN layer. The fabricated device achieves a threshold voltage (VTH) of +1.1 V, and shows a low on-resistance (RON) of <inline-formula> <tex-math>$1.8~Omega cdot $ </tex-math></inline-formula>mm and an off-state breakdown voltage of 206 V. With the engineered Mg doping profile design, a 70% PAE is achieved together with an output power density of 1W/mm at VDS of 10V.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"285-289"},"PeriodicalIF":2.0,"publicationDate":"2025-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10926554","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-13DOI: 10.1109/JEDS.2025.3569528
Jiaye Shen;Zhiqiang Li;Zhenjie Yao
Device design processes based on manual design experience require numerous experiments and simulations. As transistors continue to shrink, complex physical effects, such as quantum effects intensify, making the design process increasingly costly, whether based on experiments or technology computer-assisted design (TCAD) simulations. To reduce the experimental and simulation resources consumed during the design process, we propose a device optimization framework based on neural network-enhanced Bayesian Optimization (BO). We target two Figures of Merit (FoMs) of Nanowire field-effect transistor (NWFET) devices as optimization objectives: subthreshold swing (SS) and on-state current (Ion). By improving the neural network to better fit the nonlinear mapping between the objective functions and input parameters, we effectively optimize device parameters while reducing the number of TCAD simulations. Experimental results show that compared to Bayesian optimization frameworks based on Gaussian Process (GP), Random Forest (RF) and Deep Networks for Global Optimization (DNGO), our neural network-based Bayesian optimization framework reduced the number of iterations by 19.3%, 42.7% and 60.3%, respectively.
{"title":"Optimize Gate-All-Around Devices Using Wide Neural Network-Enhanced Bayesian Optimization","authors":"Jiaye Shen;Zhiqiang Li;Zhenjie Yao","doi":"10.1109/JEDS.2025.3569528","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3569528","url":null,"abstract":"Device design processes based on manual design experience require numerous experiments and simulations. As transistors continue to shrink, complex physical effects, such as quantum effects intensify, making the design process increasingly costly, whether based on experiments or technology computer-assisted design (TCAD) simulations. To reduce the experimental and simulation resources consumed during the design process, we propose a device optimization framework based on neural network-enhanced Bayesian Optimization (BO). We target two Figures of Merit (FoMs) of Nanowire field-effect transistor (NWFET) devices as optimization objectives: subthreshold swing (SS) and on-state current (Ion). By improving the neural network to better fit the nonlinear mapping between the objective functions and input parameters, we effectively optimize device parameters while reducing the number of TCAD simulations. Experimental results show that compared to Bayesian optimization frameworks based on Gaussian Process (GP), Random Forest (RF) and Deep Networks for Global Optimization (DNGO), our neural network-based Bayesian optimization framework reduced the number of iterations by 19.3%, 42.7% and 60.3%, respectively.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"456-463"},"PeriodicalIF":2.0,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11003089","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work investigates the reliability and aging predictions in a 14-nm FinFET-based analog circuit under high-temperature conditions. Aging simulations and accelerated aging tests were carried out on key devices of phase-locked loop (PLL) circuits, with a focus on the time-power-law exponent (n) of $Delta $ Vth and temperature activation energy. A coupling phenomenon between hot-carrier injection (HCI) and negative bias temperature instability (NBTI) effects has been found at elevated temperatures, where HCI-induced self-heating effect (SHE) exacerbated the NBTI effects. Device degradation was found to be closely related to the waveform, frequency, and operating temperature. The quasi-static-approximation (QSA) model built with DC stress test data, was employed for device and circuit degradation predictions, and its limitations and applicability were discussed. Additionally, based on AC test data, the QSA model was used to simulate corrections for device and circuit degradation at corresponding frequencies. The results revealed over-predictions of degradation level by a time factor over 10.
{"title":"Aging Analysis and Degradation Prediction of PLL Circuits in 14-nm FinFET Technology","authors":"Meng Li;Xin Xu;Xianghui Li;Yunpeng Li;Yiqun Shi;Qingqing Sun;Hao Zhu","doi":"10.1109/JEDS.2025.3549754","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3549754","url":null,"abstract":"This work investigates the reliability and aging predictions in a 14-nm FinFET-based analog circuit under high-temperature conditions. Aging simulations and accelerated aging tests were carried out on key devices of phase-locked loop (PLL) circuits, with a focus on the time-power-law exponent (n) of <inline-formula> <tex-math>$Delta $ </tex-math></inline-formula> Vth and temperature activation energy. A coupling phenomenon between hot-carrier injection (HCI) and negative bias temperature instability (NBTI) effects has been found at elevated temperatures, where HCI-induced self-heating effect (SHE) exacerbated the NBTI effects. Device degradation was found to be closely related to the waveform, frequency, and operating temperature. The quasi-static-approximation (QSA) model built with DC stress test data, was employed for device and circuit degradation predictions, and its limitations and applicability were discussed. Additionally, based on AC test data, the QSA model was used to simulate corrections for device and circuit degradation at corresponding frequencies. The results revealed over-predictions of degradation level by a time factor over 10.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"270-277"},"PeriodicalIF":2.0,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10918946","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143706804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-11DOI: 10.1109/JEDS.2025.3550268
Shunsuke Shitakata;Hiroshi Oka;Kimihiko Kato;Takumi Inaba;Shota Iizuka;Hidehiro Asai;Takahiro Mori
This study experimentally investigated hot carrier degradation (HCD) in Si-MOSFETs at cryogenic temperatures. Stress was applied to the devices at 4 K and 300 K, followed by temperature-dependent characterization from 4 K to 300 K to evaluate the degradation mechanism. The results indicated that at 4 K, the effect of HCD on current-voltage characteristics is attributable to band-edge states, whereas at 300 K, it is primarily due to deep states. Despite the temperature at which HCD occurred, both states are induced simultaneously by hot carriers. Deuterium termination of dangling bonds mitigates HCD even at 4 K, where degradation is caused by band-edge states. These results suggest that the band-edge states and deep states should be considered in conjunction, rather than in isolation, to fully understand the degradation behavior.
{"title":"Hot Carrier Degradation in Si n-MOSFETs at Cryogenic Temperatures","authors":"Shunsuke Shitakata;Hiroshi Oka;Kimihiko Kato;Takumi Inaba;Shota Iizuka;Hidehiro Asai;Takahiro Mori","doi":"10.1109/JEDS.2025.3550268","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3550268","url":null,"abstract":"This study experimentally investigated hot carrier degradation (HCD) in Si-MOSFETs at cryogenic temperatures. Stress was applied to the devices at 4 K and 300 K, followed by temperature-dependent characterization from 4 K to 300 K to evaluate the degradation mechanism. The results indicated that at 4 K, the effect of HCD on current-voltage characteristics is attributable to band-edge states, whereas at 300 K, it is primarily due to deep states. Despite the temperature at which HCD occurred, both states are induced simultaneously by hot carriers. Deuterium termination of dangling bonds mitigates HCD even at 4 K, where degradation is caused by band-edge states. These results suggest that the band-edge states and deep states should be considered in conjunction, rather than in isolation, to fully understand the degradation behavior.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"308-316"},"PeriodicalIF":2.0,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10922392","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143777773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-10DOI: 10.1109/JEDS.2025.3549721
Koya Okazaki;Takahito Yoshinaga;Nobukazu Teranishi;Atsushi Ono
A silicon-based image sensor is proposed, incorporating plasmonic diffraction gratings tailored to chief ray angles (CRAs), to enhance near-infrared (NIR) sensitivity improvement over a broad range of incident angles. Under quasi-surface plasmon resonance (quasi-SPR) conditions, the metal grating efficiently diffracted incident light into the silicon absorption layer. The period and width of the metal grating were adjusted at each pixel position according to CRAs, thereby improving the NIR sensitivity at sensor edges. The plasmonically diffracted light with angled chief ray was confined within the pixel photodiode. The photon confinement resulted in a significant improvement in absorption of approximately 37% or more, within an incident angle range of 30 degrees at a NIR wavelength of 940 nm and a silicon thickness of 3 μm. The improvement in NIR absorption over a broad incident angle range enhances the sensitivity of the entire sensor chip, representing a significant advancement for NIR cameras.
{"title":"Enhancement of Near-Infrared Sensitivity in Silicon-Based Image Sensors to Oblique Chief Rays via Quasi-Surface Plasmon Resonance","authors":"Koya Okazaki;Takahito Yoshinaga;Nobukazu Teranishi;Atsushi Ono","doi":"10.1109/JEDS.2025.3549721","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3549721","url":null,"abstract":"A silicon-based image sensor is proposed, incorporating plasmonic diffraction gratings tailored to chief ray angles (CRAs), to enhance near-infrared (NIR) sensitivity improvement over a broad range of incident angles. Under quasi-surface plasmon resonance (quasi-SPR) conditions, the metal grating efficiently diffracted incident light into the silicon absorption layer. The period and width of the metal grating were adjusted at each pixel position according to CRAs, thereby improving the NIR sensitivity at sensor edges. The plasmonically diffracted light with angled chief ray was confined within the pixel photodiode. The photon confinement resulted in a significant improvement in absorption of approximately 37% or more, within an incident angle range of 30 degrees at a NIR wavelength of 940 nm and a silicon thickness of 3 μm. The improvement in NIR absorption over a broad incident angle range enhances the sensitivity of the entire sensor chip, representing a significant advancement for NIR cameras.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"278-284"},"PeriodicalIF":2.0,"publicationDate":"2025-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10918731","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143706581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, the frequency (f) dependence of trap generation in Si n-channel fin field-effect transistors (n-FinFETs) under AC positive bias temperature instability (PBTI) stress is investigated by fast direct-current current-voltage (DCIV) method and the discharging-based multi-pulse energy profiling (DMP) technique. The experimental results show that both interface trap generation ($Delta $ NIT) and bulk trap generation ($Delta $ NOT) of n-FinFET under AC PBTI stress are almost independent of the AC frequency. However, further analysis shows that $Delta $ NOT consists of shallow traps near EC of Si and deep traps near Ev of Si. Moreover, about 22% of deep traps decrease with shallow traps increasing under 1.4V overdrive voltage (Vov) at 125°C with AC bias frequency increasing from 10 Hz to 1 MHz.
{"title":"Understanding Frequency Dependence of Trap Generation Under AC Positive Bias Temperature Instability Stress in Si n-FinFETs","authors":"Yunfei Shi;Hao Chang;Hong Yang;Qiangzhu Zhang;Qianqian Liu;Bo Tang;Longda Zhou;Zhigang Ji;Junjie Li;Xiaobin He;Junfeng Li;Huaxiang Yin;Xiaolei Wang;Jun Luo;Wenwu Wang","doi":"10.1109/JEDS.2025.3567049","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3567049","url":null,"abstract":"In this paper, the frequency (f) dependence of trap generation in Si n-channel fin field-effect transistors (n-FinFETs) under AC positive bias temperature instability (PBTI) stress is investigated by fast direct-current current-voltage (DCIV) method and the discharging-based multi-pulse energy profiling (DMP) technique. The experimental results show that both interface trap generation (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>NIT) and bulk trap generation (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>NOT) of n-FinFET under AC PBTI stress are almost independent of the AC frequency. However, further analysis shows that <inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>NOT consists of shallow traps near EC of Si and deep traps near Ev of Si. Moreover, about 22% of deep traps decrease with shallow traps increasing under 1.4V overdrive voltage (Vov) at 125°C with AC bias frequency increasing from 10 Hz to 1 MHz.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"450-455"},"PeriodicalIF":2.0,"publicationDate":"2025-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10994476","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144170896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-06DOI: 10.1109/JEDS.2025.3548595
Yeonsil Yang;Jongmin Lee;Jang Hyun Kim
In this paper, we analyze the electrical and thermal characteristics through Drain-Extended Fin Field-effect Transistor (DeFinFET) using separated high-k field plates. In this article, we first compare the structure using silicon dioxide (SiO2) as the field plate near the drain with that using aluminum oxide (Al2O3). The maximum lattice temperature ($T_{max}$ ) in the hafnium oxide (HfO2)/SiO2 structure is 391.953 K under the same current condition, whereas $T_{max}$ is reduced to 360.941 K in the HfO2/Al2O3 structure, indicating improved thermal management. Similarly, the thermal resistance $(R_th)$ is reduced by 8.73% in the Al2O3 based structure, indicating improved thermal characteristics. Heat flux analysis results show that 60.1% of the generated heat is dissipated through the extended drain region, which identifies the heat dissipation path of the device. And when the length of the Al2O3 field plate in the HfO2/Al2O3 structure was changed to 20 nm, 40 nm, 60 nm, and 80 nm, the $R_{mathrm{th}}$ of the 80 nm configuration was found to achieve the best thermal performance with a thermal resistance of 217.091 μm · K/mW. In addition, in this structure, the drain current reduction rate due to SHE was the lowest at 12.1%, and excellent breakdown voltage $(V_{mathrm{BD}})$ was derived because the electric field was not concentrated at the field plate junction near the drain. Consequently, the proposed device has potential application to high voltage (HV) System on Chip (SoC).
{"title":"Thermal Characteristics Enhancement of Drain-Extended FinFETs for System on Chip Applications With Dual High-k Field Plates","authors":"Yeonsil Yang;Jongmin Lee;Jang Hyun Kim","doi":"10.1109/JEDS.2025.3548595","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3548595","url":null,"abstract":"In this paper, we analyze the electrical and thermal characteristics through Drain-Extended Fin Field-effect Transistor (DeFinFET) using separated high-k field plates. In this article, we first compare the structure using silicon dioxide (SiO2) as the field plate near the drain with that using aluminum oxide (Al2O3). The maximum lattice temperature (<inline-formula> <tex-math>$T_{max}$ </tex-math></inline-formula>) in the hafnium oxide (HfO2)/SiO2 structure is 391.953 K under the same current condition, whereas <inline-formula> <tex-math>$T_{max}$ </tex-math></inline-formula> is reduced to 360.941 K in the HfO2/Al2O3 structure, indicating improved thermal management. Similarly, the thermal resistance <inline-formula> <tex-math>$(R_th)$ </tex-math></inline-formula> is reduced by 8.73% in the Al2O3 based structure, indicating improved thermal characteristics. Heat flux analysis results show that 60.1% of the generated heat is dissipated through the extended drain region, which identifies the heat dissipation path of the device. And when the length of the Al2O3 field plate in the HfO2/Al2O3 structure was changed to 20 nm, 40 nm, 60 nm, and 80 nm, the <inline-formula> <tex-math>$R_{mathrm{th}}$ </tex-math></inline-formula> of the 80 nm configuration was found to achieve the best thermal performance with a thermal resistance of 217.091 μm · K/mW. In addition, in this structure, the drain current reduction rate due to SHE was the lowest at 12.1%, and excellent breakdown voltage <inline-formula> <tex-math>$(V_{mathrm{BD}})$ </tex-math></inline-formula> was derived because the electric field was not concentrated at the field plate junction near the drain. Consequently, the proposed device has potential application to high voltage (HV) System on Chip (SoC).","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"182-188"},"PeriodicalIF":2.0,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10915199","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-06DOI: 10.1109/JEDS.2025.3548886
Chang-Jiun Lai;Ming-Dou Ker
Integrated circuits are susceptible to electrostatic discharge (ESD) events. Real-time detection and alerting of ESD events in semiconductor manufacturing environments is the key to achieving well ESD control. Additionally, the magnitude and duration of an ESD event are strongly correlated with the specific type of ESD events. The development of a novel ESD event detector, integrated on a single chip and featuring a logarithmic amplifier, a magnitude discriminator, and a time discriminator, has been motivated by this. This detector has been designed and fabricated in a 0.18-$mu $ m CMOS process. The magnitude of the ESD event can be detected and converted to 5-bit digital output codes, whereas the time duration of the ESD event can be converted to 3-bit digital output codes by the newly developed ESD event detector. It has been proven in field applications that the detected ESD events can be successfully transmitted to the ESD control center through the RF Wi-Fi module, enabling real-time ESD monitoring and control in manufacturing environments.
{"title":"Real-Time ESD Monitoring and Control in Semiconductor Manufacturing Environments With Silicon Chip of ESD Event Detection","authors":"Chang-Jiun Lai;Ming-Dou Ker","doi":"10.1109/JEDS.2025.3548886","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3548886","url":null,"abstract":"Integrated circuits are susceptible to electrostatic discharge (ESD) events. Real-time detection and alerting of ESD events in semiconductor manufacturing environments is the key to achieving well ESD control. Additionally, the magnitude and duration of an ESD event are strongly correlated with the specific type of ESD events. The development of a novel ESD event detector, integrated on a single chip and featuring a logarithmic amplifier, a magnitude discriminator, and a time discriminator, has been motivated by this. This detector has been designed and fabricated in a 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS process. The magnitude of the ESD event can be detected and converted to 5-bit digital output codes, whereas the time duration of the ESD event can be converted to 3-bit digital output codes by the newly developed ESD event detector. It has been proven in field applications that the detected ESD events can be successfully transmitted to the ESD control center through the RF Wi-Fi module, enabling real-time ESD monitoring and control in manufacturing environments.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"252-262"},"PeriodicalIF":2.0,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10915207","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143688051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-05DOI: 10.1109/JEDS.2025.3561075
Jin Huang;Rong Zhao;Shulong Wang;Xingyuan Yan;Hao Zhou;Liutao Li;Shupeng Chen;Hongxia Liu
Fully Depleted Silicon on Insulator (FDSOI) technology can solve the short channel effect very effectively, with low power consumption, and low voltage, and can improve the subthreshold characteristics of the device. In addition, FDSOI devices have good radiation resistance, which has become an important research object in the field of device research. Single event effect (SEE) is an important index of radiation resistance of FDSOI devices. At present, the research on SEE of FDSOI devices typically employs heavy-ion irradiation experiments and TCAD software simulations. Taking FDSOI technology as an example, this paper presents a research method of device modeling and performance prediction based on deep learning. The accuracy of the peak of transient current $(I_{peak})$ predicted by this method is 96.45%, the accuracy of total collected charge $(Q_{total})$ is 97.86%, and the determination coefficient of drain transient current pulse (It) is 0.97717. This method can obviously improve the simulation speed and reduce the calculation cost, and provide a new feasible method for the research of FDSOI devices.
{"title":"Prediction of Single Event Effect in Inverter Circuit Based on Deep Learning","authors":"Jin Huang;Rong Zhao;Shulong Wang;Xingyuan Yan;Hao Zhou;Liutao Li;Shupeng Chen;Hongxia Liu","doi":"10.1109/JEDS.2025.3561075","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3561075","url":null,"abstract":"Fully Depleted Silicon on Insulator (FDSOI) technology can solve the short channel effect very effectively, with low power consumption, and low voltage, and can improve the subthreshold characteristics of the device. In addition, FDSOI devices have good radiation resistance, which has become an important research object in the field of device research. Single event effect (SEE) is an important index of radiation resistance of FDSOI devices. At present, the research on SEE of FDSOI devices typically employs heavy-ion irradiation experiments and TCAD software simulations. Taking FDSOI technology as an example, this paper presents a research method of device modeling and performance prediction based on deep learning. The accuracy of the peak of transient current <inline-formula> <tex-math>$(I_{peak})$ </tex-math></inline-formula> predicted by this method is 96.45%, the accuracy of total collected charge <inline-formula> <tex-math>$(Q_{total})$ </tex-math></inline-formula> is 97.86%, and the determination coefficient of drain transient current pulse (It) is 0.97717. This method can obviously improve the simulation speed and reduce the calculation cost, and provide a new feasible method for the research of FDSOI devices.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"431-438"},"PeriodicalIF":2.0,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10982521","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144073414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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