The conductivity of tungsten disulfide (WS2) films using sputtering, which is a physical vapor deposition (PVD), was enhanced using a chlorine (Cl2)-plasma treatment and sulfur-vapor annealing (SVA). For WS2 films to be used in thermoelectric devices, its carrier concentration must be controlled. Therefore, we exposed WS2 films to Cl2-plasma as a doping method. In addition, SVA was performed to improve the crystallinity of the film and potentially introduce activating dopants. Consequently, the conductivity of the Cl2-plasma-treated PVD-WS2 films (0.440 S/m) more than doubled compared with that of an untreated PVD-WS2 film (0.201 S/m). The doping type in this experiment is considered to be n-type on the basis of a positive peak shift observed in the X-ray photoelectron spectra.
二硫化钨（WS2）薄膜是一种物理气相沉积（PVD）技术，采用溅射法（即物理气相沉积），通过氯（Cl2）等离子体处理和硫气退火（SVA）增强了其导电性。要将 WS2 薄膜用于热电设备，必须控制其载流子浓度。因此，我们将 WS2 薄膜暴露在 Cl2-等离子体中，作为一种掺杂方法。此外，还进行了 SVA 处理，以提高薄膜的结晶度，并可能引入活化掺杂剂。结果，经 Cl2- 等离子体处理的 PVD-WS2 薄膜的电导率（0.440 S/m）比未经处理的 PVD-WS2 薄膜的电导率（0.201 S/m）提高了一倍多。根据 X 射线光电子能谱中观察到的正峰值移动，本实验中的掺杂类型被认为是 n 型。
{"title":"Conductivity Enhancement of PVD-WS2 Films Using Cl2-Plasma Treatment Followed by Sulfur-Vapor Annealing","authors":"Keita Kurohara;Shinya Imai;Takuya Hamada;Tetsuya Tatsumi;Shigetaka Tomiya;Kuniyuki Kakushima;Kazuo Tsutsui;Hitoshi Wakabayashi","doi":"10.1109/JEDS.2024.3378745","DOIUrl":"10.1109/JEDS.2024.3378745","url":null,"abstract":"The conductivity of tungsten disulfide (WS2) films using sputtering, which is a physical vapor deposition (PVD), was enhanced using a chlorine (Cl2)-plasma treatment and sulfur-vapor annealing (SVA). For WS2 films to be used in thermoelectric devices, its carrier concentration must be controlled. Therefore, we exposed WS2 films to Cl2-plasma as a doping method. In addition, SVA was performed to improve the crystallinity of the film and potentially introduce activating dopants. Consequently, the conductivity of the Cl2-plasma-treated PVD-WS2 films (0.440 S/m) more than doubled compared with that of an untreated PVD-WS2 film (0.201 S/m). The doping type in this experiment is considered to be n-type on the basis of a positive peak shift observed in the X-ray photoelectron spectra.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10475166","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140171957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The compatibility of the advanced BSIM-CMG to the low frequency noise (LFN) simulation in amorphous IZO TFTs is evaluated over subthreshold and linear regions. Two kinds of devices with SiO2-SiNx and Al2O3 gate insulators are studied. In these devices, the 1/f noise is confirmed as the main component of LFN. Then the dominated origin of the 1/f noise is explained by the $Delta text{N}$ model in devices with SiO2-SiNx layers, and by the $Delta text{N}$ - $Delta mu $ model in devices with Al2O3 layers, respectively. Based on these models, the interficial traps density and the Hooge’s parameters are further calculated, and then applied to the extraction of noise parameters (NOIAeff, NOIB and NOIC) in BSIM-CMG. Compared to the measured data, the simulated results indicate that the noise can be well simulated by the improved BSIM-CMG both in the subthreshold and linear regions of IZO TFTs. It provides a comprehensive evaluation on the suitability of the BSIM-CMG for 1/f noise modelling in amorphous metal oxide TFTs.
{"title":"Compatibility of the BSIM-CMG to the Low-Frequency Noise Simulation in Subthreshold and Linear Regions of Amorphous InZnO TFTs","authors":"Yayi Chen;Xingji Liu;Dengyun Lei;Yuan Liu;Rongsheng Chen;Yao Ni;Hoi-Sing Kwok;Wei Zhong","doi":"10.1109/JEDS.2024.3375867","DOIUrl":"10.1109/JEDS.2024.3375867","url":null,"abstract":"The compatibility of the advanced BSIM-CMG to the low frequency noise (LFN) simulation in amorphous IZO TFTs is evaluated over subthreshold and linear regions. Two kinds of devices with SiO2-SiNx and Al2O3 gate insulators are studied. In these devices, the 1/f noise is confirmed as the main component of LFN. Then the dominated origin of the 1/f noise is explained by the \u0000<inline-formula> <tex-math>$Delta text{N}$ </tex-math></inline-formula>\u0000 model in devices with SiO2-SiNx layers, and by the \u0000<inline-formula> <tex-math>$Delta text{N}$ </tex-math></inline-formula>\u0000-\u0000<inline-formula> <tex-math>$Delta mu $ </tex-math></inline-formula>\u0000 model in devices with Al2O3 layers, respectively. Based on these models, the interficial traps density and the Hooge’s parameters are further calculated, and then applied to the extraction of noise parameters (NOIAeff, NOIB and NOIC) in BSIM-CMG. Compared to the measured data, the simulated results indicate that the noise can be well simulated by the improved BSIM-CMG both in the subthreshold and linear regions of IZO TFTs. It provides a comprehensive evaluation on the suitability of the BSIM-CMG for 1/f noise modelling in amorphous metal oxide TFTs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10466727","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140147154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
IGBT modules are core components of power electronic converters, and their reliability has gained significant attention. Among various reliability concerns, bond wire fatigue is a prominent issue. Bond wire fatigue can alter the electrical characteristics of IGBT modules, affecting the turn-off process of the IGBT. Consequently, it leads to changes in the collector-emitter voltage spike and the auxiliary emitter-emitter voltage spike during the turn-off process. The paper proposes the utilization of the K factor parameter which is not affected by the collector current and junction temperature, based on the collector-emitter voltage spike and the auxiliary emitter-emitter voltage spike, for bond wire fatigue monitoring of IGBT modules. Additionally, the monitoring of bond wire fatigue and junction temperature of IGBT modules was achieved based on the K factor parameter and the auxiliary emitter-emitter voltage spike. This provides a basis for the reliability assessment of IGBT modules.
IGBT 模块是电力电子转换器的核心部件，其可靠性已受到广泛关注。在各种可靠性问题中，键合线疲劳是一个突出问题。键合线疲劳会改变 IGBT 模块的电气特性，影响 IGBT 的关断过程。因此，它会导致关断过程中集电极-发射极电压尖峰和辅助发射极-发射极电压尖峰发生变化。本文根据集电极-发射极电压尖峰和辅助发射极-发射极电压尖峰，提出利用不受集电极电流和结温影响的 K 因子参数来监测 IGBT 模块的键合导线疲劳。此外，基于 K 因子参数和辅助发射极-发射极电压尖峰，实现了对 IGBT 模块键合线疲劳和结温的监测。这为 IGBT 模块的可靠性评估提供了依据。
{"title":"An Online Monitoring Method for Bond Wire Fatigue in IGBT Module","authors":"Hongtao Liu;Fei Wang;Xiaokang Zhang;Weiyi Xia;Lintao Ren","doi":"10.1109/JEDS.2024.3399554","DOIUrl":"10.1109/JEDS.2024.3399554","url":null,"abstract":"IGBT modules are core components of power electronic converters, and their reliability has gained significant attention. Among various reliability concerns, bond wire fatigue is a prominent issue. Bond wire fatigue can alter the electrical characteristics of IGBT modules, affecting the turn-off process of the IGBT. Consequently, it leads to changes in the collector-emitter voltage spike and the auxiliary emitter-emitter voltage spike during the turn-off process. The paper proposes the utilization of the K factor parameter which is not affected by the collector current and junction temperature, based on the collector-emitter voltage spike and the auxiliary emitter-emitter voltage spike, for bond wire fatigue monitoring of IGBT modules. Additionally, the monitoring of bond wire fatigue and junction temperature of IGBT modules was achieved based on the K factor parameter and the auxiliary emitter-emitter voltage spike. This provides a basis for the reliability assessment of IGBT modules.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10529136","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140928941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The string (STR) with various geometrical profiles in 3-D NAND flash cause the degradation of program efficiency. This is because the program speed differences among WL layers within the STR are caused by the geometrical properties observed through measurement results. In this work, we propose the method to reduce the program speed differences based on a word-line (WL) grouping in terms of threshold voltage (Vth) distribution to compensate for the program start voltage (Vstart). To address various geometrical profiles, we consider a flexible compensation method through $Delta $ Peak_Vth, i.e., the net amount of movement from the erase to the program state. $Delta $ Peak_Vth according to WL layers clearly distinguished the geometrical properties among WL layers, and through this, the linearity of $Delta $ Peak_Vth is frequently observed for specific WL layer intervals with taper profile. Utilizing this linearity, we conducted the WL grouping and successfully demonstrated $text{V}_{mathrm{ start}}$ compensation by applying the proposed method to each WL group through the measurement of a commercial 3-D NAND package. Moreover, the reduced WL grouping method is also contrived to relax circuit design complications and evaluated the usefulness of the proposed method.
{"title":"Program Start Bias Grouping to Compensate for the Geometric Property of a String in 3-D NAND Flash Memory","authors":"Sungju Kim;Sangmin Ahn;Sechun Park;Jongwoo Kim;Hyungcheol Shin","doi":"10.1109/JEDS.2024.3372971","DOIUrl":"10.1109/JEDS.2024.3372971","url":null,"abstract":"The string (STR) with various geometrical profiles in 3-D NAND flash cause the degradation of program efficiency. This is because the program speed differences among WL layers within the STR are caused by the geometrical properties observed through measurement results. In this work, we propose the method to reduce the program speed differences based on a word-line (WL) grouping in terms of threshold voltage (Vth) distribution to compensate for the program start voltage (Vstart). To address various geometrical profiles, we consider a flexible compensation method through \u0000<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>\u0000Peak_Vth, i.e., the net amount of movement from the erase to the program state. \u0000<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>\u0000Peak_Vth according to WL layers clearly distinguished the geometrical properties among WL layers, and through this, the linearity of \u0000<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>\u0000Peak_Vth is frequently observed for specific WL layer intervals with taper profile. Utilizing this linearity, we conducted the WL grouping and successfully demonstrated \u0000<inline-formula> <tex-math>$text{V}_{mathrm{ start}}$ </tex-math></inline-formula>\u0000 compensation by applying the proposed method to each WL group through the measurement of a commercial 3-D NAND package. Moreover, the reduced WL grouping method is also contrived to relax circuit design complications and evaluated the usefulness of the proposed method.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10459337","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140074155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gate-tunable Schottky barrier diodes find many applications in logic transistors, photodiodes, and sensors. In this work, the electrical properties of Schottky barrier diodes with graphene/pentacene junctions and additional gates were investigated in detail. The results of modeling equations that considered the ideality factor, series resistance, and effective barrier-height according to the gate bias (Vg) were in good agreement with the experimental results. In addition, the dominant conduction mechanism when the effective barrier-height was controlled by Vg is discussed from the perspective of the temperature-dependent currents in Schottky barrier diodes. This work provides critical information that aids our understanding of gated Schottky diodes with graphene/pentacene junctions, increasing the possible practical applications thereof.
{"title":"Electrically Tunable Ideality Factor and Series Resistance of Gate-Controlled Graphene/Pentacene Schottky Junctions","authors":"Tae Yoon Lee;Yoon-Jeong Kim;Seokhoon Ahn;Dae-Young Jeon","doi":"10.1109/JEDS.2024.3397014","DOIUrl":"10.1109/JEDS.2024.3397014","url":null,"abstract":"Gate-tunable Schottky barrier diodes find many applications in logic transistors, photodiodes, and sensors. In this work, the electrical properties of Schottky barrier diodes with graphene/pentacene junctions and additional gates were investigated in detail. The results of modeling equations that considered the ideality factor, series resistance, and effective barrier-height according to the gate bias (Vg) were in good agreement with the experimental results. In addition, the dominant conduction mechanism when the effective barrier-height was controlled by Vg is discussed from the perspective of the temperature-dependent currents in Schottky barrier diodes. This work provides critical information that aids our understanding of gated Schottky diodes with graphene/pentacene junctions, increasing the possible practical applications thereof.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10520713","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140882433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-06DOI: 10.1109/JEDS.2024.3373889
Junhyeong Park;Yumin Yun;Minji Kim;Soo-Yeon Lee
In this paper, we conducted a simulation of an indium-gallium-zinc oxide (IGZO)-based neuromorphic system and proposed layer-by-layer membrane capacitor (Cmem) optimization for integrate-and-fire (I&F) neuron circuits to minimize the accuracy drop in spiking neural network (SNN). The fabricated synaptic transistor exhibited linear 32 synaptic weights with a large dynamic range $(sim 846$ ), and an n-type-only IGZO I&F neuron circuit was proposed and verified by HSPICE simulation. The network, consisting of three fully connected layers, was evaluated with an offline learning method employing synaptic transistor and I&F circuit models for three datasets: MNIST, Fashion-MNIST, and CIFAR-10. For offline learning, accuracy drop can occur due to information loss caused by overflow or underflow in neurons, which is largely affected by Cmem. To address this problem, we introduced a layer-by-layer ${mathrm{ C}}_{mathrm{ mem}}$ optimization method that adjusts appropriate ${mathrm{ C}}_{mathrm{ mem}}$ for each layer to minimize the information loss. As a result, high SNN accuracy was achieved for MNIST, Fashion-MNIST, and CIFAR-10 at 98.42%, 89.16%, and 48.06%, respectively. Furthermore, the optimized system showed minimal accuracy degradation under device-to-device variation.
{"title":"Simulation and Optimization of IGZO-Based Neuromorphic System for Spiking Neural Networks","authors":"Junhyeong Park;Yumin Yun;Minji Kim;Soo-Yeon Lee","doi":"10.1109/JEDS.2024.3373889","DOIUrl":"10.1109/JEDS.2024.3373889","url":null,"abstract":"In this paper, we conducted a simulation of an indium-gallium-zinc oxide (IGZO)-based neuromorphic system and proposed layer-by-layer membrane capacitor (Cmem) optimization for integrate-and-fire (I&F) neuron circuits to minimize the accuracy drop in spiking neural network (SNN). The fabricated synaptic transistor exhibited linear 32 synaptic weights with a large dynamic range \u0000<inline-formula> <tex-math>$(sim 846$ </tex-math></inline-formula>\u0000), and an n-type-only IGZO I&F neuron circuit was proposed and verified by HSPICE simulation. The network, consisting of three fully connected layers, was evaluated with an offline learning method employing synaptic transistor and I&F circuit models for three datasets: MNIST, Fashion-MNIST, and CIFAR-10. For offline learning, accuracy drop can occur due to information loss caused by overflow or underflow in neurons, which is largely affected by Cmem. To address this problem, we introduced a layer-by-layer \u0000<inline-formula> <tex-math>${mathrm{ C}}_{mathrm{ mem}}$ </tex-math></inline-formula>\u0000 optimization method that adjusts appropriate \u0000<inline-formula> <tex-math>${mathrm{ C}}_{mathrm{ mem}}$ </tex-math></inline-formula>\u0000 for each layer to minimize the information loss. As a result, high SNN accuracy was achieved for MNIST, Fashion-MNIST, and CIFAR-10 at 98.42%, 89.16%, and 48.06%, respectively. Furthermore, the optimized system showed minimal accuracy degradation under device-to-device variation.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10461007","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140055338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Vertical extrinsic photoconductive semiconductor switches (PCSSs) are presented with initial characteristics comparison between V-doped 4H-SiC and Fe-doped GaN PCSS under axial triggering such as dark resistance, photoconductivity, power output, and breakdown behavior. Experiments are carried out under the 532-nm-wavelength laser with mJ-level energy and a pulse width of 30 ns. Photoconductive experiments show that the photoelectric conversion efficiency of GaN PCSS is 2.27 times higher than 4H-SiC PCSS with the same electric field strength under different laser energies from 1 mJ to 5 mJ. 4H-SiC PCSS with a dark-state resistance of $10^{12} Omega cdot $ cm can withstand a bias voltage of 8 kV (16 kV/mm) and laser energy of 8 mJ and the maximum output power is up to 428.7 kW, while that of GaN can only stand a bias voltage of 1 kV (2.9 kV/mm) because of low dark resistance and defect. Obvious cracks of 4H-SiC PCSS can be observed from the breakdown image after breakdown occurs, while the dark-state resistance of GaN PCSS drops from $10^{6} Omega cdot $ cm to $10^{4} Omega cdot $ cm under high DC voltage.
{"title":"Characteristics Comparison of SiC and GaN Extrinsic Vertical Photoconductive Switches","authors":"Linglong Zeng;Langning Wang;Xinyue Niu;Fuyin Liu;Ting He;Yanran Gu;Muyu Yi;Jinmei Yao;Tao Xun;Hanwu Yang","doi":"10.1109/JEDS.2024.3372596","DOIUrl":"10.1109/JEDS.2024.3372596","url":null,"abstract":"Vertical extrinsic photoconductive semiconductor switches (PCSSs) are presented with initial characteristics comparison between V-doped 4H-SiC and Fe-doped GaN PCSS under axial triggering such as dark resistance, photoconductivity, power output, and breakdown behavior. Experiments are carried out under the 532-nm-wavelength laser with mJ-level energy and a pulse width of 30 ns. Photoconductive experiments show that the photoelectric conversion efficiency of GaN PCSS is 2.27 times higher than 4H-SiC PCSS with the same electric field strength under different laser energies from 1 mJ to 5 mJ. 4H-SiC PCSS with a dark-state resistance of \u0000<inline-formula> <tex-math>$10^{12} Omega cdot $ </tex-math></inline-formula>\u0000 cm can withstand a bias voltage of 8 kV (16 kV/mm) and laser energy of 8 mJ and the maximum output power is up to 428.7 kW, while that of GaN can only stand a bias voltage of 1 kV (2.9 kV/mm) because of low dark resistance and defect. Obvious cracks of 4H-SiC PCSS can be observed from the breakdown image after breakdown occurs, while the dark-state resistance of GaN PCSS drops from \u0000<inline-formula> <tex-math>$10^{6} Omega cdot $ </tex-math></inline-formula>\u0000 cm to \u0000<inline-formula> <tex-math>$10^{4} Omega cdot $ </tex-math></inline-formula>\u0000 cm under high DC voltage.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10458869","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140046184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a three-dimensional (3D) DRAM prototype, which is formed using oxide semiconductor FETs (OSFETs) monolithically stacked on a Si CMOS. The OSFETs are composed of a one-layer planar FET and two-layer vertical FETs (VFETs). The 1T1C memory cells in the VFET layers and a primary sense amplifier in the planar FET layer, which are formed using heterogeneous OSFETs, provide various circuit functions in the DRAM. The operation of the 3D DRAM in a 1-Mbit memory array is demonstrated for the first time. The results show that the proposed DRAM operates with read and write times of 60 ns and 50 ns, respectively. The leakage current of the memory cell is extremely low (comparable to an $2.2times 10^{-19}$ A/cell at 85°C), indicating that over 99% of the data are retained in the memory array after one hour at 85°C without refresh.
我们提出了一种三维（3D）DRAM 原型，它是利用在硅 CMOS 上单片堆叠的氧化物半导体场效应晶体管（OSFET）形成的。OSFET 由一层平面 FET 和两层垂直 FET（VFET）组成。VFET 层中的 1T1C 存储单元和平面 FET 层中的主感应放大器由异质 OSFET 组成，为 DRAM 提供各种电路功能。我们首次在 1-Mbit 存储阵列中演示了 3D DRAM 的运行。结果表明，拟议 DRAM 的读取和写入时间分别为 60 ns 和 50 ns。存储单元的漏电流极低（相当于 85°C 下 2.2/times 10^{-19}$ A/cell 的漏电流），这表明在 85°C 下不刷新的情况下，超过 99% 的数据可在一小时后保留在存储器阵列中。
{"title":"1-Mbit 3-D DRAM Using a Monolithically Stacked Structure of a Si CMOS and Heterogeneous IGZO FETs","authors":"Takeya Hirose;Yuki Okamoto;Yusuke Komura;Toshiki Mizuguchi;Toshihiko Saito;Minato Ito;Kiyotaka Kimura;Hiroki Inoue;Tatsuya Onuki;Yoshinori Ando;Hiromi Sawai;Tsutomu Murakawa;Hitoshi Kunitake;Hajime Kimura;Takanori Matsuzaki;Makoto Ikeda;Shunpei Yamazaki","doi":"10.1109/JEDS.2024.3372053","DOIUrl":"10.1109/JEDS.2024.3372053","url":null,"abstract":"We present a three-dimensional (3D) DRAM prototype, which is formed using oxide semiconductor FETs (OSFETs) monolithically stacked on a Si CMOS. The OSFETs are composed of a one-layer planar FET and two-layer vertical FETs (VFETs). The 1T1C memory cells in the VFET layers and a primary sense amplifier in the planar FET layer, which are formed using heterogeneous OSFETs, provide various circuit functions in the DRAM. The operation of the 3D DRAM in a 1-Mbit memory array is demonstrated for the first time. The results show that the proposed DRAM operates with read and write times of 60 ns and 50 ns, respectively. The leakage current of the memory cell is extremely low (comparable to an \u0000<inline-formula> <tex-math>$2.2times 10^{-19}$ </tex-math></inline-formula>\u0000 A/cell at 85°C), indicating that over 99% of the data are retained in the memory array after one hour at 85°C without refresh.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10457845","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140018245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-29DOI: 10.1109/JEDS.2024.3371455
S. Yuan;K. Omori;T. Yamaguchi;T. Ide;S. Muranaka;M. Inoue
The selectivity of chemical mechanical polishing (CMP) is successfully enhanced due to the modification of the film surface by ultra-high-dose ion implantation for the first time. The removal rate (RR) of CMP for SiO2 and Si3N4 films was changed by implanted ions. On the other hand, polycrystalline silicon (poly-Si) films had no change regardless of ion implantation. When C+ is implanted at $3times 10{^{{16}}}$ ions/cm2 into SiO2, the RR decreases by about 40% compared with that without implantation. However, no significant change was observed after the implantation of C+ at $1times 10{^{{16}}}$ ions/cm2 or Si+ to SiO2 and poly-Si films. New findings about CMP mechanism that are against Borst’s Langmuir-Hinshelwood model have been made when the film is modified by using high-dose implantation.
{"title":"Enhancement of Selectivity for Chemical Mechanical Polishing by Ultra-High-Dose C and Si Ion Implantation","authors":"S. Yuan;K. Omori;T. Yamaguchi;T. Ide;S. Muranaka;M. Inoue","doi":"10.1109/JEDS.2024.3371455","DOIUrl":"10.1109/JEDS.2024.3371455","url":null,"abstract":"The selectivity of chemical mechanical polishing (CMP) is successfully enhanced due to the modification of the film surface by ultra-high-dose ion implantation for the first time. The removal rate (RR) of CMP for SiO2 and Si3N4 films was changed by implanted ions. On the other hand, polycrystalline silicon (poly-Si) films had no change regardless of ion implantation. When C+ is implanted at \u0000<inline-formula> <tex-math>$3times 10{^{{16}}}$ </tex-math></inline-formula>\u0000 ions/cm2 into SiO2, the RR decreases by about 40% compared with that without implantation. However, no significant change was observed after the implantation of C+ at \u0000<inline-formula> <tex-math>$1times 10{^{{16}}}$ </tex-math></inline-formula>\u0000 ions/cm2 or Si+ to SiO2 and poly-Si films. New findings about CMP mechanism that are against Borst’s Langmuir-Hinshelwood model have been made when the film is modified by using high-dose implantation.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-02-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10454590","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140002042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The InP high-electron-mobility transistor (HEMT) is employed in cryogenic low-noise amplifiers (LNAs) for the readout of faint microwave signals in quantum computing. The performance of such LNAs is ultimately limited by the properties of the active $mathrm {In_{x}Ga_{1-x}As}$ channel in the InP HEMT. In this study, we have investigated the noise performance of 100-nm gate-length InP HEMTs used in cryogenic LNAs for amplification of qubits. The channel indium content in the InP HEMTs was 53, 60 and 70%. Hall measurements of the epitaxial materials and dc characterization of the InP HEMTs confirmed the superior transport properties of the channel structures. An indirect method involving an LNA and small-signal noise modeling was used for extracting the channel noise with high accuracy. Under noise-optimized bias, we observed that the 60% indium channel InP HEMT exhibited the lowest drain noise temperature. The difference in LNA noise temperature among InP HEMTs became more pronounced with decreasing drain voltage and current. An average noise temperature and average gain of 3.3 K and 21 dB, respectively, for a 4–8 GHz three-stage hybrid cryogenic LNA using 60% indium channel InP HEMTs was measured at a dc power consumption of $108 ~mu text{W}$ . To the best of the authors’ knowledge, this is a new state-of-the-art for a C-band LNA operating below 1 mW. The higher drain noise temperature observed for 53 and 70% indium channels InP HEMTs can be attributed to a combination of thermal noise in the channel and real-space transfer of electrons from the channel to the barrier. This report gives experimental evidence of an optimum channel indium content in the InP HEMT used in LNAs for qubit amplification.
{"title":"Investigation of Noise Properties in the InP HEMT for LNAs in Qubit Amplification: Effects From Channel Indium Content","authors":"Junjie Li;Johan Bergsten;Arsalan Pourkabirian;Jan Grahn","doi":"10.1109/JEDS.2024.3371905","DOIUrl":"10.1109/JEDS.2024.3371905","url":null,"abstract":"The InP high-electron-mobility transistor (HEMT) is employed in cryogenic low-noise amplifiers (LNAs) for the readout of faint microwave signals in quantum computing. The performance of such LNAs is ultimately limited by the properties of the active \u0000<inline-formula> <tex-math>$mathrm {In_{x}Ga_{1-x}As}$ </tex-math></inline-formula>\u0000 channel in the InP HEMT. In this study, we have investigated the noise performance of 100-nm gate-length InP HEMTs used in cryogenic LNAs for amplification of qubits. The channel indium content in the InP HEMTs was 53, 60 and 70%. Hall measurements of the epitaxial materials and dc characterization of the InP HEMTs confirmed the superior transport properties of the channel structures. An indirect method involving an LNA and small-signal noise modeling was used for extracting the channel noise with high accuracy. Under noise-optimized bias, we observed that the 60% indium channel InP HEMT exhibited the lowest drain noise temperature. The difference in LNA noise temperature among InP HEMTs became more pronounced with decreasing drain voltage and current. An average noise temperature and average gain of 3.3 K and 21 dB, respectively, for a 4–8 GHz three-stage hybrid cryogenic LNA using 60% indium channel InP HEMTs was measured at a dc power consumption of \u0000<inline-formula> <tex-math>$108 ~mu text{W}$ </tex-math></inline-formula>\u0000. To the best of the authors’ knowledge, this is a new state-of-the-art for a C-band LNA operating below 1 mW. The higher drain noise temperature observed for 53 and 70% indium channels InP HEMTs can be attributed to a combination of thermal noise in the channel and real-space transfer of electrons from the channel to the barrier. This report gives experimental evidence of an optimum channel indium content in the InP HEMT used in LNAs for qubit amplification.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-02-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10454583","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140002001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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