Pub Date : 2024-12-27DOI: 10.1109/JEDS.2024.3523286
Kang Hee Lee;Mincheol Kim;Jongmin Lee;Jang Hyun Kim
We analyzed the impact of self-heating effect (SHE) on fully depleted-silicon on insulator (FD-SOI) CMOS inverter at the 28 nm technology node, considering both DC and AC operations. Specifically, we focused on investigating the principles behind how SHE influences inverter operating characteristics. To analyze the operating characteristics, we employed 2-D technology computer-aided design (TCAD) mixed mode simulation by Synopsys SentaurusTM. In DC operation, the maximum lattice temperature for n-MOSFET and p-MOSFET are 436 K and 449 K, respectively, resulting in a current degradation of 7.9%. Due to the shifted p/n ratio, the gain also varied, with values of 3.65 V/V for without SHE and 4.21 V/V for with SHE. In AC operation, the maximum temperature varies for each operating frequency: 439 K, 358 K, 324 K, and 319 K, from 10 MHz to 4 GHz. Consequently, the rate of p/n ratio deviation and the rate of voltage change over time vary accordingly. SHE exhibits a faster rate of change, showing a difference of 5.43% at 10 MHz. Analysis of propagation delay through an inverter chain showed a 10% increase at 10 MHz. The results indicate that with SHE, the propagation delay increases, and the slew rate becomes steeper, suggesting improved switching characteristics and gain. However, this unintended consequence highlights the necessity of considering SHE-induced changes in CMOS inverter design to ensure reliable operation.
{"title":"Impact of Self-Heating Effect on DC and AC Performance of FD-SOI CMOS Inverter","authors":"Kang Hee Lee;Mincheol Kim;Jongmin Lee;Jang Hyun Kim","doi":"10.1109/JEDS.2024.3523286","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3523286","url":null,"abstract":"We analyzed the impact of self-heating effect (SHE) on fully depleted-silicon on insulator (FD-SOI) CMOS inverter at the 28 nm technology node, considering both DC and AC operations. Specifically, we focused on investigating the principles behind how SHE influences inverter operating characteristics. To analyze the operating characteristics, we employed 2-D technology computer-aided design (TCAD) mixed mode simulation by Synopsys SentaurusTM. In DC operation, the maximum lattice temperature for n-MOSFET and p-MOSFET are 436 K and 449 K, respectively, resulting in a current degradation of 7.9%. Due to the shifted p/n ratio, the gain also varied, with values of 3.65 V/V for without SHE and 4.21 V/V for with SHE. In AC operation, the maximum temperature varies for each operating frequency: 439 K, 358 K, 324 K, and 319 K, from 10 MHz to 4 GHz. Consequently, the rate of p/n ratio deviation and the rate of voltage change over time vary accordingly. SHE exhibits a faster rate of change, showing a difference of 5.43% at 10 MHz. Analysis of propagation delay through an inverter chain showed a 10% increase at 10 MHz. The results indicate that with SHE, the propagation delay increases, and the slew rate becomes steeper, suggesting improved switching characteristics and gain. However, this unintended consequence highlights the necessity of considering SHE-induced changes in CMOS inverter design to ensure reliable operation.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"41-48"},"PeriodicalIF":2.0,"publicationDate":"2024-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10816664","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-27DOI: 10.1109/JEDS.2024.3523394
Jingwen Chen;Claire Qing-Ying Huang;Xin Zhang;Sheng Dong;Xiye Yang
This letter reports a trap-assisted photomultiplication-type organic photodetector (PM-OPD) with a broad sensing range from 400 to 1400 nm. By easily tunning the donor/acceptor ratio in bulk-heterojunction layer consisting Poly([2,6’-4,8-di(5-ethylhexylthienyl)benzo[1,2-b;3,3-b]dithiophene]{3-fluoro-2[(2-ethylhexyl)carbonyl] thieno[3,4-b]thiophenediyl}) (PTB7-Th) and a novel non-fullerene acceptor (NFA) pendant 2,2’-(((2,5-bis(2-octyldodecyl)-3,6-dioxo-2,3,5,6-tetrahydropyrrolo [3,4-c]pyrrole-1,4-diyl)bis(thiophene-5,2-diyl))bis(4-oxonaphthalene-3(4H)-yl-1(4H)-ylidene)) dimalononitrile named DPP-QC, the device shows specifically a high external quantum efficiency (EQE) value of 112% and specific detectivity (D*) over $10^{10}$ Jones at 1200 nm at a light intensity of 0.108 mW/cm2. Meanwhile the PM-OPD shows ultra-fast response time $t_{r}$ and $t_{f}$ of 4.1 $mu $ s and 4.3 $mu $ s on microsecond ($mu $ s) scale. Our work proves that PM-type shortwave infrared (SWIR) OPD can simultaneously achieve high responsivity, broad-spectral response, fast response and well photodiode characteristics.
{"title":"A Trap-Assisted Photomultiplication-Type Organic Photodetector With High Detectivity From Visible to Shortwave Infrared Light","authors":"Jingwen Chen;Claire Qing-Ying Huang;Xin Zhang;Sheng Dong;Xiye Yang","doi":"10.1109/JEDS.2024.3523394","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3523394","url":null,"abstract":"This letter reports a trap-assisted photomultiplication-type organic photodetector (PM-OPD) with a broad sensing range from 400 to 1400 nm. By easily tunning the donor/acceptor ratio in bulk-heterojunction layer consisting Poly([2,6’-4,8-di(5-ethylhexylthienyl)benzo[1,2-b;3,3-b]dithiophene]{3-fluoro-2[(2-ethylhexyl)carbonyl] thieno[3,4-b]thiophenediyl}) (PTB7-Th) and a novel non-fullerene acceptor (NFA) pendant 2,2’-(((2,5-bis(2-octyldodecyl)-3,6-dioxo-2,3,5,6-tetrahydropyrrolo [3,4-c]pyrrole-1,4-diyl)bis(thiophene-5,2-diyl))bis(4-oxonaphthalene-3(4H)-yl-1(4H)-ylidene)) dimalononitrile named DPP-QC, the device shows specifically a high external quantum efficiency (EQE) value of 112% and specific detectivity (D*) over <inline-formula> <tex-math>$10^{10}$ </tex-math></inline-formula> Jones at 1200 nm at a light intensity of 0.108 mW/cm2. Meanwhile the PM-OPD shows ultra-fast response time <inline-formula> <tex-math>$t_{r}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$t_{f}$ </tex-math></inline-formula> of 4.1 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>s and 4.3 <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>s on microsecond (<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>s) scale. Our work proves that PM-type shortwave infrared (SWIR) OPD can simultaneously achieve high responsivity, broad-spectral response, fast response and well photodiode characteristics.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"73-78"},"PeriodicalIF":2.0,"publicationDate":"2024-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10816666","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-26DOI: 10.1109/JEDS.2024.3523278
Martin Ćalasan;Snežana Vujošević
This brief presents two new equivalent circuit schemes for triple-diode solar cell models (TDM). These schemes enable the formulation of an analytical relationship between current and voltage using the Lambert W function. A new Root Mean Square Error (RMSE) formula is also introduced. The models are validated on two solar cells and two panels under different conditions. Results show high accuracy and efficiency.
{"title":"Novel Triple Diode Solar Cells Equivalent Circuit Models With Lambert W Function Expressions","authors":"Martin Ćalasan;Snežana Vujošević","doi":"10.1109/JEDS.2024.3523278","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3523278","url":null,"abstract":"This brief presents two new equivalent circuit schemes for triple-diode solar cell models (TDM). These schemes enable the formulation of an analytical relationship between current and voltage using the Lambert W function. A new Root Mean Square Error (RMSE) formula is also introduced. The models are validated on two solar cells and two panels under different conditions. Results show high accuracy and efficiency.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"49-53"},"PeriodicalIF":2.0,"publicationDate":"2024-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10816474","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-25DOI: 10.1109/JEDS.2024.3522577
Ghader Darbandy;Malte Koch;Lukas M. Bongartz;Karl Leo;Hans Kleemann;Alexander Kloes
Organic electrochemical transistors (OECTs) are a class of promising neuromorphic devices due to their exceptional conductivity, ease of fabrication, and cost-effectiveness. These devices exhibit ionic behavior similar to biological synapses, enabling efficient switching. Developing a compact model for OECTs is challenging due to the complex interplay of electrochemical reactions, ion transport, interactions with electrons or holes, and charge carrier dynamics that must be accurately captured and integrated into a simplified framework. In this work, we develop a combined physics-based compact model that integrates the Nernst equation from electrochemistry with thermally activated charges from semiconductor physics. This model enables easy incorporation into circuit simulations and provides a simple core framework for further extensions to account for additional effects. We fabricated, characterized, and analyzed OECTs based on PEDOT:PSS, and the proposed compact model shows good agreement with our experimental data.
{"title":"Charge-Based Compact Modeling of OECTs for Neuromorphic Applications","authors":"Ghader Darbandy;Malte Koch;Lukas M. Bongartz;Karl Leo;Hans Kleemann;Alexander Kloes","doi":"10.1109/JEDS.2024.3522577","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3522577","url":null,"abstract":"Organic electrochemical transistors (OECTs) are a class of promising neuromorphic devices due to their exceptional conductivity, ease of fabrication, and cost-effectiveness. These devices exhibit ionic behavior similar to biological synapses, enabling efficient switching. Developing a compact model for OECTs is challenging due to the complex interplay of electrochemical reactions, ion transport, interactions with electrons or holes, and charge carrier dynamics that must be accurately captured and integrated into a simplified framework. In this work, we develop a combined physics-based compact model that integrates the Nernst equation from electrochemistry with thermally activated charges from semiconductor physics. This model enables easy incorporation into circuit simulations and provides a simple core framework for further extensions to account for additional effects. We fabricated, characterized, and analyzed OECTs based on PEDOT:PSS, and the proposed compact model shows good agreement with our experimental data.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"34-40"},"PeriodicalIF":2.0,"publicationDate":"2024-12-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10816051","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-04DOI: 10.1109/JEDS.2024.3511581
Jung Rae Cho;Donghyun Ryu;Donguk Kim;Wonjung Kim;Yeonwoo Kim;Changwook Kim;Yoon Kim;Myounggon Kang;Jiyong Woo;Dae Hwan Kim
Recently, three-dimensional FLASH memory with multi-level cell characteristics has attracted increasing attention to enhance the capabilities of artificial intelligence (AI) by leveraging computingin-memory (CIM) systems. The focus is to maximize the computing performance and design FLASH memory suitable for various AI algorithms, where the memory must achieve a highly controllable multi-level threshold voltage (VT). Therefore, we developed a SPICE compact model that can rapidly simulate charge trap FLASH cells for CIM to identify optimal programming conditions. SPICE simulation results of the transfer characteristics are in good agreement with the results of experimentally fabricated FLASH memory, showing a low error rate of 10%. The model was also validated against the results obtained from the TCAD tool, showing that a consistent VT change was computed in a shorter time than that required using TCAD. Then, the developed model was used to comprehensively investigate how single or multiple gate voltage (VG) pulses affect VT. Moreover, considering recent FLASH memory fabrication processes, we found that grain boundaries in polycrystalline silicon channel materials can be involved in deteriorating gate controllability. Therefore, optimizing the pulse scheme by correcting potential errors identified in advance through fast SPICE simulation can enable the accurate achievement of the specific analog states of the FLASH cells of the CIM architecture, boosting computing performance.
{"title":"Physics-Based SPICE-Compatible Compact Model of FLASH Memory With Poly-Si Channel for Computing-in-Memory Applications","authors":"Jung Rae Cho;Donghyun Ryu;Donguk Kim;Wonjung Kim;Yeonwoo Kim;Changwook Kim;Yoon Kim;Myounggon Kang;Jiyong Woo;Dae Hwan Kim","doi":"10.1109/JEDS.2024.3511581","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3511581","url":null,"abstract":"Recently, three-dimensional FLASH memory with multi-level cell characteristics has attracted increasing attention to enhance the capabilities of artificial intelligence (AI) by leveraging computingin-memory (CIM) systems. The focus is to maximize the computing performance and design FLASH memory suitable for various AI algorithms, where the memory must achieve a highly controllable multi-level threshold voltage (VT). Therefore, we developed a SPICE compact model that can rapidly simulate charge trap FLASH cells for CIM to identify optimal programming conditions. SPICE simulation results of the transfer characteristics are in good agreement with the results of experimentally fabricated FLASH memory, showing a low error rate of 10%. The model was also validated against the results obtained from the TCAD tool, showing that a consistent VT change was computed in a shorter time than that required using TCAD. Then, the developed model was used to comprehensively investigate how single or multiple gate voltage (VG) pulses affect VT. Moreover, considering recent FLASH memory fabrication processes, we found that grain boundaries in polycrystalline silicon channel materials can be involved in deteriorating gate controllability. Therefore, optimizing the pulse scheme by correcting potential errors identified in advance through fast SPICE simulation can enable the accurate achievement of the specific analog states of the FLASH cells of the CIM architecture, boosting computing performance.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1-7"},"PeriodicalIF":2.0,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10778276","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-27DOI: 10.1109/JEDS.2024.3507379
Song-Hyeon Kuk;Kyul Ko;Bong Ho Kim;Joon Pyo Kim;Jae-Hoon Han;Sang-Hyeon Kim
Ferroelectric polarization charge in doped-HfO2 such as HfZrOx (HZO) has a high surface density (~1014 cm-2) compared to the channel carrier (~1013 cm-2), thereby, ferroelectric polarization induces high electric field near the channel surface, critically impacting on the channel carrier behaviors in metal-ferroelectric-insulator-semiconductor (MFIS) ferroelectric field-effect-transistor (FEFET). In this context, channel mobility degradation by ferroelectric polarization and trapped charges will become a concern, because it is well-known that a huge number of charges (~1014 cm-2) are trapped at the gate stack. Especially, channel mobility during the read operation is required to be discussed, because FEFETs are typically targeted for non-volatile memory applications. In this work, we show that channel mobility (μch) and surface inversion carrier density (Ns,inv) in the n-channel FEFET (nFEFET) during read can be significantly different in the multi-level-cell (MLC) operation. This indicates that trapped carriers significantly degrade mobility and the degradation has a “history” effect, revealing that μch and Ns,inv are determined by overlapped effects of ferroelectric polarization and trapped charges. In addition, it is suggested that ferroelectric polarization induces remote phonon scattering. The complicated device physics of the MFIS FEFET indicates that channel mobility should be carefully modeled in the device simulation.
{"title":"Channel Mobility and Inversion Carrier Density in MFIS FEFET: Deep Insights Into Device Physics for Non-Volatile Memory Applications","authors":"Song-Hyeon Kuk;Kyul Ko;Bong Ho Kim;Joon Pyo Kim;Jae-Hoon Han;Sang-Hyeon Kim","doi":"10.1109/JEDS.2024.3507379","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3507379","url":null,"abstract":"Ferroelectric polarization charge in doped-HfO2 such as HfZrOx (HZO) has a high surface density (~1014 cm-2) compared to the channel carrier (~1013 cm-2), thereby, ferroelectric polarization induces high electric field near the channel surface, critically impacting on the channel carrier behaviors in metal-ferroelectric-insulator-semiconductor (MFIS) ferroelectric field-effect-transistor (FEFET). In this context, channel mobility degradation by ferroelectric polarization and trapped charges will become a concern, because it is well-known that a huge number of charges (~1014 cm-2) are trapped at the gate stack. Especially, channel mobility during the read operation is required to be discussed, because FEFETs are typically targeted for non-volatile memory applications. In this work, we show that channel mobility (μch) and surface inversion carrier density (Ns,inv) in the n-channel FEFET (nFEFET) during read can be significantly different in the multi-level-cell (MLC) operation. This indicates that trapped carriers significantly degrade mobility and the degradation has a “history” effect, revealing that μch and Ns,inv are determined by overlapped effects of ferroelectric polarization and trapped charges. In addition, it is suggested that ferroelectric polarization induces remote phonon scattering. The complicated device physics of the MFIS FEFET indicates that channel mobility should be carefully modeled in the device simulation.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"8-14"},"PeriodicalIF":2.0,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10769066","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-27DOI: 10.1109/JEDS.2024.3506922
Hui Wang;Pengyu Lai;Affan Abbasi;Md Maksudul Hossain;Asif Faruque;H. Alan Mantooth;Zhong Chen
SiC-based n-channel and p-channel MOSFETs fabricated by Fraunhofer IISB SiC CMOS technology are characterized from room temperature up to 300°C. The behaviors of these low voltage devices including the short-channel effect (SCE), p-type ohmic contact with high resistivity, and the low channel mobility due to the SiC/SiO2 interface are presented. A thorough analysis is performed to understand the cause of low channel mobility, with TCAD simulations specifically on p-channel MOSFET, providing an insight into the impact of channel length, interface traps, and contact resistivity on device performance. The analysis in this paper is important in the comprehension of the low-voltage SiC MOSFETs so as to achieve balanced n-channel and p-channel MOSFETs and lead to the monolithic integration of SiC ICs with SiC power devices.
由Fraunhofer IISB SiC CMOS技术制造的基于SiC的n沟道和p沟道mosfet的特性从室温到300°C。这些低电压器件的行为包括短通道效应（SCE），高电阻率的p型欧姆接触，以及由于SiC/SiO2界面导致的低通道迁移率。通过对p沟道MOSFET进行TCAD模拟，对沟道长度、界面陷阱和接触电阻率对器件性能的影响进行了深入分析，以了解低沟道迁移率的原因。本文的分析对于理解低电压SiC mosfet具有重要意义，从而实现n沟道和p沟道mosfet的平衡，实现SiC集成电路与SiC功率器件的单片集成。
{"title":"Characterization of Silicon Carbide Low-Voltage n/p-Channel MOSFETs at High Temperatures","authors":"Hui Wang;Pengyu Lai;Affan Abbasi;Md Maksudul Hossain;Asif Faruque;H. Alan Mantooth;Zhong Chen","doi":"10.1109/JEDS.2024.3506922","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3506922","url":null,"abstract":"SiC-based n-channel and p-channel MOSFETs fabricated by Fraunhofer IISB SiC CMOS technology are characterized from room temperature up to 300°C. The behaviors of these low voltage devices including the short-channel effect (SCE), p-type ohmic contact with high resistivity, and the low channel mobility due to the SiC/SiO2 interface are presented. A thorough analysis is performed to understand the cause of low channel mobility, with TCAD simulations specifically on p-channel MOSFET, providing an insight into the impact of channel length, interface traps, and contact resistivity on device performance. The analysis in this paper is important in the comprehension of the low-voltage SiC MOSFETs so as to achieve balanced n-channel and p-channel MOSFETs and lead to the monolithic integration of SiC ICs with SiC power devices.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"24-33"},"PeriodicalIF":2.0,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10769415","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142976135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lowering the flux of sputtered particles using a molybdenum grid reduced the deposition rate of MoS2 films with an enlargement of the grain size measured by in-plane X-ray diffraction. The MoS2 film crystallinity evaluated by the Raman spectroscopy was improved because the S/Mo ratio was also enhanced by the low-rate sputtering. In addition, the enhancement of the grain size was confirmed from plan-view TEM observations of MoS2 films, consistent with the in-plane XRD results. Therefore, reducing the particle flux during sputtering is expected to contribute to the better-quality MoS2 films for pn-stacked 2D-CMOS devices and human interface devices.
{"title":"Improvement of MoS2 Film Quality by Low Flux of Sputtered Particles Using a Molybdenum Grid","authors":"Shinya Imai;Ryo Ono;Iriya Muneta;Kuniyuki Kakushima;Tetsuya Tatsumi;Shigetaka Tomiya;Kazuo Tsutsui;Hitoshi Wakabayashi","doi":"10.1109/JEDS.2024.3502922","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3502922","url":null,"abstract":"Lowering the flux of sputtered particles using a molybdenum grid reduced the deposition rate of MoS2 films with an enlargement of the grain size measured by in-plane X-ray diffraction. The MoS2 film crystallinity evaluated by the Raman spectroscopy was improved because the S/Mo ratio was also enhanced by the low-rate sputtering. In addition, the enhancement of the grain size was confirmed from plan-view TEM observations of MoS2 films, consistent with the in-plane XRD results. Therefore, reducing the particle flux during sputtering is expected to contribute to the better-quality MoS2 films for pn-stacked 2D-CMOS devices and human interface devices.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"15-23"},"PeriodicalIF":2.0,"publicationDate":"2024-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10758789","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-20DOI: 10.1109/JEDS.2024.3502738
Tae-Hyun Kil;Ju-Won Yeon;Hyo-Jun Park;Moon-Kwon Lee;Eui-Cheol Yun;Min-Woo Kim;Sang-Min Kang;Jun-Young Park
In this study, low-temperature deuterium annealing (LTDA) at 300 °C is proposed to enhance both the performance and reliability of silicon-based high-k metal gate (HKMG) MOSFETs. A comparative study with hydrogen (H2) annealing under identical conditions is conducted to evaluate the specific impact of deuterium (D2). Comprehensive DC characterizations and evaluations of stress immunity under hot-carrier injection (HCI) and positive bias stress (PBS) conditions, are performed. The results confirm that even at a low temperature of 300 °C, D2 has a more substantial effect on device performance and reliability compared to H2. This study provides a guideline for reducing the annealing temperature in the fabrication of HKMG MOSFETs.
{"title":"Low-Temperature Deuterium Annealing for HfO₂/SiO₂ Gate Dielectric in Silicon MOSFETs","authors":"Tae-Hyun Kil;Ju-Won Yeon;Hyo-Jun Park;Moon-Kwon Lee;Eui-Cheol Yun;Min-Woo Kim;Sang-Min Kang;Jun-Young Park","doi":"10.1109/JEDS.2024.3502738","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3502738","url":null,"abstract":"In this study, low-temperature deuterium annealing (LTDA) at 300 °C is proposed to enhance both the performance and reliability of silicon-based high-k metal gate (HKMG) MOSFETs. A comparative study with hydrogen (H2) annealing under identical conditions is conducted to evaluate the specific impact of deuterium (D2). Comprehensive DC characterizations and evaluations of stress immunity under hot-carrier injection (HCI) and positive bias stress (PBS) conditions, are performed. The results confirm that even at a low temperature of 300 °C, D2 has a more substantial effect on device performance and reliability compared to H2. This study provides a guideline for reducing the annealing temperature in the fabrication of HKMG MOSFETs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"1030-1033"},"PeriodicalIF":2.0,"publicationDate":"2024-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10758816","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142753873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-14DOI: 10.1109/JEDS.2024.3498008
Pei Shen;Yuan Jiang;Xiao-Dong Zhang;Ji-Yang Dai
The application of silicon carbide (SiC) MOSFETs in the field of high voltage and high frequency brings the major challenge of high switching loss. To give full advantage of its performance in high-frequency applications and provide a simulation analysis method for the analysis and design of power electronic systems, it is essential to establish simulation models of the SiC power MOSFET switching behavior suitable for different ambient temperatures. A temperature-dependent compact SPICE model considering parasitic parameters is proposed in this article, which uses only the parameters in the datasheet or provided by manufacturers. The main technology-dependent parameters are analyzed and discussed in detail, including the nonlinear parasitic capacitance, parasitic parameters of the power module, and static characteristic parameters. In static characteristics, a simple and continuous equation is used to describe the drain-source current of the SiC power MOSFET. The static characteristic parameters of the SPICE model were compared with the 1.2-kV SiC power MOSFET, manufactured by ROHM, Inc., (SCT3030KLHR). Subsequently, the dynamic characteristic is verified by comparing the simulation results with experimental results in a double pulse circuit employing the half-bridge module under different temperatures. Comparisons between the datasheet and experiments demonstrate the precision of the modeling methodology and the consistency of the results.
碳化硅 (SiC) MOSFET 在高电压和高频率领域的应用带来了高开关损耗的重大挑战。为了充分发挥 SiC 功率 MOSFET 在高频应用中的性能优势，并为电力电子系统的分析和设计提供仿真分析方法，必须建立适合不同环境温度的 SiC 功率 MOSFET 开关行为仿真模型。本文提出了一种考虑寄生参数的与温度相关的紧凑型 SPICE 模型，该模型仅使用数据手册中的参数或制造商提供的参数。文中详细分析和讨论了与技术相关的主要参数，包括非线性寄生电容、功率模块的寄生参数和静态特性参数。在静态特性方面，使用了一个简单的连续方程来描述 SiC 功率 MOSFET 的漏极-源极电流。SPICE 模型的静态特性参数与 ROHM 公司生产的 1.2 kV SiC 功率 MOSFET（SCT3030KLHR）进行了比较。随后，通过比较仿真结果和采用半桥模块的双脉冲电路在不同温度下的实验结果，验证了动态特性。数据表与实验结果的比较证明了建模方法的精确性和结果的一致性。
{"title":"A Temperature-Dependent SPICE Model of SiC Power Trench MOSFET Switching Behavior Considering Parasitic Parameters","authors":"Pei Shen;Yuan Jiang;Xiao-Dong Zhang;Ji-Yang Dai","doi":"10.1109/JEDS.2024.3498008","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3498008","url":null,"abstract":"The application of silicon carbide (SiC) MOSFETs in the field of high voltage and high frequency brings the major challenge of high switching loss. To give full advantage of its performance in high-frequency applications and provide a simulation analysis method for the analysis and design of power electronic systems, it is essential to establish simulation models of the SiC power MOSFET switching behavior suitable for different ambient temperatures. A temperature-dependent compact SPICE model considering parasitic parameters is proposed in this article, which uses only the parameters in the datasheet or provided by manufacturers. The main technology-dependent parameters are analyzed and discussed in detail, including the nonlinear parasitic capacitance, parasitic parameters of the power module, and static characteristic parameters. In static characteristics, a simple and continuous equation is used to describe the drain-source current of the SiC power MOSFET. The static characteristic parameters of the SPICE model were compared with the 1.2-kV SiC power MOSFET, manufactured by ROHM, Inc., (SCT3030KLHR). Subsequently, the dynamic characteristic is verified by comparing the simulation results with experimental results in a double pulse circuit employing the half-bridge module under different temperatures. Comparisons between the datasheet and experiments demonstrate the precision of the modeling methodology and the consistency of the results.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"98-105"},"PeriodicalIF":2.0,"publicationDate":"2024-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10753303","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143446252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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