Pub Date : 2025-12-15DOI: 10.1109/JEDS.2025.3644310
Wallace Lin;Darsen D. Lu
A method directly solving Fowler-Nordheim tunneling current equations for extracting the effective tunneling area, the barrier heights of the top and bottom electrodes and the electron tunneling effective mass in metal-insulator-metal diodes is demonstrated. Extracted result from the method is comparable with that obtained from the automated Cowell method. The property of the Pt-Al2O3-TiN and Ni-Al2O3-TiN diodes are extracted and analyzed. The effective tunneling area appears to be four to five orders smaller than the drawn device area, suggesting tunneling current flows in very narrow conduction channel(s).
{"title":"Direct Extraction of Fowler–Nordheim Tunneling Parameters of Asymmetric Metal-Insulator-Metal Diodes Based on Current-Voltage Measurement","authors":"Wallace Lin;Darsen D. Lu","doi":"10.1109/JEDS.2025.3644310","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3644310","url":null,"abstract":"A method directly solving Fowler-Nordheim tunneling current equations for extracting the effective tunneling area, the barrier heights of the top and bottom electrodes and the electron tunneling effective mass in metal-insulator-metal diodes is demonstrated. Extracted result from the method is comparable with that obtained from the automated Cowell method. The property of the Pt-Al2O3-TiN and Ni-Al2O3-TiN diodes are extracted and analyzed. The effective tunneling area appears to be four to five orders smaller than the drawn device area, suggesting tunneling current flows in very narrow conduction channel(s).","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"18-23"},"PeriodicalIF":2.4,"publicationDate":"2025-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11299545","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-11DOI: 10.1109/JEDS.2025.3642939
Theo Cabaret;Eva Dos Reis;Valerie Lapras;Nicolas Gauthier;Joel Kanyandekwe
Improvement of source/drain regions is necessary to meet the requirements of advanced Fully Depleted Silicon On Insulator (FD-SOI) nodes. The implementation and control of in-situ doped epitaxy while optimizing the dopant diffusion close to the channel is crucial for these architectures. However, few studies have been performed concerning the impact of Rapid Thermal Annealing (RTA) on in-situ doped epitaxial layers for junction optimization. Tensile-strained Si:P (t-Si:P) selective epitaxial growth is being developed for nMOS devices. We evaluate here the impact of temperature and annealing duration on electrical resistivity and diffusion length of P in such t-Si:P layers. We show that the diffusion length can be tuned by selecting the right thermal budget. The diffusion coefficient is otherwise reduced in our in-situ doped samples compared to that in ion implanted ones. Despite a slight tensile strain decrease, maybe due to SixPy cluster dissolution, the t–Si:P resistivity decreased after thermal annealing compared to that just after epitaxy. A right balance between tensile strain preservation and dopant activation was found. We finally evidenced that the active carrier concentration after RTA was in line with the dopant solubility at a given temperature. Higher temperature and shorter anneals might give access to even lower resistivities. The proposed annealing strategy paves the way for the integration of highly doped t-Si:P layers (> $10^{21}$ at/cm3) in the source/drain regions of nMOSFET device.
{"title":"Diffusion Analysis and Impact of RTA on Strained Phosphorous-Doped Si for Advanced SOI Nodes","authors":"Theo Cabaret;Eva Dos Reis;Valerie Lapras;Nicolas Gauthier;Joel Kanyandekwe","doi":"10.1109/JEDS.2025.3642939","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3642939","url":null,"abstract":"Improvement of source/drain regions is necessary to meet the requirements of advanced Fully Depleted Silicon On Insulator (FD-SOI) nodes. The implementation and control of in-situ doped epitaxy while optimizing the dopant diffusion close to the channel is crucial for these architectures. However, few studies have been performed concerning the impact of Rapid Thermal Annealing (RTA) on in-situ doped epitaxial layers for junction optimization. Tensile-strained Si:P (t-Si:P) selective epitaxial growth is being developed for nMOS devices. We evaluate here the impact of temperature and annealing duration on electrical resistivity and diffusion length of P in such t-Si:P layers. We show that the diffusion length can be tuned by selecting the right thermal budget. The diffusion coefficient is otherwise reduced in our in-situ doped samples compared to that in ion implanted ones. Despite a slight tensile strain decrease, maybe due to SixPy cluster dissolution, the t–Si:P resistivity decreased after thermal annealing compared to that just after epitaxy. A right balance between tensile strain preservation and dopant activation was found. We finally evidenced that the active carrier concentration after RTA was in line with the dopant solubility at a given temperature. Higher temperature and shorter anneals might give access to even lower resistivities. The proposed annealing strategy paves the way for the integration of highly doped t-Si:P layers (> <inline-formula> <tex-math>$10^{21}$ </tex-math></inline-formula> at/cm3) in the source/drain regions of nMOSFET device.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1306-1312"},"PeriodicalIF":2.4,"publicationDate":"2025-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11297741","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145886560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work investigates the reliability of AlScN/GaN High-Electron-Mobility Transistors (HEMTs) by integrating experimental analyzes with Technology Computer-Aided Design (TCAD) simulations. The study focuses on pulsed I-V measurements and High-Temperature Reverse Bias (HTRB) step-stress tests. The former have been performed under different quiescent conditions highlight short-term transient charge trapping, while the latter reveals long-term threshold voltage $(V_{mathrm {th}})$ , transconductance $(mathrm {gm})$ , saturation drain current $(I_{mathrm {D,ss}})$ and gate leakage $(I_{mathrm {G}})$ shifts. A TCAD model calibrated on experiments is employed to deeply understand the interplay of the different sources of degradation. In pulsed analyzes, iron traps are identified as the primary degradation contributors. In HTRB step-stress regime, trapped charges under the gate at the 2DEG interface are modeled to reproduce the $V_{mathrm {th}}$ shift, while the decreased gm is mostly ascribed to donor-trap detrapping at the SiN passivation interface. The relative $Delta I_{mathrm {D,ss}}[%]$ shift and $I_{mathrm {G}}$ are used to validate the proposed approach. Such insights also provide a net comparison of the degradation phenomena in AlScN-based HEMTs with respect to AlGaN-based counterparts, paving the way for improved technology and device designs.
{"title":"Reliability of AlScN/GaN HEMTs Under Pulsed Measurements and HTRB Step-Stress Tests: Experimental and TCAD Insights","authors":"Franco Ercolano;Luigi Balestra;Sebastian Krause;Stefano Leone;Isabel Streicher;Patrick Waltereit;Michael Dammann;Susanna Reggiani","doi":"10.1109/JEDS.2025.3641046","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3641046","url":null,"abstract":"This work investigates the reliability of AlScN/GaN High-Electron-Mobility Transistors (HEMTs) by integrating experimental analyzes with Technology Computer-Aided Design (TCAD) simulations. The study focuses on pulsed I-V measurements and High-Temperature Reverse Bias (HTRB) step-stress tests. The former have been performed under different quiescent conditions highlight short-term transient charge trapping, while the latter reveals long-term threshold voltage <inline-formula> <tex-math>$(V_{mathrm {th}})$ </tex-math></inline-formula>, transconductance <inline-formula> <tex-math>$(mathrm {gm})$ </tex-math></inline-formula>, saturation drain current <inline-formula> <tex-math>$(I_{mathrm {D,ss}})$ </tex-math></inline-formula> and gate leakage <inline-formula> <tex-math>$(I_{mathrm {G}})$ </tex-math></inline-formula> shifts. A TCAD model calibrated on experiments is employed to deeply understand the interplay of the different sources of degradation. In pulsed analyzes, iron traps are identified as the primary degradation contributors. In HTRB step-stress regime, trapped charges under the gate at the 2DEG interface are modeled to reproduce the <inline-formula> <tex-math>$V_{mathrm {th}}$ </tex-math></inline-formula> shift, while the decreased gm is mostly ascribed to donor-trap detrapping at the SiN passivation interface. The relative <inline-formula> <tex-math>$Delta I_{mathrm {D,ss}}[%]$ </tex-math></inline-formula> shift and <inline-formula> <tex-math>$I_{mathrm {G}}$ </tex-math></inline-formula> are used to validate the proposed approach. Such insights also provide a net comparison of the degradation phenomena in AlScN-based HEMTs with respect to AlGaN-based counterparts, paving the way for improved technology and device designs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"1-9"},"PeriodicalIF":2.4,"publicationDate":"2025-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11282436","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01DOI: 10.1109/JEDS.2025.3638982
Pengyu Lai;Hui Wang;H. Alan Mantooth;Zhong Chen
This paper proposes and experimentally evaluates SiC laterally diffused metal-oxide-semiconductor (LDMOS) devices fabricated on two full 4H-SiC processes with P-type and N-type epitaxial layers. The devices were characterized from 25 °C to 300 °C in terms of turn-on resistance $(R_{on})$ , breakdown voltage (BV), input capacitance $(C_{iss})$ , and output capacitance $(C_{oss})$ . At 25 °C, $R_{on}$ ranges from 5 $Omega $ /mm2 to 10 $Omega $ /mm2 and BV spans 160 V to 315 V with the device parameter variations. The figure of merit (FOM, i.e., ~14 kW/mm2) is comparable to Si-based LDMOS at room temperature and remains stable up to 300 °C, whereas Si devices degrade rapidly above 150 °C. $C_{iss}$ and $C_{oss}$ of the SiC LDMOS are higher than those of their Si counterparts but exhibit little degradation with increasing temperature. These results demonstrate that the proposed SiC LDMOS devices provide promising performance and strong thermal stability, highlighting their potential for high-voltage and high-temperature integrated circuit applications.
{"title":"Development and Evaluation of SiC LDMOS for High-Temperature Applications","authors":"Pengyu Lai;Hui Wang;H. Alan Mantooth;Zhong Chen","doi":"10.1109/JEDS.2025.3638982","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3638982","url":null,"abstract":"This paper proposes and experimentally evaluates SiC laterally diffused metal-oxide-semiconductor (LDMOS) devices fabricated on two full 4H-SiC processes with P-type and N-type epitaxial layers. The devices were characterized from 25 °C to 300 °C in terms of turn-on resistance <inline-formula> <tex-math>$(R_{on})$ </tex-math></inline-formula>, breakdown voltage (BV), input capacitance <inline-formula> <tex-math>$(C_{iss})$ </tex-math></inline-formula>, and output capacitance <inline-formula> <tex-math>$(C_{oss})$ </tex-math></inline-formula>. At 25 °C, <inline-formula> <tex-math>$R_{on}$ </tex-math></inline-formula> ranges from 5 <inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>/mm2 to 10 <inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>/mm2 and BV spans 160 V to 315 V with the device parameter variations. The figure of merit (FOM, i.e., ~14 kW/mm2) is comparable to Si-based LDMOS at room temperature and remains stable up to 300 °C, whereas Si devices degrade rapidly above 150 °C. <inline-formula> <tex-math>$C_{iss}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$C_{oss}$ </tex-math></inline-formula> of the SiC LDMOS are higher than those of their Si counterparts but exhibit little degradation with increasing temperature. These results demonstrate that the proposed SiC LDMOS devices provide promising performance and strong thermal stability, highlighting their potential for high-voltage and high-temperature integrated circuit applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"10-17"},"PeriodicalIF":2.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11271727","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-25DOI: 10.1109/JEDS.2025.3636591
Lucas Badeau;Nicolas Coudurier;Patrice Gergaud;Jean-Michel Hartmann;Vincent Reboud;Philippe Rodriguez
We have investigated Co / GeSn contacts as a promising alternative to the conventional Ni / GeSn system. While cobalt has been widely studied for silicide and germanide formation, its interaction with GeSn has not been probed yet. Using X-ray diffraction (XRD), we obtained the following phase formation sequence: cobalt was consumed at low temperatures to form CoGe near 300 °C, followed by the appearance of Co5Ge7 between 400-500 °C, and its transformation into stable CoGe2 at higher temperatures. Transient CoSnx compounds were also identified in the 350-500 °C range, likely linked to tin segregation above 350 °C. The electrical behavior of Co / n-doped Ge0.94Sn0.06 contacts was also characterized with an ohmic behavior from the as-deposited state up to 500 °C. Notably, low specific contact resistivity values were achieved, with $rho {}_{text {c}}$ as low as $8.8times 10^{-6}~Omega {}$ .cm2. Cobalt was thus shown to be a viable metallization candidate for n-doped GeSn films.
{"title":"Interfacial Reactions and Electrical Properties of Co / GeSn Contacts","authors":"Lucas Badeau;Nicolas Coudurier;Patrice Gergaud;Jean-Michel Hartmann;Vincent Reboud;Philippe Rodriguez","doi":"10.1109/JEDS.2025.3636591","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3636591","url":null,"abstract":"We have investigated Co / GeSn contacts as a promising alternative to the conventional Ni / GeSn system. While cobalt has been widely studied for silicide and germanide formation, its interaction with GeSn has not been probed yet. Using X-ray diffraction (XRD), we obtained the following phase formation sequence: cobalt was consumed at low temperatures to form CoGe near 300 °C, followed by the appearance of Co5Ge7 between 400-500 °C, and its transformation into stable CoGe2 at higher temperatures. Transient CoSnx compounds were also identified in the 350-500 °C range, likely linked to tin segregation above 350 °C. The electrical behavior of Co / n-doped Ge0.94Sn0.06 contacts was also characterized with an ohmic behavior from the as-deposited state up to 500 °C. Notably, low specific contact resistivity values were achieved, with <inline-formula> <tex-math>$rho {}_{text {c}}$ </tex-math></inline-formula> as low as <inline-formula> <tex-math>$8.8times 10^{-6}~Omega {}$ </tex-math></inline-formula>.cm2. Cobalt was thus shown to be a viable metallization candidate for n-doped GeSn films.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1299-1305"},"PeriodicalIF":2.4,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11267448","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-14DOI: 10.1109/JEDS.2025.3632845
Jun-Hyeok Yim;Jinhyeok Pyo;Myeongsu Chae;Sangyeon Pak;Hyungtak Kim;Ho-Young Cha
This study reports the fabrication and characterization of a p-GaN/AlGaN/GaN heterostructure field-effect transistor (HFET) incorporating a boron nitride (BN) film. The BN film was deposited at room temperature via RF sputtering (RT-RF sputtering) onto a SiOx passivation layer. A dual-layer passivation scheme—comprising the SiOx layer and the room-temperature-deposited BN film—was proposed to enhance interface quality and improve the on-resistance characteristics. The RT-RF sputtering BN film was found to increase the 2DEG density at the AlGaN/GaN interface without degrading the overall device performance. As a result, the on-resistance was reduced by 30%.
{"title":"Improved On-Resistance Characteristics in P-GaN/AlGaN/GaN HEMTs via Sputtered Boron Nitride Dielectric Film","authors":"Jun-Hyeok Yim;Jinhyeok Pyo;Myeongsu Chae;Sangyeon Pak;Hyungtak Kim;Ho-Young Cha","doi":"10.1109/JEDS.2025.3632845","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3632845","url":null,"abstract":"This study reports the fabrication and characterization of a p-GaN/AlGaN/GaN heterostructure field-effect transistor (HFET) incorporating a boron nitride (BN) film. The BN film was deposited at room temperature via RF sputtering (RT-RF sputtering) onto a SiOx passivation layer. A dual-layer passivation scheme—comprising the SiOx layer and the room-temperature-deposited BN film—was proposed to enhance interface quality and improve the on-resistance characteristics. The RT-RF sputtering BN film was found to increase the 2DEG density at the AlGaN/GaN interface without degrading the overall device performance. As a result, the on-resistance was reduced by 30%.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1138-1143"},"PeriodicalIF":2.4,"publicationDate":"2025-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11248840","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145560725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Random telegraph noise (RTN) in 65 nm technology bulk CMOS devices was measured at both 300 K and 1.5 K, and the dependence of noise amplitude on gate voltage was analyzed. Considering the highly random nature of RTN, 1,024 devices of both nMOS and pMOS types were measured using addressable transistor arrays to obtain statistically meaningful results. It was confirmed that the single-trap RTN amplitude is in good agreement with the number-plus-correlated-mobility fluctuation model at both 1.5 K and 300 K for both device types. It is shown that, from the extracted model parameters, it is possible to gain information on trap location and single charge scattering behavior. The effects of series resistance on the model are also discussed.
{"title":"Gate Voltage Dependence of MOSFET Random Telegraph Noise Amplitude at Room and Cryogenic Temperatures","authors":"Kiyoshi Takeuchi;Tomoko Mizutani;Takuya Saraya;Hiroshi Oka;Takahiro Mori;Masaharu Kobayashi;Toshiro Hiramoto","doi":"10.1109/JEDS.2025.3632306","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3632306","url":null,"abstract":"Random telegraph noise (RTN) in 65 nm technology bulk CMOS devices was measured at both 300 K and 1.5 K, and the dependence of noise amplitude on gate voltage was analyzed. Considering the highly random nature of RTN, 1,024 devices of both nMOS and pMOS types were measured using addressable transistor arrays to obtain statistically meaningful results. It was confirmed that the single-trap RTN amplitude is in good agreement with the number-plus-correlated-mobility fluctuation model at both 1.5 K and 300 K for both device types. It is shown that, from the extracted model parameters, it is possible to gain information on trap location and single charge scattering behavior. The effects of series resistance on the model are also discussed.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1151-1157"},"PeriodicalIF":2.4,"publicationDate":"2025-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11245544","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145560724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We have developed a novel molecular-ion implantation technique and a molecular-ion-implanted silicon epitaxial wafer for highly sensitive CMOS image sensors. This implantation technique is characterized by the use of molecular-ions consisting of carbon, hydrogen, and fluorine. In this paper, we investigate the formation of CH2F+ molecular-ion beams and conduct a fundamental study on the implantation behavior of CH2F+ molecular-ions and the characteristics of CH2F+-implanted silicon epitaxial wafers. We expect that this technique can contribute to the mass production of highly sensitive CMOS image sensors.
{"title":"Novel Production Concept of CH2F-Molecular-Ion Implanted Si Epitaxial Wafer for Highly Sensitive 3-D-Stacked CMOS Image Sensors","authors":"Ryo Hirose;Koji Kobayashi;Kazunari Kurita;Takeshi Kadono;Sho Nagatomo","doi":"10.1109/JEDS.2025.3631002","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3631002","url":null,"abstract":"We have developed a novel molecular-ion implantation technique and a molecular-ion-implanted silicon epitaxial wafer for highly sensitive CMOS image sensors. This implantation technique is characterized by the use of molecular-ions consisting of carbon, hydrogen, and fluorine. In this paper, we investigate the formation of CH2F+ molecular-ion beams and conduct a fundamental study on the implantation behavior of CH2F+ molecular-ions and the characteristics of CH2F+-implanted silicon epitaxial wafers. We expect that this technique can contribute to the mass production of highly sensitive CMOS image sensors.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1276-1281"},"PeriodicalIF":2.4,"publicationDate":"2025-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11236452","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A “memriscapacitor” consisting of a memristor and capacitor has been proposed and actually fabricated. The advantages are the wide dynamic ranges and low power consumption achieved simultaneously. First, the device structure is quite simple, namely, an amorphous Ga-Sn-O thin film between electrodes acts as a memristor, whereas a SiO2 film acts as a capacitor. Next, the hysteresis characteristic of the memristor is observed. Finally, it is validated that the multiply-accumulate calculation is realized as desired by the memriscapacitor.
{"title":"Memriscapacitor Consisting of a Memristor and Capacitor — The First Proposal and Fabrication With Validation of Multiply-Accumulate Calculation","authors":"Kenta Yachida;Kazuki Sawai;Tokiyoshi Matsuda;Hidenori Kawanishi;Mutsumi Kimura","doi":"10.1109/JEDS.2025.3630670","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3630670","url":null,"abstract":"A “memriscapacitor” consisting of a memristor and capacitor has been proposed and actually fabricated. The advantages are the wide dynamic ranges and low power consumption achieved simultaneously. First, the device structure is quite simple, namely, an amorphous Ga-Sn-O thin film between electrodes acts as a memristor, whereas a SiO2 film acts as a capacitor. Next, the hysteresis characteristic of the memristor is observed. Finally, it is validated that the multiply-accumulate calculation is realized as desired by the memriscapacitor.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1120-1124"},"PeriodicalIF":2.4,"publicationDate":"2025-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11236444","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-10DOI: 10.1109/JEDS.2025.3631061
Yu-Che Tsai;Jenn-Gwo Hwu
A compact logic-configurable device based on a concentric structure with a non-planar oxide structure is demonstrated. The implementation of a non-planar oxide structure minimizes leakage current paths, leading to a reduction in total current. The device maintains stable and different current levels over 100 repeated switching cycles for center biased at + 1 V and rings between flat-band voltage ($approx $ –0.9 V) and 0 V, demonstrating excellent reliability and suitability for multi-state computing in AI applications. When the center was biased at a selected negative bias, the output current polarity at the center electrode is determined by the interplay between tunneling and coupling effects. By adjusting the center bias, multiple logic functions of OR, MAJ, and AND can be realized within a single device by detecting current polarity. The proposed structure exhibits stable operation over 1000 cycles. Notably, the use of a non-planar oxide leads to a dramatic reduction in power consumption, reaching nearly two orders of magnitude improvement with respect to planar oxide structure. TCAD simulations confirm its scalability down to the nanoscale, underscoring its potential for energy-efficient compute-in-memory applications.
{"title":"Low Power Logic Functions in Non-Planar Oxide Metal–Insulator–Semiconductor Tunnel Diodes via Tunneling–Coupling Current Competition","authors":"Yu-Che Tsai;Jenn-Gwo Hwu","doi":"10.1109/JEDS.2025.3631061","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3631061","url":null,"abstract":"A compact logic-configurable device based on a concentric structure with a non-planar oxide structure is demonstrated. The implementation of a non-planar oxide structure minimizes leakage current paths, leading to a reduction in total current. The device maintains stable and different current levels over 100 repeated switching cycles for center biased at + 1 V and rings between flat-band voltage (<inline-formula> <tex-math>$approx $ </tex-math></inline-formula> –0.9 V) and 0 V, demonstrating excellent reliability and suitability for multi-state computing in AI applications. When the center was biased at a selected negative bias, the output current polarity at the center electrode is determined by the interplay between tunneling and coupling effects. By adjusting the center bias, multiple logic functions of OR, MAJ, and AND can be realized within a single device by detecting current polarity. The proposed structure exhibits stable operation over 1000 cycles. Notably, the use of a non-planar oxide leads to a dramatic reduction in power consumption, reaching nearly two orders of magnitude improvement with respect to planar oxide structure. TCAD simulations confirm its scalability down to the nanoscale, underscoring its potential for energy-efficient compute-in-memory applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1144-1150"},"PeriodicalIF":2.4,"publicationDate":"2025-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11237060","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145560723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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