Pub Date : 2024-09-13DOI: 10.1109/JEDS.2024.3459872
Ji Hwan Lee;Kihwan Kim;Kyungjin Rim;Soogine Chong;Hyunbo Cho;Saeroonter Oh
Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology computer-aided design (TCAD) device simulation data of GAA field-effect transistors (FETs) subjected to both tensile and compressive strain in nMOS and pMOS devices. Strain was induced into the channel via lattice mismatch between the channel and source/drain epitaxial regions, as simulated by 3D TCAD process simulator. The transport models were calibrated against advanced Monte Carlo simulations to ensure accuracy. The resulting neural compact model demonstrated a close approximation to the original simulation results, achieving a minimal error of 1%. To assess the strain effect on circuit-level performance, SPICE simulations were conducted for a 5-stage ring oscillator and a 2-input NAND gate using the neural compact model. The propagation delay of the 5-stage ring oscillator improved from 3.60 ps to 2.85 ps when implementing strained GAA FETs. Also, strain enhanced the power-delay product of the 2-input NAND gate by 13.8% to 15.5%, depending on the input voltage sequence.
{"title":"Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach","authors":"Ji Hwan Lee;Kihwan Kim;Kyungjin Rim;Soogine Chong;Hyunbo Cho;Saeroonter Oh","doi":"10.1109/JEDS.2024.3459872","DOIUrl":"10.1109/JEDS.2024.3459872","url":null,"abstract":"Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology computer-aided design (TCAD) device simulation data of GAA field-effect transistors (FETs) subjected to both tensile and compressive strain in nMOS and pMOS devices. Strain was induced into the channel via lattice mismatch between the channel and source/drain epitaxial regions, as simulated by 3D TCAD process simulator. The transport models were calibrated against advanced Monte Carlo simulations to ensure accuracy. The resulting neural compact model demonstrated a close approximation to the original simulation results, achieving a minimal error of 1%. To assess the strain effect on circuit-level performance, SPICE simulations were conducted for a 5-stage ring oscillator and a 2-input NAND gate using the neural compact model. The propagation delay of the 5-stage ring oscillator improved from 3.60 ps to 2.85 ps when implementing strained GAA FETs. Also, strain enhanced the power-delay product of the 2-input NAND gate by 13.8% to 15.5%, depending on the input voltage sequence.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10680295","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142253411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Computing-In-Memory (CIM) is widely applied in neural networks due to its unique capability to perform multiply-and-accumulate operations within a circuit array. This process directly obtains the current value through the product of voltage and conductance, accumulating it on the bit line, thus realizing storage and computing functionalities simultaneously within a single array. This significantly reduces the power consumption and time delay in data processing. Unfortunately, implementing general-purpose logic computations in large-scale memory arrays with CIM remains a challenge. This paper introduced a novel device concept, the programmable diode—a special type of memristor with a high switching window, ideally suited for memory arrays to reduce power consumption. A compact SPICE model was developed to enable circuit-level simulations in EDA tools. We also proposed a method to efficiently control the programmable diode for logic operations in memory arrays, and in this way, we constructed a parallel 8-bit full adder to verify the feasibility of the proposed method. Finally, based on the 8-bit full adder, we built a 5KB in-memory logic array capable of executing logic computations and simulated it using EDA tools. The simulation results demonstrated that the 5KB in-memory logic array can perform fundamental Boolean logic and arithmetic operations with high repeatability and parallelism, perfectly realizing the functionality of in-memory logic computation. Our work can provide a feasible scheme for realizing large-scale general logic computation systems based on CIM.
{"title":"A Novel Parallel In-Memory Logic Array Based on Programmable Diodes","authors":"Jiabao Ye;Junyu Zhu;Jifang Cao;Haoxiong Bi;Yong Ding;Bing Chen","doi":"10.1109/JEDS.2024.3457021","DOIUrl":"10.1109/JEDS.2024.3457021","url":null,"abstract":"Computing-In-Memory (CIM) is widely applied in neural networks due to its unique capability to perform multiply-and-accumulate operations within a circuit array. This process directly obtains the current value through the product of voltage and conductance, accumulating it on the bit line, thus realizing storage and computing functionalities simultaneously within a single array. This significantly reduces the power consumption and time delay in data processing. Unfortunately, implementing general-purpose logic computations in large-scale memory arrays with CIM remains a challenge. This paper introduced a novel device concept, the programmable diode—a special type of memristor with a high switching window, ideally suited for memory arrays to reduce power consumption. A compact SPICE model was developed to enable circuit-level simulations in EDA tools. We also proposed a method to efficiently control the programmable diode for logic operations in memory arrays, and in this way, we constructed a parallel 8-bit full adder to verify the feasibility of the proposed method. Finally, based on the 8-bit full adder, we built a 5KB in-memory logic array capable of executing logic computations and simulated it using EDA tools. The simulation results demonstrated that the 5KB in-memory logic array can perform fundamental Boolean logic and arithmetic operations with high repeatability and parallelism, perfectly realizing the functionality of in-memory logic computation. Our work can provide a feasible scheme for realizing large-scale general logic computation systems based on CIM.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10674001","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142198876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-06DOI: 10.1109/JEDS.2024.3455256
Boseong Son;Huijin Kim;Young-Woong Lee;Purusottam Reddy Bommireddy;Si-Hyun Park
We developed a monolithically integrated device consisting of a single GaN LED and two p-GaN-depletion MOSFETs on a GaN LED epitaxial layer. The p-GaN-depletion MOSFETs exhibited a subthreshold slope of 1 V/decade and a threshold voltage of –2 V, whereas the LED exhibited a forward voltage of 3.5 V at 1 mA and an electroluminescence peak of 445 nm. The device could be controlled by the scan voltage, with $V_{DD}$ ranging from 1 to 2 V, and cut off the total current with an applied scan voltage greater than 3 V. This work represents an important step towards the monolithic integration of LED and transistors for use in active-matrix micro-LED displays.
我们开发了一种单片集成器件，包括一个氮化镓发光二极管和两个位于氮化镓发光二极管外延层上的p-氮化镓损耗MOSFET。对氮化镓损耗 MOSFET 的阈下斜率为 1 V/decade，阈值电压为 -2 V，而 LED 在 1 mA 电流下的正向电压为 3.5 V，电致发光峰值为 445 nm。该器件可由扫描电压控制，$V_{DD}$范围为 1 至 2 V，并可在扫描电压大于 3 V 时切断总电流。
{"title":"Wafer-Scale Monolithic Integration of LEDs with p-GaN-Depletion MOSFETs on a GaN LED Epitaxial Layer","authors":"Boseong Son;Huijin Kim;Young-Woong Lee;Purusottam Reddy Bommireddy;Si-Hyun Park","doi":"10.1109/JEDS.2024.3455256","DOIUrl":"10.1109/JEDS.2024.3455256","url":null,"abstract":"We developed a monolithically integrated device consisting of a single GaN LED and two p-GaN-depletion MOSFETs on a GaN LED epitaxial layer. The p-GaN-depletion MOSFETs exhibited a subthreshold slope of 1 V/decade and a threshold voltage of –2 V, whereas the LED exhibited a forward voltage of 3.5 V at 1 mA and an electroluminescence peak of 445 nm. The device could be controlled by the scan voltage, with \u0000<inline-formula> <tex-math>$V_{DD}$ </tex-math></inline-formula>\u0000 ranging from 1 to 2 V, and cut off the total current with an applied scan voltage greater than 3 V. This work represents an important step towards the monolithic integration of LED and transistors for use in active-matrix micro-LED displays.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10668404","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-04DOI: 10.1109/JEDS.2024.3454334
Manuel Fregolent;Mirco Boito;Michele Disarò;Carlo De Santi;Matteo Buffolo;Eleonora Canato;Michele Gallo;Cristina Miccoli;Isabella Rossetto;Giansalvo Pizzo;Alfio Russo;Ferdinando Iucolano;Gaudenzio Meneghesso;Enrico Zanoni;Matteo Meneghini
For the first time, we use electrical characterization, spectrally-resolved electroluminescence measurements and degradation tests to explain the negative activation energy of gate reliability in power GaN HEMTs with p-GaN Schottky gate. First, the origin of gate leakage current was modeled. The results indicate that the gate leakage current originates from three different mechanisms: (i) thermionic emission of electrons from the uid-GaN layer across the AlGaN barrier, for gate voltages below threshold $(V_{G} lt V_{TH})$ , (ii) thermionic emission of electrons from the channel to the p-GaN layer $(V_{TH} lt V_{G} lt 4.5 V)$ and (iii) trap-assisted-tunneling of holes at the Schottky metal for higher gate voltages. Then, the analysis of the reliability as function of gate bias demonstrated a negative activation energy (longer lifetime at high temperature). By analyzing the electroluminescence spectra under high positive bias, the improved time to failure at high temperatures was ascribed to the increased hole injection and recombination, that reduces the overall number of electrons that undergo avalanche multiplication, leading to the breakdown. Finally, the model was validated by comparing the electrical properties and conduction model of the devices pre- and post-stress.
{"title":"Negative Activation Energy of Gate Reliability in Schottky-Gate p-GaN HEMTs: Combined Gate Leakage Current Modeling and Spectral Electroluminescence Investigation","authors":"Manuel Fregolent;Mirco Boito;Michele Disarò;Carlo De Santi;Matteo Buffolo;Eleonora Canato;Michele Gallo;Cristina Miccoli;Isabella Rossetto;Giansalvo Pizzo;Alfio Russo;Ferdinando Iucolano;Gaudenzio Meneghesso;Enrico Zanoni;Matteo Meneghini","doi":"10.1109/JEDS.2024.3454334","DOIUrl":"10.1109/JEDS.2024.3454334","url":null,"abstract":"For the first time, we use electrical characterization, spectrally-resolved electroluminescence measurements and degradation tests to explain the negative activation energy of gate reliability in power GaN HEMTs with p-GaN Schottky gate. First, the origin of gate leakage current was modeled. The results indicate that the gate leakage current originates from three different mechanisms: (i) thermionic emission of electrons from the uid-GaN layer across the AlGaN barrier, for gate voltages below threshold \u0000<inline-formula> <tex-math>$(V_{G} lt V_{TH})$ </tex-math></inline-formula>\u0000, (ii) thermionic emission of electrons from the channel to the p-GaN layer \u0000<inline-formula> <tex-math>$(V_{TH} lt V_{G} lt 4.5 V)$ </tex-math></inline-formula>\u0000 and (iii) trap-assisted-tunneling of holes at the Schottky metal for higher gate voltages. Then, the analysis of the reliability as function of gate bias demonstrated a negative activation energy (longer lifetime at high temperature). By analyzing the electroluminescence spectra under high positive bias, the improved time to failure at high temperatures was ascribed to the increased hole injection and recombination, that reduces the overall number of electrons that undergo avalanche multiplication, leading to the breakdown. Finally, the model was validated by comparing the electrical properties and conduction model of the devices pre- and post-stress.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10664574","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a new pixel circuit for active matrix organic light-emitting diode (AMOLED) display that can achieve high uniformity in low gray levels and its driving method are proposed. The proposed circuit compensates for threshold voltage variation of thin-film-transistors (TFTs), with the structure that minimizes the loss of sensed threshold voltage. However, the high current error rate in extremely low gray level is unavoidable, as the driving TFT (DRT) operates in subthreshold region, where the current difference caused by the threshold voltage variation can be severe. To suppress high error rates in low gray levels, the operation region of DRT is restricted to the saturation region, by adopting duty ratio modulation (DRM) method. With the DRM method, low gray is expressed with high current value and short emission time. The viability of the proposed circuit and its operation are analyzed with HSPICE. Compared to the conventional driving method, DRM significantly reduces the current error rate in low gray area. The proposed circuit is fabricated within 220 $mu {mathrm {m}} times 440 mu {mathrm {m}}$ . The measurement of the circuit also verified the capability of the proposed circuit and the DRM method.
{"title":"Highly Uniform Low Gray AMOLED Pixel Using Stable Circuit and Duty Ratio Modulation Driving","authors":"Chanjin Park;Hee-Ok Kim;Jong-Heon Yang;Jae-Eun Pi;Yong-Duck Kim;Chun-Won Byun;Kyeong-Soo Kang;Ji-Hwan Park;Minji Kim;Hyoungsik Nam;Soo-Yeon Lee","doi":"10.1109/JEDS.2024.3452753","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3452753","url":null,"abstract":"In this paper, a new pixel circuit for active matrix organic light-emitting diode (AMOLED) display that can achieve high uniformity in low gray levels and its driving method are proposed. The proposed circuit compensates for threshold voltage variation of thin-film-transistors (TFTs), with the structure that minimizes the loss of sensed threshold voltage. However, the high current error rate in extremely low gray level is unavoidable, as the driving TFT (DRT) operates in subthreshold region, where the current difference caused by the threshold voltage variation can be severe. To suppress high error rates in low gray levels, the operation region of DRT is restricted to the saturation region, by adopting duty ratio modulation (DRM) method. With the DRM method, low gray is expressed with high current value and short emission time. The viability of the proposed circuit and its operation are analyzed with HSPICE. Compared to the conventional driving method, DRM significantly reduces the current error rate in low gray area. The proposed circuit is fabricated within 220 \u0000<inline-formula> <tex-math>$mu {mathrm {m}} times 440 mu {mathrm {m}}$ </tex-math></inline-formula>\u0000. The measurement of the circuit also verified the capability of the proposed circuit and the DRM method.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10663295","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142159891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-02DOI: 10.1109/JEDS.2024.3453408
Hanqi Gao;Jing Jin;Jianjun Zhou
An extraction method to obtain the noise model parameter $T_{mathrm { d}}$ in deep submicron MOSFETs directly from radio frequency (RF) scattering parameters and noise figure measurements is presented. A simplified noise equivalent circuit, along with closed-form solutions to calculate the RF noise figure of MOSFET is developed. On-wafer experimental verification is presented and a comparison with tuner based method is given. Good agreement is obtained between simulated and measured results for $16times 1times 2{{mu }rm m}$ (number of gate fingers $times $ unit gatewidth $times $ cells) gatelength MOSFETs.
{"title":"An Approach to Determine Noise Model Parameter for Submicron MOSFET from RF Noise Figure Measurement","authors":"Hanqi Gao;Jing Jin;Jianjun Zhou","doi":"10.1109/JEDS.2024.3453408","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3453408","url":null,"abstract":"An extraction method to obtain the noise model parameter \u0000<inline-formula> <tex-math>$T_{mathrm { d}}$ </tex-math></inline-formula>\u0000 in deep submicron MOSFETs directly from radio frequency (RF) scattering parameters and noise figure measurements is presented. A simplified noise equivalent circuit, along with closed-form solutions to calculate the RF noise figure of MOSFET is developed. On-wafer experimental verification is presented and a comparison with tuner based method is given. Good agreement is obtained between simulated and measured results for \u0000<inline-formula> <tex-math>$16times 1times 2{{mu }rm m}$ </tex-math></inline-formula>\u0000 (number of gate fingers \u0000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>\u0000 unit gatewidth \u0000<inline-formula> <tex-math>$times $ </tex-math></inline-formula>\u0000 cells) gatelength MOSFETs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10663413","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142165101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-02DOI: 10.1109/JEDS.2024.3453122
Nan Wu;Zhi Jin;Jingtao Zhou;Haomiao Wei;Zhicheng Liu;Jianming Lin
The research on high power 190 GHz doubler based on the GaAs Schottky diodes is proposed in this paper. The frequency doubler comprises a improved diode configuration that increases the number of anodes by changing the diode arrangement to improve power handling capacity. Electromagnetic and thermal simulation is utilized to demonstrate that the doubler can carry more power. The input power is gradually pumping from 200 mW to 500 mW with an applied DC bias of −15 V. And the peak efficiency of the doubler is measured to be 17%, while the maximum output power is 85 mW at 190 GHz.
{"title":"High Power 190 GHz Frequency Doubler Based On GaAs Schottky Diode","authors":"Nan Wu;Zhi Jin;Jingtao Zhou;Haomiao Wei;Zhicheng Liu;Jianming Lin","doi":"10.1109/JEDS.2024.3453122","DOIUrl":"10.1109/JEDS.2024.3453122","url":null,"abstract":"The research on high power 190 GHz doubler based on the GaAs Schottky diodes is proposed in this paper. The frequency doubler comprises a improved diode configuration that increases the number of anodes by changing the diode arrangement to improve power handling capacity. Electromagnetic and thermal simulation is utilized to demonstrate that the doubler can carry more power. The input power is gradually pumping from 200 mW to 500 mW with an applied DC bias of −15 V. And the peak efficiency of the doubler is measured to be 17%, while the maximum output power is 85 mW at 190 GHz.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10663496","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-26DOI: 10.1109/JEDS.2024.3449798
Yatexu Patel;Pouya Valizadeh
In this manuscript, we have investigated the impact of the scaling of the gate-source length (LGS) and gate length (LG) on the on-state breakdown voltage (BVon) of metallic-face InAlN/AlN/GaN heterostructure field effect transistors (HFETs) having fin structures only under the gate and those having them stretched from source to drain. The results show that the downscaling of LGS and LG augments the electron velocity in the source-access region. Due to current conservation, the higher carrier velocity in the source-access region for the devices having shorter LGS and LG induces a higher electron density under the gated-channel. From what is theoretically observed, the presence of higher electron density close to the boundary with the velocity saturation region at the drain edge of the gate in devices having shorter LGS and LG does seem to initiate the device breakdown at lower drain voltages, leading to the deterioration of the on-state breakdown voltage.
在本手稿中，我们研究了栅-源长度（LGS）和栅长度（LG）的缩放对金属面 InAlN/AlN/GaN 异质结构场效应晶体管（HFET）导通击穿电压（BVon）的影响。结果表明，LGS 和 LG 的缩减提高了源极-汲极区域的电子速度。由于电流守恒，LGS 和 LG 较短的器件在源极接入区的载流子速度较高，从而导致栅极沟道下的电子密度较高。从理论上观察，在 LGS 和 LG 较短的器件中，靠近栅极漏极边缘速度饱和区边界的较高电子密度似乎会在较低的漏极电压下引发器件击穿，从而导致导通击穿电压恶化。
{"title":"Impact of the Scaling of LGS and LG on the On-State Breakdown Voltage of InAlN/GaN HFETs With Localized Fin Under the Gate Electrode","authors":"Yatexu Patel;Pouya Valizadeh","doi":"10.1109/JEDS.2024.3449798","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3449798","url":null,"abstract":"In this manuscript, we have investigated the impact of the scaling of the gate-source length (LGS) and gate length (LG) on the on-state breakdown voltage (BVon) of metallic-face InAlN/AlN/GaN heterostructure field effect transistors (HFETs) having fin structures only under the gate and those having them stretched from source to drain. The results show that the downscaling of LGS and LG augments the electron velocity in the source-access region. Due to current conservation, the higher carrier velocity in the source-access region for the devices having shorter LGS and LG induces a higher electron density under the gated-channel. From what is theoretically observed, the presence of higher electron density close to the boundary with the velocity saturation region at the drain edge of the gate in devices having shorter LGS and LG does seem to initiate the device breakdown at lower drain voltages, leading to the deterioration of the on-state breakdown voltage.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10646346","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142137517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-21DOI: 10.1109/JEDS.2024.3447149
Gerardo Malavena;Salvatore M. Amoroso;Andrew R. Brown;Plamen Asenov;Xi-Wei Lin;Victor Moroz;Mattia Giulianini;David Refaldi;Christian Monzio Compagnoni;Alessandro S. Spinelli
In this two-part article we discuss the difference between a continuous and a discrete approach to trap modeling in the simulation of 3-D NAND Flash memories with polysilicon channel. In Part I we focus on threshold voltage $({mathrm { V}}_{mathrm { T}})$ fluctuations induced by traps and show that lower values for the average and rms ${mathrm { V}}_{mathrm { T}}$ arise when the discrete nature of traps is accounted for. We explain such differences in terms of a stronger percolation that leads to a lower number of filled traps in the discrete-trap case, and investigate such differences as a function of cell parameters and temperature. Finally, we compare the two approaches showing that a continuous trap model cannot reproduce the correct dependences resulting from a discrete treatment.
{"title":"Discrete-Trap Effects on 3-D NAND Variability – Part I: Threshold Voltage","authors":"Gerardo Malavena;Salvatore M. Amoroso;Andrew R. Brown;Plamen Asenov;Xi-Wei Lin;Victor Moroz;Mattia Giulianini;David Refaldi;Christian Monzio Compagnoni;Alessandro S. Spinelli","doi":"10.1109/JEDS.2024.3447149","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3447149","url":null,"abstract":"In this two-part article we discuss the difference between a continuous and a discrete approach to trap modeling in the simulation of 3-D NAND Flash memories with polysilicon channel. In Part I we focus on threshold voltage \u0000<inline-formula> <tex-math>$({mathrm { V}}_{mathrm { T}})$ </tex-math></inline-formula>\u0000 fluctuations induced by traps and show that lower values for the average and rms \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { T}}$ </tex-math></inline-formula>\u0000 arise when the discrete nature of traps is accounted for. We explain such differences in terms of a stronger percolation that leads to a lower number of filled traps in the discrete-trap case, and investigate such differences as a function of cell parameters and temperature. Finally, we compare the two approaches showing that a continuous trap model cannot reproduce the correct dependences resulting from a discrete treatment.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10643153","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142137553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-21DOI: 10.1109/JEDS.2024.3447022
Qiang Chen;Y. Q. Chen;Chang Liu;Zhiyuan He;Yuan Chen;K. W. Geng;Y. J. He;W. Y. Chen
In this paper, we investigate the electrical characteristics of AlGaN/GaN HEMTs at the lowest temperature of 20 K. The measurement results indicate that the output current of the device decreases significantly with increasing temperature at temperature ranging from 40 K to 260 K, and the saturation drain current decreases by 19%. The gate leakage current rises slightly when the temperature increases. However, both the transfer and C-V characteristics indicate that the threshold voltage shift slightly in a negative direction as the temperature rises. In order to determine the physical mechanism of electrical characteristics change, the low-frequency noise (LFN) characteristics at different temperatures were measured and the density of traps was extracted. Finally, we consider that there are two competing mechanisms affecting the electrical characteristics of devices. The trap density reduction caused by temperature rise leads to threshold voltage’s negative shift, while the drop of 2DEG mobility is the main reason for the decrease of output current.
测量结果表明，在 40 K 至 260 K 的温度范围内，器件的输出电流随着温度的升高而显著减小，饱和漏极电流减小了 19%。温度升高时，栅极漏电流略有上升。然而，转移特性和 C-V 特性都表明，随着温度升高，阈值电压略微向负方向移动。为了确定电气特性变化的物理机制，我们测量了不同温度下的低频噪声（LFN）特性，并提取了陷阱密度。最后，我们认为有两种相互竞争的机制影响着器件的电气特性。温度升高引起的陷阱密度降低导致阈值电压负移，而二维电子元件迁移率下降则是输出电流降低的主要原因。
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