We investigate the leakage current density–voltage (J–V) characteristics and gettering behavior of metallic impurities using a pn-junction diode fabricated with hydrocarbon (C3H5)-molecular-ion-implanted epitaxial silicon wafer. The pn-junction diode with C3H5 molecular ion implantation reduced the reverse leakage current. Additionally, metallic impurities such as Cu, Fe, and Au, identified by Deep level transient spectroscopy (DLTS) analysis, and oxygen dissolved in the silicon substrate were gettered in the C3H5-molecular-ion-implanted region. Furthermore, it became clear that the gettering behavior of metallic impurities and oxygen competes with one another during the pn-junction fabrication process. These findings suggest that lowering the oxygen concentration in silicon substrates improves the gettering capacity of metallic impurities.
{"title":"Metallic Impurity Gettering Behavior of Hydrocarbon-Molecular-Ion-Implanted Epitaxial Silicon Wafer During the pn-Junction Diode Fabrication Process","authors":"Sho Nagatomo;Takeshi Kadono;Ryo Hirose;Koji Kobayashi;Shun Sasaki;Kazunari Kurita","doi":"10.1109/JEDS.2025.3624795","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3624795","url":null,"abstract":"We investigate the leakage current density–voltage (J–V) characteristics and gettering behavior of metallic impurities using a pn-junction diode fabricated with hydrocarbon (C3H5)-molecular-ion-implanted epitaxial silicon wafer. The pn-junction diode with C3H5 molecular ion implantation reduced the reverse leakage current. Additionally, metallic impurities such as Cu, Fe, and Au, identified by Deep level transient spectroscopy (DLTS) analysis, and oxygen dissolved in the silicon substrate were gettered in the C3H5-molecular-ion-implanted region. Furthermore, it became clear that the gettering behavior of metallic impurities and oxygen competes with one another during the pn-junction fabrication process. These findings suggest that lowering the oxygen concentration in silicon substrates improves the gettering capacity of metallic impurities.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1282-1287"},"PeriodicalIF":2.4,"publicationDate":"2025-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11215678","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-22DOI: 10.1109/JEDS.2025.3624015
Bertwin Bilgrim Otto Seibertz;Bernd Szyszka
This work investigates the capability of direct current (DC) excited hollow cathode gas flow sputtering (GFS) to contribute to the synthesis of high performing thin films for micro electronic applications. Therefore, high-k tantalum oxide (TaOx) was deposited by reactive GFS onto heavily doped silicon and characterized in metal-insulator-semiconductor capacitors. The influence of substrate bias conditions on material properties like density, microstructure, dielectric constant, breakdown voltage and leakage current is studied. TaOx deposited unbiased exhibits columnar growth, leading to high leakage currents and insufficient isolation. The oxygen flow only had small influence on this behavior. By adding substrate bias, additional energy is provided to the growing films. Direct current (DC) bias lead only to minor improvements. Applying pulsed DC bias significantly improved layer properties. For 15V pulsed DC bias as deposited, ultra smooth TaOx achieved a dielectric constant in the order of 30, breakdown field strength above 5 MV/cm-1 and leakage currents in the order of 10−8 A/cm-2. Increasing the bias voltage decreased the performance of the films. The breakdown voltage shifts towards smaller values, and the leakage current at 2 MV/cm-1 increases. The density seems to be unaffected, however the surface morphology becomes rougher.
本文研究了直流（DC）激励空心阴极气体流溅射（GFS）在微电子应用中合成高性能薄膜的能力。因此，利用反应性GFS将高钾氧化钽（TaOx）沉积在重掺杂硅上，并在金属-绝缘体-半导体电容器中进行表征。研究了衬底偏置条件对材料密度、微观结构、介电常数、击穿电压和漏电流等性能的影响。TaOx无偏沉积呈现柱状生长，导致高泄漏电流和隔离不足。氧气流量对这一行为的影响很小。通过增加衬底偏压，可以为生长中的薄膜提供额外的能量。直流电（DC）的偏置只导致了微小的改进。施加脉冲直流偏压显著改善了层的性能。对于沉积的15V脉冲直流偏置，超光滑TaOx的介电常数约为30，击穿场强高于5 MV/cm-1，泄漏电流约为10−8 a /cm-2。增加偏置电压会降低薄膜的性能。击穿电压向更小的值移动，2 MV/cm-1的泄漏电流增大。密度似乎不受影响，但表面形貌变得粗糙。
{"title":"Deposition of High-k Tantalum Oxide by DC Hollow Cathode Gas Flow Sputtering and the Influence of DC and Pulsed DC Substrate Bias","authors":"Bertwin Bilgrim Otto Seibertz;Bernd Szyszka","doi":"10.1109/JEDS.2025.3624015","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3624015","url":null,"abstract":"This work investigates the capability of direct current (DC) excited hollow cathode gas flow sputtering (GFS) to contribute to the synthesis of high performing thin films for micro electronic applications. Therefore, high-k tantalum oxide (TaOx) was deposited by reactive GFS onto heavily doped silicon and characterized in metal-insulator-semiconductor capacitors. The influence of substrate bias conditions on material properties like density, microstructure, dielectric constant, breakdown voltage and leakage current is studied. TaOx deposited unbiased exhibits columnar growth, leading to high leakage currents and insufficient isolation. The oxygen flow only had small influence on this behavior. By adding substrate bias, additional energy is provided to the growing films. Direct current (DC) bias lead only to minor improvements. Applying pulsed DC bias significantly improved layer properties. For 15V pulsed DC bias as deposited, ultra smooth TaOx achieved a dielectric constant in the order of 30, breakdown field strength above 5 MV/cm-1 and leakage currents in the order of 10−8 A/cm-2. Increasing the bias voltage decreased the performance of the films. The breakdown voltage shifts towards smaller values, and the leakage current at 2 MV/cm-1 increases. The density seems to be unaffected, however the surface morphology becomes rougher.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1088-1097"},"PeriodicalIF":2.4,"publicationDate":"2025-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11214222","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In recent years, h-BN has emerged as a promising candidate for direct thermal neutron detection due to its compactness, efficiency, and radiation resistance, offering an attractive solution for long-term safety monitoring in harsh environments such as nuclear reactors. In this research, a high-performance thermal neutron detector was prepared using h-BN single crystals synthesized via the metal flux method. The detector demonstrates a leakage current as low as 112 pA and a stable specific capacitance of 158 pF/cm2 at a bias voltage of 100 V, ensuring low-noise operation. Simulation results indicated that the products of the 10B(n, $alpha $ )7Li nuclear reaction could deposit sufficient energy within the h-BN layers; when the total thickness of h-BN was $160~mu $ m, the theoretical thermal neutron detection efficiency approached 49.5%. Beamline tests at the BL20 thermal neutron station of the China Spallation Neutron Source reveals that the actual thermal neutron detection efficiency of the detector reaches 9.9%. The thermal neutron test spectrum exhibits two prominent peaks, corresponding to the $alpha $ particles and 7Li ions produced by the nuclear reaction. These results indicate that the stacked structure significantly enhances the neutron absorption probability and promotes effective charge collection, further highlighting the great potential of metal flux grown h-BN single crystals in next-generation thermal neutron detection technologies.
近年来，h-BN因其结构紧凑、效率高、耐辐射等优点，成为直接热中子探测的理想选择，为核反应堆等恶劣环境下的长期安全监测提供了有吸引力的解决方案。本研究利用金属通量法合成的h-BN单晶制备了高性能热中子探测器。在100 V的偏置电压下，该检测器的漏电流低至112 pA，比电容稳定为158 pF/cm2，可确保低噪声工作。模拟结果表明，10B(n, $alpha $)7Li核反应产物能在h-BN层内沉积足够的能量；当h-BN总厚度为$160~mu $ m时，理论热中子探测效率接近49.5%. Beamline tests at the BL20 thermal neutron station of the China Spallation Neutron Source reveals that the actual thermal neutron detection efficiency of the detector reaches 9.9%. The thermal neutron test spectrum exhibits two prominent peaks, corresponding to the $alpha $ particles and 7Li ions produced by the nuclear reaction. These results indicate that the stacked structure significantly enhances the neutron absorption probability and promotes effective charge collection, further highlighting the great potential of metal flux grown h-BN single crystals in next-generation thermal neutron detection technologies.
{"title":"High Efficiency Thermal Neutron Detection Using Vertically Stacked h-BN Single Crystals","authors":"Deyu Wang;Dawei Guo;Ze Long;Jiajin Tai;Xiaochuan Xia;Bin Tang;Wei Jiang;Ruirui Fan;Hong Yin;Hongwei Liang","doi":"10.1109/JEDS.2025.3623794","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3623794","url":null,"abstract":"In recent years, h-BN has emerged as a promising candidate for direct thermal neutron detection due to its compactness, efficiency, and radiation resistance, offering an attractive solution for long-term safety monitoring in harsh environments such as nuclear reactors. In this research, a high-performance thermal neutron detector was prepared using h-BN single crystals synthesized via the metal flux method. The detector demonstrates a leakage current as low as 112 pA and a stable specific capacitance of 158 pF/cm2 at a bias voltage of 100 V, ensuring low-noise operation. Simulation results indicated that the products of the 10B(n, <inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>)7Li nuclear reaction could deposit sufficient energy within the h-BN layers; when the total thickness of h-BN was <inline-formula> <tex-math>$160~mu $ </tex-math></inline-formula>m, the theoretical thermal neutron detection efficiency approached 49.5%. Beamline tests at the BL20 thermal neutron station of the China Spallation Neutron Source reveals that the actual thermal neutron detection efficiency of the detector reaches 9.9%. The thermal neutron test spectrum exhibits two prominent peaks, corresponding to the <inline-formula> <tex-math>$alpha $ </tex-math></inline-formula> particles and 7Li ions produced by the nuclear reaction. These results indicate that the stacked structure significantly enhances the neutron absorption probability and promotes effective charge collection, further highlighting the great potential of metal flux grown h-BN single crystals in next-generation thermal neutron detection technologies.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1082-1087"},"PeriodicalIF":2.4,"publicationDate":"2025-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11208689","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145405312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-20DOI: 10.1109/JEDS.2025.3623692
Gyuhyeon Lee;Myeongsang Yun;Seongjae Cho;Myounggon Kang
This study proposes a method to optimize the charge transfer mechanism in synaptic devices, a practical core component of neuromorphic systems, by employing bandgap engineering (BE) with high-$k$ materials. The conventional Al2O3 blocking oxide was substituted with a single $rm HfO_{2}$ layer and a stacked HfO2/Al2O3 structure to enhance the program and erase characteristics. Simulation results indicate that the structures utilizing high-$k$ materials demonstrated a larger threshold voltage $(V_{mathrm { th}})$ shift during program operations compared with the conventional structure. This improvement is attributed to the increased electron acceleration and the reduction in equivalent oxide thickness (EOT) due to the high permittivity of high-$k$ materials. Moreover, a greater $V_{mathrm { th}}$ shift was documented during erase operations, which is explained by the band offset between the blocking oxide and the nitride trap layer. Consequently, the BE charge-trap flash device demonstrated an enhancement of 2.22 V in the memory window compared with device in the conventional structure.
{"title":"Bandgap-Engineered Side-Path Synaptic Device Utilizing High- κ Materials for Low-Power Operation","authors":"Gyuhyeon Lee;Myeongsang Yun;Seongjae Cho;Myounggon Kang","doi":"10.1109/JEDS.2025.3623692","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3623692","url":null,"abstract":"This study proposes a method to optimize the charge transfer mechanism in synaptic devices, a practical core component of neuromorphic systems, by employing bandgap engineering (BE) with high-<inline-formula> <tex-math>$k$ </tex-math></inline-formula> materials. The conventional Al2O3 blocking oxide was substituted with a single <inline-formula> <tex-math>$rm HfO_{2}$ </tex-math></inline-formula> layer and a stacked HfO2/Al2O3 structure to enhance the program and erase characteristics. Simulation results indicate that the structures utilizing high-<inline-formula> <tex-math>$k$ </tex-math></inline-formula> materials demonstrated a larger threshold voltage <inline-formula> <tex-math>$(V_{mathrm { th}})$ </tex-math></inline-formula> shift during program operations compared with the conventional structure. This improvement is attributed to the increased electron acceleration and the reduction in equivalent oxide thickness (EOT) due to the high permittivity of high-<inline-formula> <tex-math>$k$ </tex-math></inline-formula> materials. Moreover, a greater <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula> shift was documented during erase operations, which is explained by the band offset between the blocking oxide and the nitride trap layer. Consequently, the BE charge-trap flash device demonstrated an enhancement of 2.22 V in the memory window compared with device in the conventional structure.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1098-1102"},"PeriodicalIF":2.4,"publicationDate":"2025-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11208718","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The p-type doping of solid-phase crystallized molybdenum disulfide (MoS${}_{2}$ ) films deposited via radio-frequency magnetron sputtering has been achieved by nitrogen annealing accelerated by hydrogen using forming gas (3% H2/N${}_{2}$ ). The hydrogen reduces S-S and also Mo-S bondings on the PVD-MoS2 film surface formed by sulfur vapor annealing, allowing for the incorporation of nitrogen in the film and resulting in p-type doping. Based on the experimental results, the Fermi level of MoS2 film relative to valence band maximum shifted from 0.79 to 0.53 eV after forming gas annealing at 100°C. Thus, it is suggested that the nitrogen annealing accelerated by hydrogen, with careful consideration of the balance between the effects of S-S bonding reduction and nitrogen incorporation, serves as a non-destructive p-type doping method for solid-phase crystallized PVD-MoS2 films compatible with the complementary metal-oxide-semiconductor (CMOS) process.
{"title":"P-Type Doping of Solid-Phase Crystallized PVD-MoS₂ Film Using Nitrogen Annealing Accelerated by Hydrogen","authors":"Jaehyo Jang;Shinya Imai;Naoki Matsunaga;Soma Ito;Kaede Teraoka;Md Iftekharul Alam;Takuya Hoshii;Kuniyuki Kakushima;Akinobu Teramoto;Hitoshi Wakabayashi","doi":"10.1109/JEDS.2025.3619018","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3619018","url":null,"abstract":"The p-type doping of solid-phase crystallized molybdenum disulfide (MoS<inline-formula> <tex-math>${}_{2}$ </tex-math></inline-formula>) films deposited via radio-frequency magnetron sputtering has been achieved by nitrogen annealing accelerated by hydrogen using forming gas (3% H2/N<inline-formula> <tex-math>${}_{2}$ </tex-math></inline-formula>). The hydrogen reduces S-S and also Mo-S bondings on the PVD-MoS2 film surface formed by sulfur vapor annealing, allowing for the incorporation of nitrogen in the film and resulting in p-type doping. Based on the experimental results, the Fermi level of MoS2 film relative to valence band maximum shifted from 0.79 to 0.53 eV after forming gas annealing at 100°C. Thus, it is suggested that the nitrogen annealing accelerated by hydrogen, with careful consideration of the balance between the effects of S-S bonding reduction and nitrogen incorporation, serves as a non-destructive p-type doping method for solid-phase crystallized PVD-MoS2 films compatible with the complementary metal-oxide-semiconductor (CMOS) process.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1288-1298"},"PeriodicalIF":2.4,"publicationDate":"2025-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11196062","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) are beginning to be installed in electric vehicles (EVs), and the demand for reliability as well as chip performance is increasing. Generally, multiple chips are connected in parallel. Although SiC MOSFETs have a smaller temperature dependence of on-resistance <inline-formula> <tex-math>$(R_{mathrm { on}})$ </tex-math></inline-formula> than Si MOSFETs, they are prone to current imbalance due to the negative temperature dependence of the threshold voltage <inline-formula> <tex-math>$(V_{mathrm { th}})$ </tex-math></inline-formula>, which is also affected by the dispersion of <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula>, and is said to be a challenge for module stability and reliability <xref>[1]</xref>, <xref>[2]</xref>, <xref>[3]</xref>. To solve this problem, appropriate chip classification, addition of inductance, and devising a new gate driving method are being considered <xref>[4]</xref>, <xref>[5]</xref>, <xref>[6]</xref>. However, from the perspective of chip suppliers, ensuring uniformity of <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula> is the top priority. So far, the high electron trap density at the MOS interface of SiC MOSFETs has been a major obstacle to improving performance. Post oxidation annealing (POA) technology after gate oxidation has improved channel mobility by passivating electron traps <xref>[7]</xref>, and the channel resistance has been significantly reduced by increasing the channel density through the application of trench-type gates with sidewalls made of the crystal planes of {1-100} or {11-20} with the low electron trap density <xref>[8]</xref>, <xref>[9]</xref>, <xref>[10]</xref>. However, since the electron trap density is strongly dependent on the crystal plane orientation <xref>[11]</xref>, <xref>[12]</xref>, the interface charge density will vary if the crystal orientation of the MOS interface is misaligned. As a result, the angle misalignment of the trench sidewalls causes variations in <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula>. In response to this, we have developed a V-shaped trench MOSFET (VMOSFET) with sidewalls made of {0-33-8} planes, which have the smallest electron trap density <xref>[13]</xref>, <xref>[14]</xref>, <xref>[15]</xref>, <xref>[16]</xref>. Since V-shaped trenches are formed by a thermo-chemical etching in a chlorine gas ambient <xref>[17]</xref>, <xref>[18]</xref>, the crystal planes are naturally exposed according to the chemical properties of 4H-SiC, the crystal orientation of the MOS interface is not essentially misaligned. Therefore, it is possible to manufacture chips with small variations in <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula> and good reproducibility. In this article, we introduce the unique device structures and manufacturing processes that support the performance and reliability of the
{"title":"Key Technologies Supporting High Performance and Reliability of SiC VMOSFET","authors":"Takeyoshi Masuda;Yoshinori Hara;Tomoki Ikeda;Kosuke Uchida;Yu Saito;Shin Harada;Tomoaki Hatayama;Jun Wada;Toru Hiyoshi;Hirofumi Yamamoto;Masaki Furumai;Takao Kiyama;Heiji Watanabe","doi":"10.1109/JEDS.2025.3614628","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3614628","url":null,"abstract":"4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) are beginning to be installed in electric vehicles (EVs), and the demand for reliability as well as chip performance is increasing. Generally, multiple chips are connected in parallel. Although SiC MOSFETs have a smaller temperature dependence of on-resistance <inline-formula> <tex-math>$(R_{mathrm { on}})$ </tex-math></inline-formula> than Si MOSFETs, they are prone to current imbalance due to the negative temperature dependence of the threshold voltage <inline-formula> <tex-math>$(V_{mathrm { th}})$ </tex-math></inline-formula>, which is also affected by the dispersion of <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula>, and is said to be a challenge for module stability and reliability <xref>[1]</xref>, <xref>[2]</xref>, <xref>[3]</xref>. To solve this problem, appropriate chip classification, addition of inductance, and devising a new gate driving method are being considered <xref>[4]</xref>, <xref>[5]</xref>, <xref>[6]</xref>. However, from the perspective of chip suppliers, ensuring uniformity of <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula> is the top priority. So far, the high electron trap density at the MOS interface of SiC MOSFETs has been a major obstacle to improving performance. Post oxidation annealing (POA) technology after gate oxidation has improved channel mobility by passivating electron traps <xref>[7]</xref>, and the channel resistance has been significantly reduced by increasing the channel density through the application of trench-type gates with sidewalls made of the crystal planes of {1-100} or {11-20} with the low electron trap density <xref>[8]</xref>, <xref>[9]</xref>, <xref>[10]</xref>. However, since the electron trap density is strongly dependent on the crystal plane orientation <xref>[11]</xref>, <xref>[12]</xref>, the interface charge density will vary if the crystal orientation of the MOS interface is misaligned. As a result, the angle misalignment of the trench sidewalls causes variations in <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula>. In response to this, we have developed a V-shaped trench MOSFET (VMOSFET) with sidewalls made of {0-33-8} planes, which have the smallest electron trap density <xref>[13]</xref>, <xref>[14]</xref>, <xref>[15]</xref>, <xref>[16]</xref>. Since V-shaped trenches are formed by a thermo-chemical etching in a chlorine gas ambient <xref>[17]</xref>, <xref>[18]</xref>, the crystal planes are naturally exposed according to the chemical properties of 4H-SiC, the crystal orientation of the MOS interface is not essentially misaligned. Therefore, it is possible to manufacture chips with small variations in <inline-formula> <tex-math>$V_{mathrm { th}}$ </tex-math></inline-formula> and good reproducibility. In this article, we introduce the unique device structures and manufacturing processes that support the performance and reliability of the","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1267-1275"},"PeriodicalIF":2.4,"publicationDate":"2025-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11182284","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work uncovers a temperature-dependent relationship between gate leakage current ($mathrm{I}_{mathrm{G}}$ ) and threshold voltage shift ($Delta mathrm{V}_{mathrm{TH}}$ ) through an evaluation combining deep level transient spectroscopy (DLTS) measurements, $mathrm{I}_{mathrm{G}}$ testing, and assessments of $mathrm{V}_{mathrm{TH}}$ instability. Analysis across a temperature range of 80 K to 440 K of p-GaN gate defects on device characteristics. These findings indicate that the same type of gate defects simultaneously affects both gate leakage and $mathrm{V}_{mathrm{TH}}$ instability. Specifically, defects release holes during positive gate stress. During low-bias $mathrm{V}_{text {TH }}$ measurement, the persistent negative charge from defects, due to slow hole re-trapping, enhances the depletion of the two-dimensional electron gas (2DEG) at the AlGaN/GaN interface, reducing 2DEG density and causing a positive $Delta mathrm{V}_{mathrm{TH}}$ . Furthermore, high-temperature gate bias (HTGB) stress significantly increases the concentration of relevant defects within the p-GaN gate, leading to a marked rise in both $mathrm{I}_{mathrm{G}}$ and $Delta mathrm{V}_{mathrm{TH}}$ . Notably, the $mathrm{I}_{mathrm{G}} / Delta mathrm{V}_{mathrm{TH}}$ ratio remains consistent even after HTGB stress. These observations provide valuable insights into the relationship between gate defects and the performance of p-GaN gate HEMT.
{"title":"Study on the Relationship Between Threshold Voltage Instability and Gate Leakage Current in p-GaN HEMTs","authors":"Yifan Cui;Yang Jiang;Yutian Gan;Qiaoyu Hu;Qing Wang;Hongyu Yu","doi":"10.1109/JEDS.2025.3603890","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3603890","url":null,"abstract":"This work uncovers a temperature-dependent relationship between gate leakage current (<inline-formula> <tex-math>$mathrm{I}_{mathrm{G}}$ </tex-math></inline-formula>) and threshold voltage shift (<inline-formula> <tex-math>$Delta mathrm{V}_{mathrm{TH}}$ </tex-math></inline-formula>) through an evaluation combining deep level transient spectroscopy (DLTS) measurements, <inline-formula> <tex-math>$mathrm{I}_{mathrm{G}}$ </tex-math></inline-formula> testing, and assessments of <inline-formula> <tex-math>$mathrm{V}_{mathrm{TH}}$ </tex-math></inline-formula> instability. Analysis across a temperature range of 80 K to 440 K of p-GaN gate defects on device characteristics. These findings indicate that the same type of gate defects simultaneously affects both gate leakage and <inline-formula> <tex-math>$mathrm{V}_{mathrm{TH}}$ </tex-math></inline-formula> instability. Specifically, defects release holes during positive gate stress. During low-bias <inline-formula> <tex-math>$mathrm{V}_{text {TH }}$ </tex-math></inline-formula> measurement, the persistent negative charge from defects, due to slow hole re-trapping, enhances the depletion of the two-dimensional electron gas (2DEG) at the AlGaN/GaN interface, reducing 2DEG density and causing a positive <inline-formula> <tex-math>$Delta mathrm{V}_{mathrm{TH}}$ </tex-math></inline-formula>. Furthermore, high-temperature gate bias (HTGB) stress significantly increases the concentration of relevant defects within the p-GaN gate, leading to a marked rise in both <inline-formula> <tex-math>$mathrm{I}_{mathrm{G}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$Delta mathrm{V}_{mathrm{TH}}$ </tex-math></inline-formula>. Notably, the <inline-formula> <tex-math>$mathrm{I}_{mathrm{G}} / Delta mathrm{V}_{mathrm{TH}}$ </tex-math></inline-formula> ratio remains consistent even after HTGB stress. These observations provide valuable insights into the relationship between gate defects and the performance of p-GaN gate HEMT.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1018-1025"},"PeriodicalIF":2.4,"publicationDate":"2025-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11148282","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145110192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-28DOI: 10.1109/JEDS.2025.3603559
Satoshi Fujii;Soma Shimabukuro;Akira Uedono
The miniaturization of Si-MOS-FET logic integrated circuits necessitates the precise control of electron and hole densities through high-concentration impurity doping to realize transistors within the 2 nm technology node. Among the various thermal treatment techniques, microwave annealing (MWA) has emerged as a promising method for forming high-concentration active layers, offering advantages such as rapid processing and potential nonthermal effects. However, existing MWA systems suffer from interference and standing-wave effects because of their multimode cavity design, which makes it challenging to understand the underlying mechanisms. This study investigated the fundamental heating mechanisms of MWA, focusing on both the electric and magnetic field contributions. The role of Joule heating was examined, and the presence of nonthermal microwave effects was explored by applying MWA to Si substrates implanted with phosphorus or boron and comparing the results with those of conventional rapid thermal processing. The experimental evaluations included sheet resistance measurements, impurity distribution analysis, and defect assessments using slow-energy positron annihilation spectroscopy. The findings indicate that MWA enables the effective activation of implanted impurities at low temperatures, reduces defect formation, and minimizes impurity diffusion, highlighting its potential as a low-temperature processing technique for fabricating advanced semiconductor devices.
{"title":"Mechanistic Insights Into Microwave Annealing for Lattice Defect Recovery","authors":"Satoshi Fujii;Soma Shimabukuro;Akira Uedono","doi":"10.1109/JEDS.2025.3603559","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3603559","url":null,"abstract":"The miniaturization of Si-MOS-FET logic integrated circuits necessitates the precise control of electron and hole densities through high-concentration impurity doping to realize transistors within the 2 nm technology node. Among the various thermal treatment techniques, microwave annealing (MWA) has emerged as a promising method for forming high-concentration active layers, offering advantages such as rapid processing and potential nonthermal effects. However, existing MWA systems suffer from interference and standing-wave effects because of their multimode cavity design, which makes it challenging to understand the underlying mechanisms. This study investigated the fundamental heating mechanisms of MWA, focusing on both the electric and magnetic field contributions. The role of Joule heating was examined, and the presence of nonthermal microwave effects was explored by applying MWA to Si substrates implanted with phosphorus or boron and comparing the results with those of conventional rapid thermal processing. The experimental evaluations included sheet resistance measurements, impurity distribution analysis, and defect assessments using slow-energy positron annihilation spectroscopy. The findings indicate that MWA enables the effective activation of implanted impurities at low temperatures, reduces defect formation, and minimizes impurity diffusion, highlighting its potential as a low-temperature processing technique for fabricating advanced semiconductor devices.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1258-1266"},"PeriodicalIF":2.4,"publicationDate":"2025-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11143163","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-27DOI: 10.1109/JEDS.2025.3603203
A. Uedono;R. Tanaka;S. Takashima;K. Ueno;M. Edo;K. Shima;S. F. Chichibu;J. Uzuhashi;T. Ohkubo;S. Ishibashi;K. Sierakowski;M. Bockowski
Annealing behaviors of vacancy-type defects in Mg and N-implanted GaN were studied by positron annihilation. The major defect species in as-implanted samples was identified as Ga-vacancy (VGa)-type defects. For Mg-implanted GaN with sequential N-implantation after annealing above 1000°C, the defect species were vacancy clusters such as (VGaVN)3. Due to the downward shift of the Fermi level position resulting from a partial activation of Mg, the charge states of defects tended to become positive. For N-implanted GaN, the size of the vacancy cluster started to decrease above 1200°C annealing, which was attributed to recombinations between VNs coupled with VGas and excess N atoms. The impact of sequential N-implantations on vacancies in Mg-implanted GaN was found to be most pronounced when the ratio of the concentration of N to that of Mg was three.
{"title":"Characterization of Vacancy-Type Defects in Mg- and N-Implanted GaN by Using a Monoenergetic Positron Beam","authors":"A. Uedono;R. Tanaka;S. Takashima;K. Ueno;M. Edo;K. Shima;S. F. Chichibu;J. Uzuhashi;T. Ohkubo;S. Ishibashi;K. Sierakowski;M. Bockowski","doi":"10.1109/JEDS.2025.3603203","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3603203","url":null,"abstract":"Annealing behaviors of vacancy-type defects in Mg and N-implanted GaN were studied by positron annihilation. The major defect species in as-implanted samples was identified as Ga-vacancy (VGa)-type defects. For Mg-implanted GaN with sequential N-implantation after annealing above 1000°C, the defect species were vacancy clusters such as (VGaVN)3. Due to the downward shift of the Fermi level position resulting from a partial activation of Mg, the charge states of defects tended to become positive. For N-implanted GaN, the size of the vacancy cluster started to decrease above 1200°C annealing, which was attributed to recombinations between VNs coupled with VGas and excess N atoms. The impact of sequential N-implantations on vacancies in Mg-implanted GaN was found to be most pronounced when the ratio of the concentration of N to that of Mg was three.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1252-1257"},"PeriodicalIF":2.4,"publicationDate":"2025-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11142782","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper introduces the deposition of seed layers using a soaking technique to deposit dielectric layers on transition metal dichalcogenides (TMDs). This method addresses the bottleneck caused by the lack of dangling bonds in two-dimensional materials, which hinders the adsorption of precursors during the ALD process. We utilize the Hafnium soak technique, which can facilitate depositing a gate dielectric onto TMDs exhibiting smooth film characteristics and outstanding physical properties. We fabricate dual-gate devices using TMDs with an equivalent oxide thickness (EOT) of 1 nm and a subthreshold swing (S.S.) of 94 mV/dec. Additionally, the soaking technique promotes growth on both the top and back sides of two-dimensional materials, facilitating the development of gate-all-around (GAA) field-effect transistors.
{"title":"Low Temperature HfO₂ Interface Engineering in Dual-Gate and Gate-All-Around MoS₂ Transistors","authors":"Po-Heng Pao;Cheng-Yi Lin;Heng-Tung Hsu;Chao-Hsin Chien","doi":"10.1109/JEDS.2025.3600006","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3600006","url":null,"abstract":"This paper introduces the deposition of seed layers using a soaking technique to deposit dielectric layers on transition metal dichalcogenides (TMDs). This method addresses the bottleneck caused by the lack of dangling bonds in two-dimensional materials, which hinders the adsorption of precursors during the ALD process. We utilize the Hafnium soak technique, which can facilitate depositing a gate dielectric onto TMDs exhibiting smooth film characteristics and outstanding physical properties. We fabricate dual-gate devices using TMDs with an equivalent oxide thickness (EOT) of 1 nm and a subthreshold swing (S.S.) of 94 mV/dec. Additionally, the soaking technique promotes growth on both the top and back sides of two-dimensional materials, facilitating the development of gate-all-around (GAA) field-effect transistors.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1006-1009"},"PeriodicalIF":2.4,"publicationDate":"2025-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11129037","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145011290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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