In this paper, the stress degradation of P-channel Fin Field-Effect Transistor (FinFET) under AC mixed NBTI and HCD stress is studied and compared with the effects of individual NBTI and HCD. In the scope of this study, degradation caused by interface traps becomes more and more dominant with the increase of individual NBTI stress. The more significant degradation observed under individual HCD stress, in comparison to individual NBTI stress at the same voltage, may primarily be attributed to an increase in interfacial traps. The AC mixed stress experiment demonstrates that the interruption of NBTI stress persistence leads to a significant reduction in the defect components within the oxide layer affected by NBTI. Even when NBTI accounts for 85% of the total degradation, the overall extent of degradation remains considerably lower than that observed with single NBTI. Consequently, in AC scenarios, interface traps emerge as the primary contributors to degradation. This finding may hold substantial implications for circuit designers. In practical AC applications, it may reduce the design margin allocated to degradation, thereby avoiding overdesign.
{"title":"Research on Degradation of P-FinFET Under Mixed NBTI and HCD Stress","authors":"Yanghao Wang;Hang Xu;Peng Liao;Jianbin Guo;Qingqing Sun;David Wei Zhang","doi":"10.1109/JEDS.2026.3653934","DOIUrl":"https://doi.org/10.1109/JEDS.2026.3653934","url":null,"abstract":"In this paper, the stress degradation of P-channel Fin Field-Effect Transistor (FinFET) under AC mixed NBTI and HCD stress is studied and compared with the effects of individual NBTI and HCD. In the scope of this study, degradation caused by interface traps becomes more and more dominant with the increase of individual NBTI stress. The more significant degradation observed under individual HCD stress, in comparison to individual NBTI stress at the same voltage, may primarily be attributed to an increase in interfacial traps. The AC mixed stress experiment demonstrates that the interruption of NBTI stress persistence leads to a significant reduction in the defect components within the oxide layer affected by NBTI. Even when NBTI accounts for 85% of the total degradation, the overall extent of degradation remains considerably lower than that observed with single NBTI. Consequently, in AC scenarios, interface traps emerge as the primary contributors to degradation. This finding may hold substantial implications for circuit designers. In practical AC applications, it may reduce the design margin allocated to degradation, thereby avoiding overdesign.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"70-78"},"PeriodicalIF":2.4,"publicationDate":"2026-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11347527","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-30DOI: 10.1109/JEDS.2025.3648598
{"title":"IEEE ELECTRON DEVICES SOCIETY","authors":"","doi":"10.1109/JEDS.2025.3648598","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3648598","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"C2-C2"},"PeriodicalIF":2.4,"publicationDate":"2025-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11319359","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145886667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this study, we demonstrate a hybrid ferroelectric charge-trapping gate-stack enhancement-mode GaN tri-gate high electron mobility transistor (FEG-HEMT) featuring a fluorinated HfO2 (F-HfO2) charge trapping layer (CTL), combined with a tri-gate architecture for power device applications. This architecture integrates ferroelectric polarization and charge-trapping mechanisms within a tri-gate nanowire (fin) structure to achieve normally-off operation. Unlike conventional planar HEMTs, the tri-gate configuration exposes the 2-dimensional electron gas (2DEG) channel along the fin sidewalls, enabling effective depletion through trapped charges in the CTL, thereby achieving a high and stable threshold voltage (VTH). There is a possibility that incorporating fluorine into the HfO2 layer reduces oxygen vacancies and dangling bonds, significantly improving the dielectric interface and device reliability. At the dielectric/semiconductor interface, the interface trap density (Dit) was estimated to be $sim ~1times 10{^{{11}}}$ to $1.2times 10{^{{13}}}$ cm${^{text {$mathord {-}$2}}} cdot $ eV${}^{text {$mathord {-}$1}}$ , as extracted using the frequency-dependent conductance method. The tri-gate device demonstrates an impressive VTH of 4.4 ± 0.2 V, I${}_{text {DS-MAX}}$ of 946 ± 10 mA/mm, breakdown voltage (BV) of 768 V, and a high-power figure-of-merit (PFOM) of 973 MW/cm2. Additionally, the device exhibits enhanced time-dependent dielectric breakdown (TDDB) lifetime and gate stress resilience, confirming its superior performance and robustness for high-power applications.
在这项研究中，我们展示了一种混合铁电电荷捕获门堆栈增强模式GaN三栅极高电子迁移率晶体管（fg - hemt），具有氟化HfO2 （F-HfO2）电荷捕获层（CTL），并结合了用于功率器件应用的三栅极结构。该结构将铁电极化和电荷捕获机制集成在三栅极纳米线（鳍）结构中，以实现正常关闭操作。与传统的平面hemt不同，三栅极结构暴露了沿翅片侧壁的二维电子气（2DEG）通道，通过CTL中的捕获电荷实现有效耗尽，从而实现高而稳定的阈值电压（VTH）。在HfO2层中加入氟有可能减少氧空位和悬空键，显著改善介电界面和器件可靠性。在介质/半导体界面处，使用频率相关电导法提取的界面陷阱密度（Dit）估计为$sim ~1乘以10{^{{11}}}$到$1.2乘以10{^{{11}}}$ cm ${^{text {$mathord {-}$2}}} cdot $ eV ${}}^{text {$mathord{-}$1} $。该三栅极器件的VTH为4.4±0.2 V，击穿电压为946±10 mA/mm，击穿电压（BV）为768 V，大功率性能因数（PFOM）为973 MW/cm2。此外，该器件具有增强的时间相关介质击穿（TDDB）寿命和栅极应力恢复能力，证实了其在高功率应用中的优越性能和稳健性。
{"title":"Enhancement Mode GaN Tri-Gate MISHEMT With Fluorinated HfO₂ as Charge Trapping Layer in Hybrid Ferroelectric Gate Stack","authors":"Rahul Rai;Khanh Quoc Nguyen;Hung Duy Tran;Viet Quoc Ho;You Chen Weng;Baquer Mazhari;Hao Chung Kuo;Edward Yi Chang","doi":"10.1109/JEDS.2025.3649208","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3649208","url":null,"abstract":"In this study, we demonstrate a hybrid ferroelectric charge-trapping gate-stack enhancement-mode GaN tri-gate high electron mobility transistor (FEG-HEMT) featuring a fluorinated HfO2 (F-HfO2) charge trapping layer (CTL), combined with a tri-gate architecture for power device applications. This architecture integrates ferroelectric polarization and charge-trapping mechanisms within a tri-gate nanowire (fin) structure to achieve normally-off operation. Unlike conventional planar HEMTs, the tri-gate configuration exposes the 2-dimensional electron gas (2DEG) channel along the fin sidewalls, enabling effective depletion through trapped charges in the CTL, thereby achieving a high and stable threshold voltage (VTH). There is a possibility that incorporating fluorine into the HfO2 layer reduces oxygen vacancies and dangling bonds, significantly improving the dielectric interface and device reliability. At the dielectric/semiconductor interface, the interface trap density (Dit) was estimated to be <inline-formula> <tex-math>$sim ~1times 10{^{{11}}}$ </tex-math></inline-formula> to <inline-formula> <tex-math>$1.2times 10{^{{13}}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math>${^{text {$mathord {-}$2}}} cdot $ </tex-math></inline-formula>eV<inline-formula> <tex-math>${}^{text {$mathord {-}$1}}$ </tex-math></inline-formula>, as extracted using the frequency-dependent conductance method. The tri-gate device demonstrates an impressive VTH of 4.4 ± 0.2 V, I<inline-formula> <tex-math>${}_{text {DS-MAX}}$ </tex-math></inline-formula> of 946 ± 10 mA/mm, breakdown voltage (BV) of 768 V, and a high-power figure-of-merit (PFOM) of 973 MW/cm2. Additionally, the device exhibits enhanced time-dependent dielectric breakdown (TDDB) lifetime and gate stress resilience, confirming its superior performance and robustness for high-power applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1313-1319"},"PeriodicalIF":2.4,"publicationDate":"2025-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11317969","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-24DOI: 10.1109/JEDS.2025.3647724
J. Ajayan;Vakkalakula Bharath Sreenivasulu;Amit Krishna Dwivedi;Shubham Tayal
The relentless advancement of the semiconductor industry continues to be fueled by the pursuit of enhanced transistor performance. As CMOS technology undergoes aggressive scaling to enable higher integration densities in modern integrated circuits (ICs), there arises a pressing demand for novel device architectures that can minimize cell area without compromising functionality. The complementary-field-effect-transistor (CFET) is emerging as a leading contender to succeed gate-all-around (GAA) FETs beyond the 2-nm technology node, offering a compelling pathway to sustain Moore’s Law into the next era of scaling. Unlike forksheet FET (FSFET) architectures, where nFET and pFET devices are laterally separated, CFETs adopt a vertically stacked configuration. This vertical integration minimizes the required device footprint, constrained primarily by cell height rather than horizontal spacing. As a result, CFETs not only enhance the effective channel width and drive current but also offer the potential for up to a twofold increase in integration density compared to conventional CMOS technologies. This review explores recent advances in CFET architectures, fabrication progress, and associated challenges, exciting prospects in IC design enabled by CFET’s compact structure and vertical integration. Finally, the article highlights critical reliability concerns, emphasizing the need for continued innovation to ensure robust device performance. CFET stands at the forefront of next-generation transistor technologies.
{"title":"Complementary Field Effect Transistor (CFET) for the 2-nm Technology Node: A Review From Device to Circuit Perspectives","authors":"J. Ajayan;Vakkalakula Bharath Sreenivasulu;Amit Krishna Dwivedi;Shubham Tayal","doi":"10.1109/JEDS.2025.3647724","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3647724","url":null,"abstract":"The relentless advancement of the semiconductor industry continues to be fueled by the pursuit of enhanced transistor performance. As CMOS technology undergoes aggressive scaling to enable higher integration densities in modern integrated circuits (ICs), there arises a pressing demand for novel device architectures that can minimize cell area without compromising functionality. The complementary-field-effect-transistor (CFET) is emerging as a leading contender to succeed gate-all-around (GAA) FETs beyond the 2-nm technology node, offering a compelling pathway to sustain Moore’s Law into the next era of scaling. Unlike forksheet FET (FSFET) architectures, where nFET and pFET devices are laterally separated, CFETs adopt a vertically stacked configuration. This vertical integration minimizes the required device footprint, constrained primarily by cell height rather than horizontal spacing. As a result, CFETs not only enhance the effective channel width and drive current but also offer the potential for up to a twofold increase in integration density compared to conventional CMOS technologies. This review explores recent advances in CFET architectures, fabrication progress, and associated challenges, exciting prospects in IC design enabled by CFET’s compact structure and vertical integration. Finally, the article highlights critical reliability concerns, emphasizing the need for continued innovation to ensure robust device performance. CFET stands at the forefront of next-generation transistor technologies.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"58-69"},"PeriodicalIF":2.4,"publicationDate":"2025-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11314663","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-23DOI: 10.1109/JEDS.2025.3647706
Andreas Fuchsberger;Nikolas Knaller;Daniele Nazzari;Jacqueline Marböck;Enrique Prado Navarrete;Moritz Brehm;Aníbal Pacheco-Sanchez;Lilian Vogl;Peter Schweizer;Walter M. Weber;Masiar Sistani
Transistors capable of operating at cryogenic temperatures are key components for the fast and energy-efficient control and readout of qubits. However, the ultra-low power requirements and performance metrics are not met by conventional complementary metal oxide semiconductor technology, which has been optimized for room-temperature operation. Here, we propose to enhance Si-based Schottky junction field-effect transistors with ultra-thin layers of SiGeSn to address these issues. By combining single-elementary Al contacts to avoid dopant freeze-out and utilizing a multi-gate transistor architecture, which suppresses reverse junction leakage, a fivefold increase in on-current and a threefold increase in peak transconductance were achieved compared to a Si reference device. Measurements down to 5 K revealed a drain current modulation over nine orders of magnitude with improved inverse subthreshold slopes of 20 mV/dec below 50 K and 50% reduced threshold voltages, while the on-currents remain mostly temperature-independent, making the system interesting for cryogenic computing.
{"title":"A Cryogenic Ultra-Thin Body SiGeSn Transistor","authors":"Andreas Fuchsberger;Nikolas Knaller;Daniele Nazzari;Jacqueline Marböck;Enrique Prado Navarrete;Moritz Brehm;Aníbal Pacheco-Sanchez;Lilian Vogl;Peter Schweizer;Walter M. Weber;Masiar Sistani","doi":"10.1109/JEDS.2025.3647706","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3647706","url":null,"abstract":"Transistors capable of operating at cryogenic temperatures are key components for the fast and energy-efficient control and readout of qubits. However, the ultra-low power requirements and performance metrics are not met by conventional complementary metal oxide semiconductor technology, which has been optimized for room-temperature operation. Here, we propose to enhance Si-based Schottky junction field-effect transistors with ultra-thin layers of SiGeSn to address these issues. By combining single-elementary Al contacts to avoid dopant freeze-out and utilizing a multi-gate transistor architecture, which suppresses reverse junction leakage, a fivefold increase in on-current and a threefold increase in peak transconductance were achieved compared to a Si reference device. Measurements down to 5 K revealed a drain current modulation over nine orders of magnitude with improved inverse subthreshold slopes of 20 mV<italic>/</i>dec below 50 K and 50% reduced threshold voltages, while the on-currents remain mostly temperature-independent, making the system interesting for cryogenic computing.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"24-29"},"PeriodicalIF":2.4,"publicationDate":"2025-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11313085","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145886668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-15DOI: 10.1109/JEDS.2025.3644310
Wallace Lin;Darsen D. Lu
A method directly solving Fowler-Nordheim tunneling current equations for extracting the effective tunneling area, the barrier heights of the top and bottom electrodes and the electron tunneling effective mass in metal-insulator-metal diodes is demonstrated. Extracted result from the method is comparable with that obtained from the automated Cowell method. The property of the Pt-Al2O3-TiN and Ni-Al2O3-TiN diodes are extracted and analyzed. The effective tunneling area appears to be four to five orders smaller than the drawn device area, suggesting tunneling current flows in very narrow conduction channel(s).
{"title":"Direct Extraction of Fowler–Nordheim Tunneling Parameters of Asymmetric Metal-Insulator-Metal Diodes Based on Current-Voltage Measurement","authors":"Wallace Lin;Darsen D. Lu","doi":"10.1109/JEDS.2025.3644310","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3644310","url":null,"abstract":"A method directly solving Fowler-Nordheim tunneling current equations for extracting the effective tunneling area, the barrier heights of the top and bottom electrodes and the electron tunneling effective mass in metal-insulator-metal diodes is demonstrated. Extracted result from the method is comparable with that obtained from the automated Cowell method. The property of the Pt-Al2O3-TiN and Ni-Al2O3-TiN diodes are extracted and analyzed. The effective tunneling area appears to be four to five orders smaller than the drawn device area, suggesting tunneling current flows in very narrow conduction channel(s).","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"18-23"},"PeriodicalIF":2.4,"publicationDate":"2025-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11299545","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-11DOI: 10.1109/JEDS.2025.3642939
Theo Cabaret;Eva Dos Reis;Valerie Lapras;Nicolas Gauthier;Joel Kanyandekwe
Improvement of source/drain regions is necessary to meet the requirements of advanced Fully Depleted Silicon On Insulator (FD-SOI) nodes. The implementation and control of in-situ doped epitaxy while optimizing the dopant diffusion close to the channel is crucial for these architectures. However, few studies have been performed concerning the impact of Rapid Thermal Annealing (RTA) on in-situ doped epitaxial layers for junction optimization. Tensile-strained Si:P (t-Si:P) selective epitaxial growth is being developed for nMOS devices. We evaluate here the impact of temperature and annealing duration on electrical resistivity and diffusion length of P in such t-Si:P layers. We show that the diffusion length can be tuned by selecting the right thermal budget. The diffusion coefficient is otherwise reduced in our in-situ doped samples compared to that in ion implanted ones. Despite a slight tensile strain decrease, maybe due to SixPy cluster dissolution, the t–Si:P resistivity decreased after thermal annealing compared to that just after epitaxy. A right balance between tensile strain preservation and dopant activation was found. We finally evidenced that the active carrier concentration after RTA was in line with the dopant solubility at a given temperature. Higher temperature and shorter anneals might give access to even lower resistivities. The proposed annealing strategy paves the way for the integration of highly doped t-Si:P layers (> $10^{21}$ at/cm3) in the source/drain regions of nMOSFET device.
{"title":"Diffusion Analysis and Impact of RTA on Strained Phosphorous-Doped Si for Advanced SOI Nodes","authors":"Theo Cabaret;Eva Dos Reis;Valerie Lapras;Nicolas Gauthier;Joel Kanyandekwe","doi":"10.1109/JEDS.2025.3642939","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3642939","url":null,"abstract":"Improvement of source/drain regions is necessary to meet the requirements of advanced Fully Depleted Silicon On Insulator (FD-SOI) nodes. The implementation and control of in-situ doped epitaxy while optimizing the dopant diffusion close to the channel is crucial for these architectures. However, few studies have been performed concerning the impact of Rapid Thermal Annealing (RTA) on in-situ doped epitaxial layers for junction optimization. Tensile-strained Si:P (t-Si:P) selective epitaxial growth is being developed for nMOS devices. We evaluate here the impact of temperature and annealing duration on electrical resistivity and diffusion length of P in such t-Si:P layers. We show that the diffusion length can be tuned by selecting the right thermal budget. The diffusion coefficient is otherwise reduced in our in-situ doped samples compared to that in ion implanted ones. Despite a slight tensile strain decrease, maybe due to SixPy cluster dissolution, the t–Si:P resistivity decreased after thermal annealing compared to that just after epitaxy. A right balance between tensile strain preservation and dopant activation was found. We finally evidenced that the active carrier concentration after RTA was in line with the dopant solubility at a given temperature. Higher temperature and shorter anneals might give access to even lower resistivities. The proposed annealing strategy paves the way for the integration of highly doped t-Si:P layers (> <inline-formula> <tex-math>$10^{21}$ </tex-math></inline-formula> at/cm3) in the source/drain regions of nMOSFET device.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1306-1312"},"PeriodicalIF":2.4,"publicationDate":"2025-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11297741","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145886560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work investigates the reliability of AlScN/GaN High-Electron-Mobility Transistors (HEMTs) by integrating experimental analyzes with Technology Computer-Aided Design (TCAD) simulations. The study focuses on pulsed I-V measurements and High-Temperature Reverse Bias (HTRB) step-stress tests. The former have been performed under different quiescent conditions highlight short-term transient charge trapping, while the latter reveals long-term threshold voltage $(V_{mathrm {th}})$ , transconductance $(mathrm {gm})$ , saturation drain current $(I_{mathrm {D,ss}})$ and gate leakage $(I_{mathrm {G}})$ shifts. A TCAD model calibrated on experiments is employed to deeply understand the interplay of the different sources of degradation. In pulsed analyzes, iron traps are identified as the primary degradation contributors. In HTRB step-stress regime, trapped charges under the gate at the 2DEG interface are modeled to reproduce the $V_{mathrm {th}}$ shift, while the decreased gm is mostly ascribed to donor-trap detrapping at the SiN passivation interface. The relative $Delta I_{mathrm {D,ss}}[%]$ shift and $I_{mathrm {G}}$ are used to validate the proposed approach. Such insights also provide a net comparison of the degradation phenomena in AlScN-based HEMTs with respect to AlGaN-based counterparts, paving the way for improved technology and device designs.
{"title":"Reliability of AlScN/GaN HEMTs Under Pulsed Measurements and HTRB Step-Stress Tests: Experimental and TCAD Insights","authors":"Franco Ercolano;Luigi Balestra;Sebastian Krause;Stefano Leone;Isabel Streicher;Patrick Waltereit;Michael Dammann;Susanna Reggiani","doi":"10.1109/JEDS.2025.3641046","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3641046","url":null,"abstract":"This work investigates the reliability of AlScN/GaN High-Electron-Mobility Transistors (HEMTs) by integrating experimental analyzes with Technology Computer-Aided Design (TCAD) simulations. The study focuses on pulsed I-V measurements and High-Temperature Reverse Bias (HTRB) step-stress tests. The former have been performed under different quiescent conditions highlight short-term transient charge trapping, while the latter reveals long-term threshold voltage <inline-formula> <tex-math>$(V_{mathrm {th}})$ </tex-math></inline-formula>, transconductance <inline-formula> <tex-math>$(mathrm {gm})$ </tex-math></inline-formula>, saturation drain current <inline-formula> <tex-math>$(I_{mathrm {D,ss}})$ </tex-math></inline-formula> and gate leakage <inline-formula> <tex-math>$(I_{mathrm {G}})$ </tex-math></inline-formula> shifts. A TCAD model calibrated on experiments is employed to deeply understand the interplay of the different sources of degradation. In pulsed analyzes, iron traps are identified as the primary degradation contributors. In HTRB step-stress regime, trapped charges under the gate at the 2DEG interface are modeled to reproduce the <inline-formula> <tex-math>$V_{mathrm {th}}$ </tex-math></inline-formula> shift, while the decreased gm is mostly ascribed to donor-trap detrapping at the SiN passivation interface. The relative <inline-formula> <tex-math>$Delta I_{mathrm {D,ss}}[%]$ </tex-math></inline-formula> shift and <inline-formula> <tex-math>$I_{mathrm {G}}$ </tex-math></inline-formula> are used to validate the proposed approach. Such insights also provide a net comparison of the degradation phenomena in AlScN-based HEMTs with respect to AlGaN-based counterparts, paving the way for improved technology and device designs.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"1-9"},"PeriodicalIF":2.4,"publicationDate":"2025-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11282436","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01DOI: 10.1109/JEDS.2025.3638982
Pengyu Lai;Hui Wang;H. Alan Mantooth;Zhong Chen
This paper proposes and experimentally evaluates SiC laterally diffused metal-oxide-semiconductor (LDMOS) devices fabricated on two full 4H-SiC processes with P-type and N-type epitaxial layers. The devices were characterized from 25 °C to 300 °C in terms of turn-on resistance $(R_{on})$ , breakdown voltage (BV), input capacitance $(C_{iss})$ , and output capacitance $(C_{oss})$ . At 25 °C, $R_{on}$ ranges from 5 $Omega $ /mm2 to 10 $Omega $ /mm2 and BV spans 160 V to 315 V with the device parameter variations. The figure of merit (FOM, i.e., ~14 kW/mm2) is comparable to Si-based LDMOS at room temperature and remains stable up to 300 °C, whereas Si devices degrade rapidly above 150 °C. $C_{iss}$ and $C_{oss}$ of the SiC LDMOS are higher than those of their Si counterparts but exhibit little degradation with increasing temperature. These results demonstrate that the proposed SiC LDMOS devices provide promising performance and strong thermal stability, highlighting their potential for high-voltage and high-temperature integrated circuit applications.
{"title":"Development and Evaluation of SiC LDMOS for High-Temperature Applications","authors":"Pengyu Lai;Hui Wang;H. Alan Mantooth;Zhong Chen","doi":"10.1109/JEDS.2025.3638982","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3638982","url":null,"abstract":"This paper proposes and experimentally evaluates SiC laterally diffused metal-oxide-semiconductor (LDMOS) devices fabricated on two full 4H-SiC processes with P-type and N-type epitaxial layers. The devices were characterized from 25 °C to 300 °C in terms of turn-on resistance <inline-formula> <tex-math>$(R_{on})$ </tex-math></inline-formula>, breakdown voltage (BV), input capacitance <inline-formula> <tex-math>$(C_{iss})$ </tex-math></inline-formula>, and output capacitance <inline-formula> <tex-math>$(C_{oss})$ </tex-math></inline-formula>. At 25 °C, <inline-formula> <tex-math>$R_{on}$ </tex-math></inline-formula> ranges from 5 <inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>/mm2 to 10 <inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>/mm2 and BV spans 160 V to 315 V with the device parameter variations. The figure of merit (FOM, i.e., ~14 kW/mm2) is comparable to Si-based LDMOS at room temperature and remains stable up to 300 °C, whereas Si devices degrade rapidly above 150 °C. <inline-formula> <tex-math>$C_{iss}$ </tex-math></inline-formula> and <inline-formula> <tex-math>$C_{oss}$ </tex-math></inline-formula> of the SiC LDMOS are higher than those of their Si counterparts but exhibit little degradation with increasing temperature. These results demonstrate that the proposed SiC LDMOS devices provide promising performance and strong thermal stability, highlighting their potential for high-voltage and high-temperature integrated circuit applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"14 ","pages":"10-17"},"PeriodicalIF":2.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11271727","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-25DOI: 10.1109/JEDS.2025.3636591
Lucas Badeau;Nicolas Coudurier;Patrice Gergaud;Jean-Michel Hartmann;Vincent Reboud;Philippe Rodriguez
We have investigated Co / GeSn contacts as a promising alternative to the conventional Ni / GeSn system. While cobalt has been widely studied for silicide and germanide formation, its interaction with GeSn has not been probed yet. Using X-ray diffraction (XRD), we obtained the following phase formation sequence: cobalt was consumed at low temperatures to form CoGe near 300 °C, followed by the appearance of Co5Ge7 between 400-500 °C, and its transformation into stable CoGe2 at higher temperatures. Transient CoSnx compounds were also identified in the 350-500 °C range, likely linked to tin segregation above 350 °C. The electrical behavior of Co / n-doped Ge0.94Sn0.06 contacts was also characterized with an ohmic behavior from the as-deposited state up to 500 °C. Notably, low specific contact resistivity values were achieved, with $rho {}_{text {c}}$ as low as $8.8times 10^{-6}~Omega {}$ .cm2. Cobalt was thus shown to be a viable metallization candidate for n-doped GeSn films.
{"title":"Interfacial Reactions and Electrical Properties of Co / GeSn Contacts","authors":"Lucas Badeau;Nicolas Coudurier;Patrice Gergaud;Jean-Michel Hartmann;Vincent Reboud;Philippe Rodriguez","doi":"10.1109/JEDS.2025.3636591","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3636591","url":null,"abstract":"We have investigated Co / GeSn contacts as a promising alternative to the conventional Ni / GeSn system. While cobalt has been widely studied for silicide and germanide formation, its interaction with GeSn has not been probed yet. Using X-ray diffraction (XRD), we obtained the following phase formation sequence: cobalt was consumed at low temperatures to form CoGe near 300 °C, followed by the appearance of Co5Ge7 between 400-500 °C, and its transformation into stable CoGe2 at higher temperatures. Transient CoSnx compounds were also identified in the 350-500 °C range, likely linked to tin segregation above 350 °C. The electrical behavior of Co / n-doped Ge0.94Sn0.06 contacts was also characterized with an ohmic behavior from the as-deposited state up to 500 °C. Notably, low specific contact resistivity values were achieved, with <inline-formula> <tex-math>$rho {}_{text {c}}$ </tex-math></inline-formula> as low as <inline-formula> <tex-math>$8.8times 10^{-6}~Omega {}$ </tex-math></inline-formula>.cm2. Cobalt was thus shown to be a viable metallization candidate for n-doped GeSn films.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1299-1305"},"PeriodicalIF":2.4,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11267448","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：