Pub Date : 2024-10-01DOI: 10.1109/JEDS.2024.3471999
Eunseok Oh;Hyungcheol Shin
Random telegraph noise (RTN) shifts the threshold voltage (Vt) of 3D NAND flash memory cells, making it a key factor of the device malfunction. The aim of this study is to predict the distribution of RTN induced ${mathrm { V}}_{mathrm { t}}$ shift in 3D NAND flash memory. Artificial neural network (ANN)-based machine learning (ML) is used for this prediction. With 2000 samples, ANN is trained and tested to predict the ${mathrm { V}}_{mathrm { t}}$ shift of random cells with high reliability. Furthermore, ANN is applied to predict the tendency of RTN-induced ${mathrm { V}}_{mathrm { t}}$ shift in scaled 3D NAND. Compared to prior works which has required far more measurements or simulations, the predictions are shown to shorten the time spent to obtain the distribution. Based on these predictions, the dependency of the decay constant on cell variation is investigated, which is a most critical parameter in analyzing the RTN distribution. This indicates that it is possible to apply ANN-based ML to predict various characteristics of 3D NAND flash memory in a much shorter time and to develop numerical models of related parameters.
{"title":"Prediction of Random Telegraph Noise-Induced Threshold Voltage Shift and Its Scaling Dependency Using Machine Learning","authors":"Eunseok Oh;Hyungcheol Shin","doi":"10.1109/JEDS.2024.3471999","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3471999","url":null,"abstract":"Random telegraph noise (RTN) shifts the threshold voltage (Vt) of 3D NAND flash memory cells, making it a key factor of the device malfunction. The aim of this study is to predict the distribution of RTN induced \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { t}}$ </tex-math></inline-formula>\u0000 shift in 3D NAND flash memory. Artificial neural network (ANN)-based machine learning (ML) is used for this prediction. With 2000 samples, ANN is trained and tested to predict the \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { t}}$ </tex-math></inline-formula>\u0000 shift of random cells with high reliability. Furthermore, ANN is applied to predict the tendency of RTN-induced \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { t}}$ </tex-math></inline-formula>\u0000 shift in scaled 3D NAND. Compared to prior works which has required far more measurements or simulations, the predictions are shown to shorten the time spent to obtain the distribution. Based on these predictions, the dependency of the decay constant on cell variation is investigated, which is a most critical parameter in analyzing the RTN distribution. This indicates that it is possible to apply ANN-based ML to predict various characteristics of 3D NAND flash memory in a much shorter time and to develop numerical models of related parameters.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10702511","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-30DOI: 10.1109/JEDS.2024.3469917
Junha Suk;Yohan Kim;Jungho Do;Garoom Kim;Woojin Rim;Sanghoon Baek;Seiseung Yoon;Soyoung Kim
In this paper, we propose a process-aware analytical gate resistance model for nanosheet field-effect transistors (NSFETs). The proposed NSFET gate resistance is modeled by applying the distributed resistance coefficient, which can be used when current flows vertically and horizontally. By predicting the direction of current flow, the resistance components are approximated in series with parallel connection of divided segments. The proposed model can reflect changes in structural parameters, making it possible to predict the scaling trend of NSFETs. This is validated through TCAD simulation results. The proposed model can be implemented in general compact models such as the Berkeley short channel IGFET model (BSIM)-common multi-gate (CMG) and can be used to predict circuit performance more accurately.
{"title":"A Process-Aware Analytical Gate Resistance Model for Nanosheet Field-Effect Transistors","authors":"Junha Suk;Yohan Kim;Jungho Do;Garoom Kim;Woojin Rim;Sanghoon Baek;Seiseung Yoon;Soyoung Kim","doi":"10.1109/JEDS.2024.3469917","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3469917","url":null,"abstract":"In this paper, we propose a process-aware analytical gate resistance model for nanosheet field-effect transistors (NSFETs). The proposed NSFET gate resistance is modeled by applying the distributed resistance coefficient, which can be used when current flows vertically and horizontally. By predicting the direction of current flow, the resistance components are approximated in series with parallel connection of divided segments. The proposed model can reflect changes in structural parameters, making it possible to predict the scaling trend of NSFETs. This is validated through TCAD simulation results. The proposed model can be implemented in general compact models such as the Berkeley short channel IGFET model (BSIM)-common multi-gate (CMG) and can be used to predict circuit performance more accurately.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10699326","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142408862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-27DOI: 10.1109/JEDS.2024.3469398
Nalin Vilochan Mishra;Aditya Sankar Medury
The ability of Ultra-Thin-Body (UTB) MOS devices to enable channel length scaling can only be realistically assessed by accurately taking key physical effects such as Quantum Confinement effects (QCEs) and Short channel effects (SCEs) into account. QCEs can accurately be considered only through a full band structure-based approach, which tends to be computationally inefficient, particularly at higher channel thicknesses, and is further exacerbated when required to be used to calculate 2-D channel electrostatics. Therefore, in this work, we propose a methodology to efficiently simulate the channel electrostatics of a UTB Double Gate MOSFET by solving the 1-D band structure with the 2-D Poisson’s equation self consistently, determined by using the $sp^{3}d^{5}s^{*}$ semi-empirical tight-binding approach only over those k-points that are likely to have a significant effect on the electrostatics. By showing that determining the 1-D Band structure at the source-channel junction is adequate to accurately determine the 2-D channel electrostatics, we show that this approach remains computationally tractable even at higher channel lengths. By following this approach, we obtain the 2-D profile of important device parameters such as electron density and channel potential, which, in turn, enables the determination of the thermionic current density and source-to-drain tunneling current density for a wide range of device parameters using Tsu-Esaki and WKB formalism respectively. Furthermore, the effect of phonon scattering, which is likely to manifest at longer channel lengths, is also incorporated in the drain current calculation, thus making this approach widely applicable.
{"title":"Computationally Efficient Band Structure-Based Approach for Accurately Determining Electrostatics and Source-to-Drain Tunneling Current in UTB MOSFETs","authors":"Nalin Vilochan Mishra;Aditya Sankar Medury","doi":"10.1109/JEDS.2024.3469398","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3469398","url":null,"abstract":"The ability of Ultra-Thin-Body (UTB) MOS devices to enable channel length scaling can only be realistically assessed by accurately taking key physical effects such as Quantum Confinement effects (QCEs) and Short channel effects (SCEs) into account. QCEs can accurately be considered only through a full band structure-based approach, which tends to be computationally inefficient, particularly at higher channel thicknesses, and is further exacerbated when required to be used to calculate 2-D channel electrostatics. Therefore, in this work, we propose a methodology to efficiently simulate the channel electrostatics of a UTB Double Gate MOSFET by solving the 1-D band structure with the 2-D Poisson’s equation self consistently, determined by using the \u0000<inline-formula> <tex-math>$sp^{3}d^{5}s^{*}$ </tex-math></inline-formula>\u0000 semi-empirical tight-binding approach only over those k-points that are likely to have a significant effect on the electrostatics. By showing that determining the 1-D Band structure at the source-channel junction is adequate to accurately determine the 2-D channel electrostatics, we show that this approach remains computationally tractable even at higher channel lengths. By following this approach, we obtain the 2-D profile of important device parameters such as electron density and channel potential, which, in turn, enables the determination of the thermionic current density and source-to-drain tunneling current density for a wide range of device parameters using Tsu-Esaki and WKB formalism respectively. Furthermore, the effect of phonon scattering, which is likely to manifest at longer channel lengths, is also incorporated in the drain current calculation, thus making this approach widely applicable.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10697110","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142383489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-26DOI: 10.1109/JEDS.2024.3468300
Jinyeong Lee;Jaewook Jeong
In this paper, the photoluminescence characteristics of solution-processed amorphous ZnO and related compounds of InZnO and GaZnO thin films were comparatively analyzed. Depending on the molarity of the precursor solution, PL emission peaks ranging from 382.4 nm to 384.8 nm were observed for the ZnO thin films. The PL emission peaks were closely related to the surface morphology of the thin films, which were clearly observed when isolated, nano-sized particles of quantum dot structure were present, leading to quantum confinement effect in the ZnO and GaZnO thin films. When uniform thin films formed, the PL emission peaks disappeared due to the increase of electrical and morphological connectivity, which reveals that the analysis of PL emission peak can be used to evaluate the film quality and the performance of thin-film transistors (TFTs) in solution-processed oxide-based materials.
{"title":"Correlation Between Quantum Confinement Effect and Characteristics of Thin-Film Transistors in Solution-Processed Oxide-Based Thin-Films","authors":"Jinyeong Lee;Jaewook Jeong","doi":"10.1109/JEDS.2024.3468300","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3468300","url":null,"abstract":"In this paper, the photoluminescence characteristics of solution-processed amorphous ZnO and related compounds of InZnO and GaZnO thin films were comparatively analyzed. Depending on the molarity of the precursor solution, PL emission peaks ranging from 382.4 nm to 384.8 nm were observed for the ZnO thin films. The PL emission peaks were closely related to the surface morphology of the thin films, which were clearly observed when isolated, nano-sized particles of quantum dot structure were present, leading to quantum confinement effect in the ZnO and GaZnO thin films. When uniform thin films formed, the PL emission peaks disappeared due to the increase of electrical and morphological connectivity, which reveals that the analysis of PL emission peak can be used to evaluate the film quality and the performance of thin-film transistors (TFTs) in solution-processed oxide-based materials.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10695762","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142442957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The device performance of indium zinc oxide (IZO) thin-film transistors (TFTs) is optimized through process optimizations. By jointly adjusting the annealing condition, the channel thickness and the sputtering atmosphere, the roughness and oxygen vacancies (Vos) are precisely regulated. The optimized IZO TFTs can achieve the highest field effect mobility of ~71.8 cm2/Vs with a threshold voltage of ~-0.6 V. Reliability of IZO TFTs under positive/negative bias stress is also examined. The interface quality and the Vo are two key factors influencing the device performance and reliability, confirmed by X-ray photoelectron spectroscopy and atomic force microscopy analysis.
{"title":"Performance Enhancement of Indium Zinc Oxide Thin-Film Transistors Through Process Optimizations","authors":"Mingjun Zhang;Jinyang Huang;Zihan Wang;Paramasivam Balasubramanian;Yan Yan;Ye Zhou;Su-Ting Han;Lei Lu;Meng Zhang","doi":"10.1109/JEDS.2024.3466956","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3466956","url":null,"abstract":"The device performance of indium zinc oxide (IZO) thin-film transistors (TFTs) is optimized through process optimizations. By jointly adjusting the annealing condition, the channel thickness and the sputtering atmosphere, the roughness and oxygen vacancies (Vos) are precisely regulated. The optimized IZO TFTs can achieve the highest field effect mobility of ~71.8 cm2/Vs with a threshold voltage of ~-0.6 V. Reliability of IZO TFTs under positive/negative bias stress is also examined. The interface quality and the Vo are two key factors influencing the device performance and reliability, confirmed by X-ray photoelectron spectroscopy and atomic force microscopy analysis.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10690260","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142383447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
One-dimensionalcarbon nanotube field-effect transistors (CNFETs) have offered a solution for obtaining high transistor performance in a compatible low-temperature BEOL process, enabling monolithic 3D integration benefits for more functional circuits. Currently, CNT transistors need to further improve their performance with a more stable process and explore the most suitable circuit application scene. In this study, we successfully enhanced the performance of CNFETs through special Y2O3 film passivation and vacuum annealing processes. The on-state current of the optimized device was improved by $36.6times $ compared to the device without these processes. Besides, the subthreshold swing (SS) was notably reduced from 259 mV/dec to 215 mV/dec and the threshold voltage was decreased from 2.02 V to 1.79 V due to the reduction of the interface state. Meanwhile, the devices’ optoelectronic characteristics were significantly improved and exhibited a $72times $ increase in $Delta $ Ids under identical illumination. With an improved annealing process, the $Delta $ Ids were further increased to $231times $ compared to the original device because of the reduction of defects within the device. Finally, the tentative Morse code communication applications all by the optimized CNFETs were obtained. These technologies and functional implementations provided a promising approach for future 3D functional communication systems with CNT technology.
{"title":"High-Performance Carbon Nanotube Optoelectronic Transistor With Optimized Process for 3D Communication Circuit Applications","authors":"Shuang Liu;Heyi Huang;Yanqing Li;Yadong Zhang;Feixiong Wang;Zhaohao Zhang;Qingzhu Zhang;Jiali Huo;Jiaxin Yao;Jing Wen;Huaxiang Yin","doi":"10.1109/JEDS.2024.3465669","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3465669","url":null,"abstract":"One-dimensionalcarbon nanotube field-effect transistors (CNFETs) have offered a solution for obtaining high transistor performance in a compatible low-temperature BEOL process, enabling monolithic 3D integration benefits for more functional circuits. Currently, CNT transistors need to further improve their performance with a more stable process and explore the most suitable circuit application scene. In this study, we successfully enhanced the performance of CNFETs through special Y2O3 film passivation and vacuum annealing processes. The on-state current of the optimized device was improved by \u0000<inline-formula> <tex-math>$36.6times $ </tex-math></inline-formula>\u0000 compared to the device without these processes. Besides, the subthreshold swing (SS) was notably reduced from 259 mV/dec to 215 mV/dec and the threshold voltage was decreased from 2.02 V to 1.79 V due to the reduction of the interface state. Meanwhile, the devices’ optoelectronic characteristics were significantly improved and exhibited a \u0000<inline-formula> <tex-math>$72times $ </tex-math></inline-formula>\u0000 increase in \u0000<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>\u0000 Ids under identical illumination. With an improved annealing process, the \u0000<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>\u0000 Ids were further increased to \u0000<inline-formula> <tex-math>$231times $ </tex-math></inline-formula>\u0000 compared to the original device because of the reduction of defects within the device. Finally, the tentative Morse code communication applications all by the optimized CNFETs were obtained. These technologies and functional implementations provided a promising approach for future 3D functional communication systems with CNT technology.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10685345","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142408907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-23DOI: 10.1109/JEDS.2024.3465594
Su Yeon Jung;Hyunwoo Kim;Jongmin Lee;Jang Hyun Kim
We analyzed the impact of work-function variation (WFV) in ferroelectric field-effect transistor (FeFET). To analyze the operation characteristics, we employed the technology computer-aided design (TCAD) simulations. After evaluating ferroelectricity (FE) characteristics and optimizing device model parameters through calibration, we extracted five key parameters from the hysteretic transfer curves of the FeFET: threshold voltage (Vth), on current (Iin), subthreshold swing (SS), off current (Ioff), and gate-induced drain leakage (GIDL). The extracted parameters were compared based on the presence or absence of FE and the ferroelectric thickness. It was confirmed that the presence of FE leads to increased variation due to dipole alignment with WFV, and that the electric field is maintained even with an increase in ferroelectric thickness
我们分析了铁电场效应晶体管（FeFET）中功函数变化（WFV）的影响。为了分析工作特性，我们采用了技术计算机辅助设计（TCAD）模拟。在评估了铁电（FE）特性并通过校准优化了器件模型参数后，我们从铁电场效应晶体管的滞后转移曲线中提取了五个关键参数：阈值电压（Vth）、导通电流（Iin）、亚阈值摆动（SS）、关断电流（Ioff）和栅极诱导漏极泄漏（GIDL）。根据是否存在 FE 和铁电厚度对提取的参数进行了比较。结果证实，FE 的存在会导致偶极对齐与 WFV 的变化增加，而且即使铁电厚度增加，电场也会保持不变。
{"title":"Impact of Work-Function Variation in Ferroelectric Field-Effect Transistor","authors":"Su Yeon Jung;Hyunwoo Kim;Jongmin Lee;Jang Hyun Kim","doi":"10.1109/JEDS.2024.3465594","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3465594","url":null,"abstract":"We analyzed the impact of work-function variation (WFV) in ferroelectric field-effect transistor (FeFET). To analyze the operation characteristics, we employed the technology computer-aided design (TCAD) simulations. After evaluating ferroelectricity (FE) characteristics and optimizing device model parameters through calibration, we extracted five key parameters from the hysteretic transfer curves of the FeFET: threshold voltage (Vth), on current (Iin), subthreshold swing (SS), off current (Ioff), and gate-induced drain leakage (GIDL). The extracted parameters were compared based on the presence or absence of FE and the ferroelectric thickness. It was confirmed that the presence of FE leads to increased variation due to dipole alignment with WFV, and that the electric field is maintained even with an increase in ferroelectric thickness","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10685408","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142359756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-18DOI: 10.1109/JEDS.2024.3462930
S. Ohmi;M. Tanuma;J.W. Shin
In this work, we have investigated the conductance control of the metal-ferroelectrics-Si field-effect transistor (MFSFET) utilizing 5 nm thick ferroelectric nondoped $rm HfO_{2}$ (FeND-HfO2) gate insulator. The Kr-plasma process is effective to decrease the plasma damage compared to the Ar-plasma process during the in-situ deposition of FeND-HfO2 and Pt gate electrode by RF-magnetron sputtering. The precise control such as less than 20 mV was realized which led to the conductance control for 10 states from 0 to $0.6~mu $ S/ $mu $ m both for potentiation and depression operations with the input pulses of $mathbf {pm 3}$ V/100 ns.
{"title":"Kr-Plasma Process for Conductance Control of MFSFET With FeND-HfO₂ Gate Insulator","authors":"S. Ohmi;M. Tanuma;J.W. Shin","doi":"10.1109/JEDS.2024.3462930","DOIUrl":"10.1109/JEDS.2024.3462930","url":null,"abstract":"In this work, we have investigated the conductance control of the metal-ferroelectrics-Si field-effect transistor (MFSFET) utilizing 5 nm thick ferroelectric nondoped \u0000<inline-formula> <tex-math>$rm HfO_{2}$ </tex-math></inline-formula>\u0000 (FeND-HfO2) gate insulator. The Kr-plasma process is effective to decrease the plasma damage compared to the Ar-plasma process during the in-situ deposition of FeND-HfO2 and Pt gate electrode by RF-magnetron sputtering. The precise control such as less than 20 mV was realized which led to the conductance control for 10 states from 0 to \u0000<inline-formula> <tex-math>$0.6~mu $ </tex-math></inline-formula>\u0000S/\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m both for potentiation and depression operations with the input pulses of \u0000<inline-formula> <tex-math>$mathbf {pm 3}$ </tex-math></inline-formula>\u0000 V/100 ns.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10682993","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142253406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-17DOI: 10.1109/JEDS.2024.3462590
Wei-Cheng Wang;Ming-Dou Ker
When more circuit functions are integrated into a single chip fabricated by the GaN-on-Silicon process, the need for on-chip electrostatic discharge (ESD) protection design becomes crucial to safeguard GaN integrated circuits (ICs). In this work, the power-rail ESD clamp circuit with gate-coupled design, fabricated in a GaN-on-Silicon process, was investigated. By increasing the gate-coupled capacitance, ESD level of the power-rail ESD clamp circuit can be significantly improved. However, the increased capacitance induces transient leakage current during normal power-on operation. To overcome this issue, a new detection circuit was proposed, which can differentiate between the ESD event and the normal power-on transient operation. Therefore, incorporating this new proposed detection circuit with the gate-coupled design allows for good ESD robustness, while also preventing transient leakage current during normal power-on condition.
{"title":"Fully Integrated GaN-on-Silicon Power-Rail ESD Clamp Circuit Without Transient Leakage Current During Normal Power-on Operation","authors":"Wei-Cheng Wang;Ming-Dou Ker","doi":"10.1109/JEDS.2024.3462590","DOIUrl":"10.1109/JEDS.2024.3462590","url":null,"abstract":"When more circuit functions are integrated into a single chip fabricated by the GaN-on-Silicon process, the need for on-chip electrostatic discharge (ESD) protection design becomes crucial to safeguard GaN integrated circuits (ICs). In this work, the power-rail ESD clamp circuit with gate-coupled design, fabricated in a GaN-on-Silicon process, was investigated. By increasing the gate-coupled capacitance, ESD level of the power-rail ESD clamp circuit can be significantly improved. However, the increased capacitance induces transient leakage current during normal power-on operation. To overcome this issue, a new detection circuit was proposed, which can differentiate between the ESD event and the normal power-on transient operation. Therefore, incorporating this new proposed detection circuit with the gate-coupled design allows for good ESD robustness, while also preventing transient leakage current during normal power-on condition.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10681588","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142253407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-16DOI: 10.1109/JEDS.2024.3461169
Ahmad Khusro;Saddam Husain;Mohammad S. Hashmi
This paper uses the Adaptive Neuro-Fuzzy Inference System (ANFIS) to investigate and propose a new alternative behavioral modeling technique for microwave power transistors. Utilizing measured I-V characteristics, associated parameters like transconductance $(g_{text {m}})$ and output conductance $(g_{text {ds}})$ , etc., S-parameters characteristics, and RF performance parameters such as unity current gain frequency $(f_{text {T}})$ , maximum unilateral gain frequency $(f_{max })$ , ANFIS-based behavioral models are developed for Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) and validated. The models have been developed using two distinct devices with dimensions of $10times 200~mu m$ and $10times 250~mu m$ for multi-bias conditions and over a broad frequency range (0.5 to 43.5 GHz). Subsequently, the proposed model performance is validated on devices with geometries of $10times 220~mu m$ , $4times 100~mu m$ , and $2times 200~mu m$ to examine the interpolation accuracy, extrapolation potential, and scalability. Here, ANFIS utilizes the subtractive clustering method to process the measurement characteristics by computing the clusters and opts for the best-performing model using error and number of fuzzy rules as criteria. The parameters involved in the fuzzy representation are trained using neural network algorithms, namely gradient-descent and least squares estimate. The proposed models are subsequently incorporated in a commercial circuit simulator (Keysight’s ADS) and the class-F power amplifier’s gain and stability characteristics are computed and studied.
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