Pub Date : 2025-01-30DOI: 10.1109/JEDS.2025.3528209
{"title":"Exploration of the exciting world of multifunctional oxide-based electronic devices: from material to system-level applications","authors":"","doi":"10.1109/JEDS.2025.3528209","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3528209","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1072-1073"},"PeriodicalIF":2.0,"publicationDate":"2025-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10858463","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Semiconducting single-walled carbon nanotubes (SWCNTs) have stimulated tremendous research interest in high performance electronics thanks to their impressive mechanical and electronic properties. However, it is still challenging to prepare wafer-scale SWCNTs thin films and fine-tunable device performance. Here, layer-by-layer (LbL) assembly is presented as an effective approach to prepare multilayer SWCNT thin films by coordinating poly(diallyldimethylammonium chloride) (PDDA) with SWCNTs. The thickness of SWCNTs thin film is linearly dependent on the bilayer numbers. Thin film transistors (TFTs) fabricated from SWCNTs thin films showed prominent device performance with a mobility of $rm 15.3 cm_{2} cdot V_{1}cdot s_{1}$ . Further the molecular dopants bis (trifluoromethane) sulfonimide (TFSI), with strong electro-withdrawing capability and protonating nature, was utilized to functionalize SWCNTs thin films, thereby regulating their electronic performances. The TFSI surface functionalization can remove excess electrons from SWCNT thin films, resulting in improved on-state current, increased carrier mobility and positively shifted threshold voltage. The molecular doping holds great promise for the future realization of large-area, low-power logic circuits and high-performance electronics.
{"title":"Self-Assembled Multilayer Single-Walled Carbon Nanotube Thin Film Transistors and Doping Regulation","authors":"Xiangxiang Gao;Zhenhua Lin;Jincheng Zhang;Yue Hao;Jingjing Chang","doi":"10.1109/JEDS.2025.3532593","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3532593","url":null,"abstract":"Semiconducting single-walled carbon nanotubes (SWCNTs) have stimulated tremendous research interest in high performance electronics thanks to their impressive mechanical and electronic properties. However, it is still challenging to prepare wafer-scale SWCNTs thin films and fine-tunable device performance. Here, layer-by-layer (LbL) assembly is presented as an effective approach to prepare multilayer SWCNT thin films by coordinating poly(diallyldimethylammonium chloride) (PDDA) with SWCNTs. The thickness of SWCNTs thin film is linearly dependent on the bilayer numbers. Thin film transistors (TFTs) fabricated from SWCNTs thin films showed prominent device performance with a mobility of <inline-formula> <tex-math>$rm 15.3 cm_{2} cdot V_{1}cdot s_{1}$ </tex-math></inline-formula>. Further the molecular dopants bis (trifluoromethane) sulfonimide (TFSI), with strong electro-withdrawing capability and protonating nature, was utilized to functionalize SWCNTs thin films, thereby regulating their electronic performances. The TFSI surface functionalization can remove excess electrons from SWCNT thin films, resulting in improved on-state current, increased carrier mobility and positively shifted threshold voltage. The molecular doping holds great promise for the future realization of large-area, low-power logic circuits and high-performance electronics.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"93-97"},"PeriodicalIF":2.0,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10849582","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143361064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As gate-all-around nanosheet transistors (GAA NSFETs) replacing current FinFETs for their superior gate control capabilities, it needs various performance optimizations for better transistor and circuit benefits. In this paper, special optimizations to source/drain (S/D) doping engineering including spacer bottom footing (SBF) and refining the lightly doped drain (LDD) implantation process are explored to enhance both fabricated complementary metal oxide semiconductor (CMOS) NSFETs and their 6T-SRAM cells. The experimental results demonstrate that the optimal SBF width increased the static noise margin (SNM) of the SRAM cells by 14.9%, while significantly reducing static power consumption for the balance performance between the NMOS and PMOS and reduced current in all leakage paths of SRAM. Moreover, the LDD optimization significantly reduced off-state leakage current ($rm I_{mathrm {off}}$ ) for both NMOS and PMOS due to the reductions of peak electric field in overlap region between the S/D and the channel, leading to a 9.5% improvement in SNM and a substantial reduction in static power consumption. These results indicate that the optimization to S/D doping engineering may achieve substantial performance gains in both the GAA CMOS transistors and the SRAM cells.
{"title":"Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells via Source/Drain Doping Engineering","authors":"Xuexiang Zhang;Qingkun Li;Lei Cao;Qingzhu Zhang;Renjie Jiang;Peng Wang;Jiaxin Yao;Huaxiang Yin","doi":"10.1109/JEDS.2025.3531432","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3531432","url":null,"abstract":"As gate-all-around nanosheet transistors (GAA NSFETs) replacing current FinFETs for their superior gate control capabilities, it needs various performance optimizations for better transistor and circuit benefits. In this paper, special optimizations to source/drain (S/D) doping engineering including spacer bottom footing (SBF) and refining the lightly doped drain (LDD) implantation process are explored to enhance both fabricated complementary metal oxide semiconductor (CMOS) NSFETs and their 6T-SRAM cells. The experimental results demonstrate that the optimal SBF width increased the static noise margin (SNM) of the SRAM cells by 14.9%, while significantly reducing static power consumption for the balance performance between the NMOS and PMOS and reduced current in all leakage paths of SRAM. Moreover, the LDD optimization significantly reduced off-state leakage current (<inline-formula> <tex-math>$rm I_{mathrm {off}}$ </tex-math></inline-formula>) for both NMOS and PMOS due to the reductions of peak electric field in overlap region between the S/D and the channel, leading to a 9.5% improvement in SNM and a substantial reduction in static power consumption. These results indicate that the optimization to S/D doping engineering may achieve substantial performance gains in both the GAA CMOS transistors and the SRAM cells.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"86-92"},"PeriodicalIF":2.0,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10845751","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We examined the fabrication and the operation of GeSn/GeSiSn resonant tunneling diode (RTD) and demonstrated the observation of negative differential resistance (NDR) at a low temperature through the hole resonant tunneling. First, we revealed the possible designed contents of GeSiSn to Si and Sn of 40–60% and ∼10%, respectively to achieve the valence band offset over 0.3 eV with sustaining the biaxial strain value less than 1.0%, which is an important factor for the pseudomorphic growth of GeSn/GeSiSn heterostructure on Ge. Then, we successfully fabricated GeSn/GeSiSn RTD with a double barrier structure composed of ultra-thin GeSiSn barriers and GeSn well, which has the steep heterointerface. The current-density–voltage (J–V) characteristics at 10 K of the fabricated GeSn/GeSiSn RTD showed NDRs at applied voltages of approximately −1.5 and −1.8 V with peak to valley current ratio of 1.06 and 1.14, respectively, and peak current density of ∼3 and ∼5 kA/cm2, respectively. We also demonstrated that the observed NDR is reproducible. The quantum level and J–V simulations suggests that these two NDRs would originate from the hole resonant tunneling current through the first and second quantum levels formed in the GeSn well layer. Furthermore, we also discussed issues newly found in this study and future remarks of GeSn/GeSiSn heterostructures as RTD applications for the terahertz oscillator and the nonvolatile RAM.
{"title":"Emergence of Negative Differential Resistance Through Hole Resonant Tunneling in GeSn/GeSiSn Double Barrier Structure","authors":"Shigehisa Shibayama;Shuto Ishimoto;Yoshiki Kato;Mitsuo Sakashita;Masashi Kurosawa;Osamu Nakatsuka","doi":"10.1109/JEDS.2025.3529079","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3529079","url":null,"abstract":"We examined the fabrication and the operation of GeSn/GeSiSn resonant tunneling diode (RTD) and demonstrated the observation of negative differential resistance (NDR) at a low temperature through the hole resonant tunneling. First, we revealed the possible designed contents of GeSiSn to Si and Sn of 40–60% and ∼10%, respectively to achieve the valence band offset over 0.3 eV with sustaining the biaxial strain value less than 1.0%, which is an important factor for the pseudomorphic growth of GeSn/GeSiSn heterostructure on Ge. Then, we successfully fabricated GeSn/GeSiSn RTD with a double barrier structure composed of ultra-thin GeSiSn barriers and GeSn well, which has the steep heterointerface. The current-density–voltage (J–V) characteristics at 10 K of the fabricated GeSn/GeSiSn RTD showed NDRs at applied voltages of approximately −1.5 and −1.8 V with peak to valley current ratio of 1.06 and 1.14, respectively, and peak current density of ∼3 and ∼5 kA/cm2, respectively. We also demonstrated that the observed NDR is reproducible. The quantum level and J–V simulations suggests that these two NDRs would originate from the hole resonant tunneling current through the first and second quantum levels formed in the GeSn well layer. Furthermore, we also discussed issues newly found in this study and future remarks of GeSn/GeSiSn heterostructures as RTD applications for the terahertz oscillator and the nonvolatile RAM.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"79-85"},"PeriodicalIF":2.0,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10839296","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-10DOI: 10.1109/JEDS.2025.3528073
Yue Zhao;Lihua Xu;Chuanke Chen;Xufan Li;Kexin Shang;Di Geng;Lingfei Wang;Ling Li
Threshold control of amorphous In-Ga-Zn-O field-effect transistor (a-IGZO FET) is generally a critical issue through material composition adjustment. Instead, this work reports a cylindrical vertical double-surrounding-gate (DSG) a-IGZO FET, featuring flexibility of threshold modulation, by the 3-D technology computer-aided design (TCAD) simulation. Firstly, physics-based parameters are calibrated to single-gated vertical transistor experiments. Thereafter, the performance is simulated by sweeping inner gate (G1) bias voltages under the various outer gate (G2) voltages, indicating the ability of threshold modulation. Length-scaling and position-variation of $G_{2}$ significantly impact the transistor performance metrics. For in-depth understanding of dimensional dependence, the surface potential of the channel and the electric field distribution near electrode are systematically investigated for an ultra-thin outer gate electrode, via considering spatial and geometric effects. These results will boost a design technology co-optimization flow of the future DSG-a-IGZO-FET-based extremely large-scale and high-density M3D memory.
{"title":"TCAD Simulation Study of Cylindrical Vertical Double-Surrounding-Gate a-InGaZnO FETs and Geometric Parameter Optimization","authors":"Yue Zhao;Lihua Xu;Chuanke Chen;Xufan Li;Kexin Shang;Di Geng;Lingfei Wang;Ling Li","doi":"10.1109/JEDS.2025.3528073","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3528073","url":null,"abstract":"Threshold control of amorphous In-Ga-Zn-O field-effect transistor (a-IGZO FET) is generally a critical issue through material composition adjustment. Instead, this work reports a cylindrical vertical double-surrounding-gate (DSG) a-IGZO FET, featuring flexibility of threshold modulation, by the 3-D technology computer-aided design (TCAD) simulation. Firstly, physics-based parameters are calibrated to single-gated vertical transistor experiments. Thereafter, the performance is simulated by sweeping inner gate (G1) bias voltages under the various outer gate (G2) voltages, indicating the ability of threshold modulation. Length-scaling and position-variation of <inline-formula> <tex-math>$G_{2}$ </tex-math></inline-formula> significantly impact the transistor performance metrics. For in-depth understanding of dimensional dependence, the surface potential of the channel and the electric field distribution near electrode are systematically investigated for an ultra-thin outer gate electrode, via considering spatial and geometric effects. These results will boost a design technology co-optimization flow of the future DSG-a-IGZO-FET-based extremely large-scale and high-density M3D memory.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"66-72"},"PeriodicalIF":2.0,"publicationDate":"2025-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10836807","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
High-electron mobility transistors (HEMTs) employing AlGaN/GaN heterostructures are suitable for high-power and high-frequency applications. To meet target specifications, GaN HEMTs must be designed and optimized by accurately considering the coupling of electrical and thermal characteristics, from the static to the pulsed regimes of operation. Toward this, we implement an electro-thermal modeling and simulation framework for experimentally fabricated GaN on SiC HEMTs and use the framework to predict the high-temperature performance of the technology, up to 448 K. We utilize the transient measurement data at different ambient temperatures to extract the trap characteristics, which are important to understand from the RF dispersion perspective. Our work highlights the significance of the thermal boundary conditions at the source, drain, and gate metal electrodes and the impact of heat dissipation paths on the lattice temperature rise and I-V characteristics. Overall, our work provides a physical insight into the thermal response of GaN HEMTs and can facilitate suitable thermal management strategies of the device over a broad range of DC and transient operating conditions.
{"title":"An Accurate Electrical and Thermal Co-Simulation Framework for Modeling High-Temperature DC and Pulsed I - V Characteristics of GaN HEMTs","authors":"Yicong Dong;Eiji Yagyu;Takashi Matsuda;Koon Hoo Teo;Chungwei Lin;Shaloo Rakheja","doi":"10.1109/JEDS.2025.3528307","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3528307","url":null,"abstract":"High-electron mobility transistors (HEMTs) employing AlGaN/GaN heterostructures are suitable for high-power and high-frequency applications. To meet target specifications, GaN HEMTs must be designed and optimized by accurately considering the coupling of electrical and thermal characteristics, from the static to the pulsed regimes of operation. Toward this, we implement an electro-thermal modeling and simulation framework for experimentally fabricated GaN on SiC HEMTs and use the framework to predict the high-temperature performance of the technology, up to 448 K. We utilize the transient measurement data at different ambient temperatures to extract the trap characteristics, which are important to understand from the RF dispersion perspective. Our work highlights the significance of the thermal boundary conditions at the source, drain, and gate metal electrodes and the impact of heat dissipation paths on the lattice temperature rise and I-V characteristics. Overall, our work provides a physical insight into the thermal response of GaN HEMTs and can facilitate suitable thermal management strategies of the device over a broad range of DC and transient operating conditions.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"54-65"},"PeriodicalIF":2.0,"publicationDate":"2025-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10836823","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-07DOI: 10.1109/JEDS.2024.3489072
{"title":"Call for Nominations for Editor-in-Chief","authors":"","doi":"10.1109/JEDS.2024.3489072","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3489072","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"1076-1076"},"PeriodicalIF":2.0,"publicationDate":"2025-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10832123","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-07DOI: 10.1109/JEDS.2023.3348195
{"title":"IEEE ELECTRON DEVICES SOCIETY","authors":"","doi":"10.1109/JEDS.2023.3348195","DOIUrl":"https://doi.org/10.1109/JEDS.2023.3348195","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"C2-C2"},"PeriodicalIF":2.0,"publicationDate":"2025-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10832128","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142937956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-30DOI: 10.1109/JEDS.2024.3518273
Lluís F. Marsal;Arturo Escobosa;Benjamin Iñiguez;Fernando Guarín
{"title":"Foreword Special Issue on the 5th Latin American Electron Device Conference","authors":"Lluís F. Marsal;Arturo Escobosa;Benjamin Iñiguez;Fernando Guarín","doi":"10.1109/JEDS.2024.3518273","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3518273","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"1034-1036"},"PeriodicalIF":2.0,"publicationDate":"2024-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10818400","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142912417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-30DOI: 10.1109/JEDS.2024.3512073
{"title":"Golden List of Reviewers for 2024","authors":"","doi":"10.1109/JEDS.2024.3512073","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3512073","url":null,"abstract":"","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"1065-1069"},"PeriodicalIF":2.0,"publicationDate":"2024-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10818401","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142912523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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