Pub Date : 2025-11-25DOI: 10.1109/JEDS.2025.3636591
Lucas Badeau;Nicolas Coudurier;Patrice Gergaud;Jean-Michel Hartmann;Vincent Reboud;Philippe Rodriguez
We have investigated Co / GeSn contacts as a promising alternative to the conventional Ni / GeSn system. While cobalt has been widely studied for silicide and germanide formation, its interaction with GeSn has not been probed yet. Using X-ray diffraction (XRD), we obtained the following phase formation sequence: cobalt was consumed at low temperatures to form CoGe near 300 °C, followed by the appearance of Co5Ge7 between 400-500 °C, and its transformation into stable CoGe2 at higher temperatures. Transient CoSnx compounds were also identified in the 350-500 °C range, likely linked to tin segregation above 350 °C. The electrical behavior of Co / n-doped Ge0.94Sn0.06 contacts was also characterized with an ohmic behavior from the as-deposited state up to 500 °C. Notably, low specific contact resistivity values were achieved, with $rho {}_{text {c}}$ as low as $8.8times 10^{-6}~Omega {}$ .cm2. Cobalt was thus shown to be a viable metallization candidate for n-doped GeSn films.
{"title":"Interfacial Reactions and Electrical Properties of Co / GeSn Contacts","authors":"Lucas Badeau;Nicolas Coudurier;Patrice Gergaud;Jean-Michel Hartmann;Vincent Reboud;Philippe Rodriguez","doi":"10.1109/JEDS.2025.3636591","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3636591","url":null,"abstract":"We have investigated Co / GeSn contacts as a promising alternative to the conventional Ni / GeSn system. While cobalt has been widely studied for silicide and germanide formation, its interaction with GeSn has not been probed yet. Using X-ray diffraction (XRD), we obtained the following phase formation sequence: cobalt was consumed at low temperatures to form CoGe near 300 °C, followed by the appearance of Co5Ge7 between 400-500 °C, and its transformation into stable CoGe2 at higher temperatures. Transient CoSnx compounds were also identified in the 350-500 °C range, likely linked to tin segregation above 350 °C. The electrical behavior of Co / n-doped Ge0.94Sn0.06 contacts was also characterized with an ohmic behavior from the as-deposited state up to 500 °C. Notably, low specific contact resistivity values were achieved, with <inline-formula> <tex-math>$rho {}_{text {c}}$ </tex-math></inline-formula> as low as <inline-formula> <tex-math>$8.8times 10^{-6}~Omega {}$ </tex-math></inline-formula>.cm2. Cobalt was thus shown to be a viable metallization candidate for n-doped GeSn films.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1299-1305"},"PeriodicalIF":2.4,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11267448","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-14DOI: 10.1109/JEDS.2025.3632845
Jun-Hyeok Yim;Jinhyeok Pyo;Myeongsu Chae;Sangyeon Pak;Hyungtak Kim;Ho-Young Cha
This study reports the fabrication and characterization of a p-GaN/AlGaN/GaN heterostructure field-effect transistor (HFET) incorporating a boron nitride (BN) film. The BN film was deposited at room temperature via RF sputtering (RT-RF sputtering) onto a SiOx passivation layer. A dual-layer passivation scheme—comprising the SiOx layer and the room-temperature-deposited BN film—was proposed to enhance interface quality and improve the on-resistance characteristics. The RT-RF sputtering BN film was found to increase the 2DEG density at the AlGaN/GaN interface without degrading the overall device performance. As a result, the on-resistance was reduced by 30%.
{"title":"Improved On-Resistance Characteristics in P-GaN/AlGaN/GaN HEMTs via Sputtered Boron Nitride Dielectric Film","authors":"Jun-Hyeok Yim;Jinhyeok Pyo;Myeongsu Chae;Sangyeon Pak;Hyungtak Kim;Ho-Young Cha","doi":"10.1109/JEDS.2025.3632845","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3632845","url":null,"abstract":"This study reports the fabrication and characterization of a p-GaN/AlGaN/GaN heterostructure field-effect transistor (HFET) incorporating a boron nitride (BN) film. The BN film was deposited at room temperature via RF sputtering (RT-RF sputtering) onto a SiOx passivation layer. A dual-layer passivation scheme—comprising the SiOx layer and the room-temperature-deposited BN film—was proposed to enhance interface quality and improve the on-resistance characteristics. The RT-RF sputtering BN film was found to increase the 2DEG density at the AlGaN/GaN interface without degrading the overall device performance. As a result, the on-resistance was reduced by 30%.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1138-1143"},"PeriodicalIF":2.4,"publicationDate":"2025-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11248840","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145560725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Random telegraph noise (RTN) in 65 nm technology bulk CMOS devices was measured at both 300 K and 1.5 K, and the dependence of noise amplitude on gate voltage was analyzed. Considering the highly random nature of RTN, 1,024 devices of both nMOS and pMOS types were measured using addressable transistor arrays to obtain statistically meaningful results. It was confirmed that the single-trap RTN amplitude is in good agreement with the number-plus-correlated-mobility fluctuation model at both 1.5 K and 300 K for both device types. It is shown that, from the extracted model parameters, it is possible to gain information on trap location and single charge scattering behavior. The effects of series resistance on the model are also discussed.
{"title":"Gate Voltage Dependence of MOSFET Random Telegraph Noise Amplitude at Room and Cryogenic Temperatures","authors":"Kiyoshi Takeuchi;Tomoko Mizutani;Takuya Saraya;Hiroshi Oka;Takahiro Mori;Masaharu Kobayashi;Toshiro Hiramoto","doi":"10.1109/JEDS.2025.3632306","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3632306","url":null,"abstract":"Random telegraph noise (RTN) in 65 nm technology bulk CMOS devices was measured at both 300 K and 1.5 K, and the dependence of noise amplitude on gate voltage was analyzed. Considering the highly random nature of RTN, 1,024 devices of both nMOS and pMOS types were measured using addressable transistor arrays to obtain statistically meaningful results. It was confirmed that the single-trap RTN amplitude is in good agreement with the number-plus-correlated-mobility fluctuation model at both 1.5 K and 300 K for both device types. It is shown that, from the extracted model parameters, it is possible to gain information on trap location and single charge scattering behavior. The effects of series resistance on the model are also discussed.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1151-1157"},"PeriodicalIF":2.4,"publicationDate":"2025-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11245544","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145560724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We have developed a novel molecular-ion implantation technique and a molecular-ion-implanted silicon epitaxial wafer for highly sensitive CMOS image sensors. This implantation technique is characterized by the use of molecular-ions consisting of carbon, hydrogen, and fluorine. In this paper, we investigate the formation of CH2F+ molecular-ion beams and conduct a fundamental study on the implantation behavior of CH2F+ molecular-ions and the characteristics of CH2F+-implanted silicon epitaxial wafers. We expect that this technique can contribute to the mass production of highly sensitive CMOS image sensors.
{"title":"Novel Production Concept of CH2F-Molecular-Ion Implanted Si Epitaxial Wafer for Highly Sensitive 3-D-Stacked CMOS Image Sensors","authors":"Ryo Hirose;Koji Kobayashi;Kazunari Kurita;Takeshi Kadono;Sho Nagatomo","doi":"10.1109/JEDS.2025.3631002","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3631002","url":null,"abstract":"We have developed a novel molecular-ion implantation technique and a molecular-ion-implanted silicon epitaxial wafer for highly sensitive CMOS image sensors. This implantation technique is characterized by the use of molecular-ions consisting of carbon, hydrogen, and fluorine. In this paper, we investigate the formation of CH2F+ molecular-ion beams and conduct a fundamental study on the implantation behavior of CH2F+ molecular-ions and the characteristics of CH2F+-implanted silicon epitaxial wafers. We expect that this technique can contribute to the mass production of highly sensitive CMOS image sensors.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1276-1281"},"PeriodicalIF":2.4,"publicationDate":"2025-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11236452","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A “memriscapacitor” consisting of a memristor and capacitor has been proposed and actually fabricated. The advantages are the wide dynamic ranges and low power consumption achieved simultaneously. First, the device structure is quite simple, namely, an amorphous Ga-Sn-O thin film between electrodes acts as a memristor, whereas a SiO2 film acts as a capacitor. Next, the hysteresis characteristic of the memristor is observed. Finally, it is validated that the multiply-accumulate calculation is realized as desired by the memriscapacitor.
{"title":"Memriscapacitor Consisting of a Memristor and Capacitor — The First Proposal and Fabrication With Validation of Multiply-Accumulate Calculation","authors":"Kenta Yachida;Kazuki Sawai;Tokiyoshi Matsuda;Hidenori Kawanishi;Mutsumi Kimura","doi":"10.1109/JEDS.2025.3630670","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3630670","url":null,"abstract":"A “memriscapacitor” consisting of a memristor and capacitor has been proposed and actually fabricated. The advantages are the wide dynamic ranges and low power consumption achieved simultaneously. First, the device structure is quite simple, namely, an amorphous Ga-Sn-O thin film between electrodes acts as a memristor, whereas a SiO2 film acts as a capacitor. Next, the hysteresis characteristic of the memristor is observed. Finally, it is validated that the multiply-accumulate calculation is realized as desired by the memriscapacitor.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1120-1124"},"PeriodicalIF":2.4,"publicationDate":"2025-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11236444","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-10DOI: 10.1109/JEDS.2025.3631061
Yu-Che Tsai;Jenn-Gwo Hwu
A compact logic-configurable device based on a concentric structure with a non-planar oxide structure is demonstrated. The implementation of a non-planar oxide structure minimizes leakage current paths, leading to a reduction in total current. The device maintains stable and different current levels over 100 repeated switching cycles for center biased at + 1 V and rings between flat-band voltage ($approx $ –0.9 V) and 0 V, demonstrating excellent reliability and suitability for multi-state computing in AI applications. When the center was biased at a selected negative bias, the output current polarity at the center electrode is determined by the interplay between tunneling and coupling effects. By adjusting the center bias, multiple logic functions of OR, MAJ, and AND can be realized within a single device by detecting current polarity. The proposed structure exhibits stable operation over 1000 cycles. Notably, the use of a non-planar oxide leads to a dramatic reduction in power consumption, reaching nearly two orders of magnitude improvement with respect to planar oxide structure. TCAD simulations confirm its scalability down to the nanoscale, underscoring its potential for energy-efficient compute-in-memory applications.
{"title":"Low Power Logic Functions in Non-Planar Oxide Metal–Insulator–Semiconductor Tunnel Diodes via Tunneling–Coupling Current Competition","authors":"Yu-Che Tsai;Jenn-Gwo Hwu","doi":"10.1109/JEDS.2025.3631061","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3631061","url":null,"abstract":"A compact logic-configurable device based on a concentric structure with a non-planar oxide structure is demonstrated. The implementation of a non-planar oxide structure minimizes leakage current paths, leading to a reduction in total current. The device maintains stable and different current levels over 100 repeated switching cycles for center biased at + 1 V and rings between flat-band voltage (<inline-formula> <tex-math>$approx $ </tex-math></inline-formula> –0.9 V) and 0 V, demonstrating excellent reliability and suitability for multi-state computing in AI applications. When the center was biased at a selected negative bias, the output current polarity at the center electrode is determined by the interplay between tunneling and coupling effects. By adjusting the center bias, multiple logic functions of OR, MAJ, and AND can be realized within a single device by detecting current polarity. The proposed structure exhibits stable operation over 1000 cycles. Notably, the use of a non-planar oxide leads to a dramatic reduction in power consumption, reaching nearly two orders of magnitude improvement with respect to planar oxide structure. TCAD simulations confirm its scalability down to the nanoscale, underscoring its potential for energy-efficient compute-in-memory applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1144-1150"},"PeriodicalIF":2.4,"publicationDate":"2025-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11237060","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145560723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-04DOI: 10.1109/JEDS.2025.3628873
Mohammad Masum Billah;Minkyu Chun;Md Delwar Hossain Chowdhury;Jin Jang;Moath Alathbah
We report the effect of secondary gate bias (both the top gate voltage, ${mathrm { V}}_{mathrm {TG}}{({mathrm { V}})}$ and bottom gate voltage ${mathrm { V}}_{mathrm {BG}}{({mathrm { V}}})$ on the temperature-dependent density of state (DOS) estimation in dual gate (DG) amorphous indium gallium zinc oxide (a−IGZO) thin-film transistors (TFTs). The measured transfer characteristics exhibit a negative shift with increasing secondary gate bias from 0 V to 15 V, which can be explained as the Fermi energy $({mathrm { E}}_{mathrm { F}})$ shift towards the conduction band $({mathrm { E}}_{mathrm { C}})$ edge. The extracted Meyer-Neldel energy $({mathrm { E}}_{mathrm {MN}})$ from temperature-dependent transfer characteristics of a−IGZO TFTs shows two trends depending on activation energy $({mathrm { E}}_{mathrm { A}})$ ; normal ${mathrm { E}}_{mathrm {MN}}~({mathrm { E}}_{mathrm { A}}{gt 0.1 {mathrm { eV}}})$ and inverse ${mathrm { E}}_{mathrm {MN}}~({mathrm { E}}_{mathrm { A}}{lt 0.1 {mathrm { eV}}})$ . The secondary gate bias-independent normal ${mathrm { E}}_{mathrm {MN}}{ sim 41}$ meV can be explained as the statistical shift of ${mathrm { E}}_{mathrm { F}}$ below${ }{mathrm { E}}_{mathrm { C}}$ , whereas, secondary gate bias-dependent inverse ${mathrm { E}}_{mathrm {MN}}$ increases with increasing secondary gate voltage (0 V to 15 V) and appears to be due to the increased contact resistance at source/drain regions, which is confirmed by TCAD simulation. The density of tail states as a function of energy (E) is obtained from the MN rule as ${sim }{3.2 times 10}^{19}$ $bullet $ $ ~{{mathrm { exp}}(- {mathrm { E}}/}{mathrm { W}}_{mathrm { T}})$ with ${mathrm { V}}_{mathrm {TG}}$ , ${sim }{5.4 times 10}^{19}$ $bullet $ $ ~{{mathrm { exp}}(- {mathrm { E}}/}{mathrm { W}}_{mathrm { T}})$ with ${mathrm { V}}_{mathrm {BG}}$ , and a tail state slope
{"title":"Extraction of Density of State of Dual Gate Amorphous In-Ga-Zn-O Transistors From Meyer-Neldel (MN) Analysis","authors":"Mohammad Masum Billah;Minkyu Chun;Md Delwar Hossain Chowdhury;Jin Jang;Moath Alathbah","doi":"10.1109/JEDS.2025.3628873","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3628873","url":null,"abstract":"We report the effect of secondary gate bias (both the top gate voltage, <inline-formula> <tex-math>${mathrm { V}}_{mathrm {TG}}{({mathrm { V}})}$ </tex-math></inline-formula> and bottom gate voltage <inline-formula> <tex-math>${mathrm { V}}_{mathrm {BG}}{({mathrm { V}}})$ </tex-math></inline-formula> on the temperature-dependent density of state (DOS) estimation in dual gate (DG) amorphous indium gallium zinc oxide (a−IGZO) thin-film transistors (TFTs). The measured transfer characteristics exhibit a negative shift with increasing secondary gate bias from 0 V to 15 V, which can be explained as the Fermi energy <inline-formula> <tex-math>$({mathrm { E}}_{mathrm { F}})$ </tex-math></inline-formula> shift towards the conduction band <inline-formula> <tex-math>$({mathrm { E}}_{mathrm { C}})$ </tex-math></inline-formula> edge. The extracted Meyer-Neldel energy <inline-formula> <tex-math>$({mathrm { E}}_{mathrm {MN}})$ </tex-math></inline-formula> from temperature-dependent transfer characteristics of a−IGZO TFTs shows two trends depending on activation energy <inline-formula> <tex-math>$({mathrm { E}}_{mathrm { A}})$ </tex-math></inline-formula>; normal <inline-formula> <tex-math>${mathrm { E}}_{mathrm {MN}}~({mathrm { E}}_{mathrm { A}}{gt 0.1 {mathrm { eV}}})$ </tex-math></inline-formula> and inverse <inline-formula> <tex-math>${mathrm { E}}_{mathrm {MN}}~({mathrm { E}}_{mathrm { A}}{lt 0.1 {mathrm { eV}}})$ </tex-math></inline-formula>. The secondary gate bias-independent normal <inline-formula> <tex-math>${mathrm { E}}_{mathrm {MN}}{ sim 41}$ </tex-math></inline-formula> meV can be explained as the statistical shift of <inline-formula> <tex-math>${mathrm { E}}_{mathrm { F}}$ </tex-math></inline-formula> below<inline-formula> <tex-math>${ }{mathrm { E}}_{mathrm { C}}$ </tex-math></inline-formula>, whereas, secondary gate bias-dependent inverse <inline-formula> <tex-math>${mathrm { E}}_{mathrm {MN}}$ </tex-math></inline-formula> increases with increasing secondary gate voltage (0 V to 15 V) and appears to be due to the increased contact resistance at source/drain regions, which is confirmed by TCAD simulation. The density of tail states as a function of energy (E) is obtained from the MN rule as <inline-formula> <tex-math>${sim }{3.2 times 10}^{19}$ </tex-math></inline-formula><inline-formula> <tex-math>$bullet $ </tex-math></inline-formula><inline-formula> <tex-math>$ ~{{mathrm { exp}}(- {mathrm { E}}/}{mathrm { W}}_{mathrm { T}})$ </tex-math></inline-formula> with <inline-formula> <tex-math>${mathrm { V}}_{mathrm {TG}}$ </tex-math></inline-formula>, <inline-formula> <tex-math>${sim }{5.4 times 10}^{19}$ </tex-math></inline-formula><inline-formula> <tex-math>$bullet $ </tex-math></inline-formula><inline-formula> <tex-math>$ ~{{mathrm { exp}}(- {mathrm { E}}/}{mathrm { W}}_{mathrm { T}})$ </tex-math></inline-formula> with <inline-formula> <tex-math>${mathrm { V}}_{mathrm {BG}}$ </tex-math></inline-formula>, and a tail state slope <inline-formula> <t","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1125-1132"},"PeriodicalIF":2.4,"publicationDate":"2025-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11224921","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Atomic layer deposition (ALD) In2O3 is a promising candidate channel material for the back-end of line (BEOL) transistors due to its numerous advantages. However, its application is limited by the degenerative doping of the channel caused by the deposition of top-gate (TG) dielectrics. In this study, we utilized mild (the temperature remains < 150 ° C through gate-stack fabrication steps) ozone-based treatment to improve the interfacial properties of In2O3, resulting in high stability during HfO2 deposition. Our ozone-based In2O3 TG transistors have a high on current (Ion) ${=}284~mu $ A/$mu $ m, a low Subthreshold Swing (SS) = 63 mV/dec at V${_{text {d}}}{=}1$ V for L${_{text {ch}}}{=}1~mu $ m. Additionally, high field-effect mobility $(mu _{mathrm { FE}}){=}120$ cm2V−1s−1, small threshold voltage (VT) shift = –63 mV under positive stress voltage = 2 V, and VT shift = −88 mV from 25 ° C to 125 ° C are also achieved, demonstrating the great potential of ozone-based treatment for future In2O3 TG transistors.
{"title":"High Mobility and Robust Top-Gate In₂O₃ Thin Film Transistor by Ozone-Based Treatment","authors":"Ching-Shuan Huang;Tung-Cheng Shih;Che-Chi Shih;Wu-Wei Tsai;Chien-Wei Chen;Yu-Hsuan Yu;Wei-Yen Woon;Chao-Hsin Chien","doi":"10.1109/JEDS.2025.3627495","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3627495","url":null,"abstract":"Atomic layer deposition (ALD) In2O3 is a promising candidate channel material for the back-end of line (BEOL) transistors due to its numerous advantages. However, its application is limited by the degenerative doping of the channel caused by the deposition of top-gate (TG) dielectrics. In this study, we utilized mild (the temperature remains < 150 ° C through gate-stack fabrication steps) ozone-based treatment to improve the interfacial properties of In2O3, resulting in high stability during HfO2 deposition. Our ozone-based In2O3 TG transistors have a high on current (Ion) <inline-formula> <tex-math>${=}284~mu $ </tex-math></inline-formula>A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, a low Subthreshold Swing (SS) = 63 mV/dec at V<inline-formula> <tex-math>${_{text {d}}}{=}1$ </tex-math></inline-formula> V for L<inline-formula> <tex-math>${_{text {ch}}}{=}1~mu $ </tex-math></inline-formula>m. Additionally, high field-effect mobility <inline-formula> <tex-math>$(mu _{mathrm { FE}}){=}120$ </tex-math></inline-formula> cm2V−1s−1, small threshold voltage (VT) shift = –63 mV under positive stress voltage = 2 V, and VT shift = −88 mV from 25 ° C to 125 ° C are also achieved, demonstrating the great potential of ozone-based treatment for future In2O3 TG transistors.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1112-1119"},"PeriodicalIF":2.4,"publicationDate":"2025-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11222119","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-30DOI: 10.1109/JEDS.2025.3627211
Y. T. Zheng;H. L. Zhu;Y. K. Zhang;W. L. Liu;Q. Wang;X. Y. Chen;P. H. Sun;K. Q. Zhao;S. S. Lu;Y. D;B. H. Wang;J. B. Liu;G. B. Bai;Q. F. Jiang;X. B. He;J. Luo
We present dual Vertical C-Shaped-Channel Nanosheet Field-Effect Transistors (dVCNFETs), with a novel integration process aimed at advancing the scalability and performance of future CMOS technologies. The proposed method leverages epitaxial Si/SiGe/Si layers, enabling precise control over gate length and channel thickness. By incorporating spacer image transfer (SIT) and bidirectional cross-etching (BCE) techniques, dual-channel structures are formed with self-aligned high-k metal gates (HKMG). The dVCNFETs demonstrate impressive electrical performance with an on-state current (Idsat) of $442~mu $ A/$mu $ m, sub-threshold slope (SS) of 61.64 mV/dec, and a high Ion/Ioff ratio of $1.19times 10^{8}$ , showcasing superior short-channel control and device scalability. This integration technique, which could fabricate multiple channels, compatible with state-of-the-art CMOS fabrication processes, holds significant potential for high-density integrated circuits and future advanced logic applications.
{"title":"Fabrication of Dual Vertical C-Shaped-Channel Nanosheet FETs via a Novel Integration Process for High-Density, Scalable CMOS Applications","authors":"Y. T. Zheng;H. L. Zhu;Y. K. Zhang;W. L. Liu;Q. Wang;X. Y. Chen;P. H. Sun;K. Q. Zhao;S. S. Lu;Y. D;B. H. Wang;J. B. Liu;G. B. Bai;Q. F. Jiang;X. B. He;J. Luo","doi":"10.1109/JEDS.2025.3627211","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3627211","url":null,"abstract":"We present dual Vertical C-Shaped-Channel Nanosheet Field-Effect Transistors (dVCNFETs), with a novel integration process aimed at advancing the scalability and performance of future CMOS technologies. The proposed method leverages epitaxial Si/SiGe/Si layers, enabling precise control over gate length and channel thickness. By incorporating spacer image transfer (SIT) and bidirectional cross-etching (BCE) techniques, dual-channel structures are formed with self-aligned high-k metal gates (HKMG). The dVCNFETs demonstrate impressive electrical performance with an on-state current (Idsat) of <inline-formula> <tex-math>$442~mu $ </tex-math></inline-formula>A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, sub-threshold slope (SS) of 61.64 mV/dec, and a high Ion/Ioff ratio of <inline-formula> <tex-math>$1.19times 10^{8}$ </tex-math></inline-formula>, showcasing superior short-channel control and device scalability. This integration technique, which could fabricate multiple channels, compatible with state-of-the-art CMOS fabrication processes, holds significant potential for high-density integrated circuits and future advanced logic applications.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1133-1137"},"PeriodicalIF":2.4,"publicationDate":"2025-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11222666","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145560722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
1.2 kV 4H-SiC MOSFETs with linear, hexagonal, square, and ladder topological layouts were designed with uniform design rules and fabricated simultaneously on the same wafer. These devices were then diced and packaged to conduct a comprehensive analysis between their static and dynamic electrical characteristics. 3D TCAD simulations for each device type were also conducted to further elucidate the trends observed with the experimental data. The ladder and hexagonal MOSFET designs both demonstrated the greatest improvement in specific on-resistance (Ron,sp) with no degradation in the breakdown voltage. However, 3D simulations of the blocking characteristics reveal that the maximum electric field in the oxide and 4H-SiC are greater in the hexagonal design due to the corner in the JFET region. Furthermore, the MOSFET with the ladder design demonstrates superior switching characteristics compared to the hexagonal design due to its large increase in channel density and minimal increase in JFET density, with a (FOM[Ciss/Crss]) 2x greater than the Nominal MOSFET, where Ciss is the input capacitance and Cgd is the reverse transfer capacitance.
{"title":"Comprehensive Experimental and Simulation Study of Six 1.2 kV SiC MOSFET Layout Topologies","authors":"Skylar deBoer;Seung Yup Jang;Adam Morgan;Woongje Sung","doi":"10.1109/JEDS.2025.3624282","DOIUrl":"https://doi.org/10.1109/JEDS.2025.3624282","url":null,"abstract":"1.2 kV 4H-SiC MOSFETs with linear, hexagonal, square, and ladder topological layouts were designed with uniform design rules and fabricated simultaneously on the same wafer. These devices were then diced and packaged to conduct a comprehensive analysis between their static and dynamic electrical characteristics. 3D TCAD simulations for each device type were also conducted to further elucidate the trends observed with the experimental data. The ladder and hexagonal MOSFET designs both demonstrated the greatest improvement in specific on-resistance (Ron,sp) with no degradation in the breakdown voltage. However, 3D simulations of the blocking characteristics reveal that the maximum electric field in the oxide and 4H-SiC are greater in the hexagonal design due to the corner in the JFET region. Furthermore, the MOSFET with the ladder design demonstrates superior switching characteristics compared to the hexagonal design due to its large increase in channel density and minimal increase in JFET density, with a (FOM[Ciss/Crss]) 2x greater than the Nominal MOSFET, where Ciss is the input capacitance and Cgd is the reverse transfer capacitance.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"1103-1111"},"PeriodicalIF":2.4,"publicationDate":"2025-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11214226","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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