Pub Date : 2024-09-23DOI: 10.1109/JEDS.2024.3465594
Su Yeon Jung;Hyunwoo Kim;Jongmin Lee;Jang Hyun Kim
We analyzed the impact of work-function variation (WFV) in ferroelectric field-effect transistor (FeFET). To analyze the operation characteristics, we employed the technology computer-aided design (TCAD) simulations. After evaluating ferroelectricity (FE) characteristics and optimizing device model parameters through calibration, we extracted five key parameters from the hysteretic transfer curves of the FeFET: threshold voltage (Vth), on current (Iin), subthreshold swing (SS), off current (Ioff), and gate-induced drain leakage (GIDL). The extracted parameters were compared based on the presence or absence of FE and the ferroelectric thickness. It was confirmed that the presence of FE leads to increased variation due to dipole alignment with WFV, and that the electric field is maintained even with an increase in ferroelectric thickness
我们分析了铁电场效应晶体管（FeFET）中功函数变化（WFV）的影响。为了分析工作特性，我们采用了技术计算机辅助设计（TCAD）模拟。在评估了铁电（FE）特性并通过校准优化了器件模型参数后，我们从铁电场效应晶体管的滞后转移曲线中提取了五个关键参数：阈值电压（Vth）、导通电流（Iin）、亚阈值摆动（SS）、关断电流（Ioff）和栅极诱导漏极泄漏（GIDL）。根据是否存在 FE 和铁电厚度对提取的参数进行了比较。结果证实，FE 的存在会导致偶极对齐与 WFV 的变化增加，而且即使铁电厚度增加，电场也会保持不变。
{"title":"Impact of Work-Function Variation in Ferroelectric Field-Effect Transistor","authors":"Su Yeon Jung;Hyunwoo Kim;Jongmin Lee;Jang Hyun Kim","doi":"10.1109/JEDS.2024.3465594","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3465594","url":null,"abstract":"We analyzed the impact of work-function variation (WFV) in ferroelectric field-effect transistor (FeFET). To analyze the operation characteristics, we employed the technology computer-aided design (TCAD) simulations. After evaluating ferroelectricity (FE) characteristics and optimizing device model parameters through calibration, we extracted five key parameters from the hysteretic transfer curves of the FeFET: threshold voltage (Vth), on current (Iin), subthreshold swing (SS), off current (Ioff), and gate-induced drain leakage (GIDL). The extracted parameters were compared based on the presence or absence of FE and the ferroelectric thickness. It was confirmed that the presence of FE leads to increased variation due to dipole alignment with WFV, and that the electric field is maintained even with an increase in ferroelectric thickness","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"779-784"},"PeriodicalIF":2.0,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10685408","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142359756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
One-dimensionalcarbon nanotube field-effect transistors (CNFETs) have offered a solution for obtaining high transistor performance in a compatible low-temperature BEOL process, enabling monolithic 3D integration benefits for more functional circuits. Currently, CNT transistors need to further improve their performance with a more stable process and explore the most suitable circuit application scene. In this study, we successfully enhanced the performance of CNFETs through special Y2O3 film passivation and vacuum annealing processes. The on-state current of the optimized device was improved by $36.6times $ compared to the device without these processes. Besides, the subthreshold swing (SS) was notably reduced from 259 mV/dec to 215 mV/dec and the threshold voltage was decreased from 2.02 V to 1.79 V due to the reduction of the interface state. Meanwhile, the devices’ optoelectronic characteristics were significantly improved and exhibited a $72times $ increase in $Delta $ Ids under identical illumination. With an improved annealing process, the $Delta $ Ids were further increased to $231times $ compared to the original device because of the reduction of defects within the device. Finally, the tentative Morse code communication applications all by the optimized CNFETs were obtained. These technologies and functional implementations provided a promising approach for future 3D functional communication systems with CNT technology.
{"title":"High-Performance Carbon Nanotube Optoelectronic Transistor With Optimized Process for 3D Communication Circuit Applications","authors":"Shuang Liu;Heyi Huang;Yanqing Li;Yadong Zhang;Feixiong Wang;Zhaohao Zhang;Qingzhu Zhang;Jiali Huo;Jiaxin Yao;Jing Wen;Huaxiang Yin","doi":"10.1109/JEDS.2024.3465669","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3465669","url":null,"abstract":"One-dimensionalcarbon nanotube field-effect transistors (CNFETs) have offered a solution for obtaining high transistor performance in a compatible low-temperature BEOL process, enabling monolithic 3D integration benefits for more functional circuits. Currently, CNT transistors need to further improve their performance with a more stable process and explore the most suitable circuit application scene. In this study, we successfully enhanced the performance of CNFETs through special Y2O3 film passivation and vacuum annealing processes. The on-state current of the optimized device was improved by \u0000<inline-formula> <tex-math>$36.6times $ </tex-math></inline-formula>\u0000 compared to the device without these processes. Besides, the subthreshold swing (SS) was notably reduced from 259 mV/dec to 215 mV/dec and the threshold voltage was decreased from 2.02 V to 1.79 V due to the reduction of the interface state. Meanwhile, the devices’ optoelectronic characteristics were significantly improved and exhibited a \u0000<inline-formula> <tex-math>$72times $ </tex-math></inline-formula>\u0000 increase in \u0000<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>\u0000 Ids under identical illumination. With an improved annealing process, the \u0000<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>\u0000 Ids were further increased to \u0000<inline-formula> <tex-math>$231times $ </tex-math></inline-formula>\u0000 compared to the original device because of the reduction of defects within the device. Finally, the tentative Morse code communication applications all by the optimized CNFETs were obtained. These technologies and functional implementations provided a promising approach for future 3D functional communication systems with CNT technology.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"889-897"},"PeriodicalIF":2.0,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10685345","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142408907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-18DOI: 10.1109/JEDS.2024.3462930
S. Ohmi;M. Tanuma;J.W. Shin
In this work, we have investigated the conductance control of the metal-ferroelectrics-Si field-effect transistor (MFSFET) utilizing 5 nm thick ferroelectric nondoped $rm HfO_{2}$ (FeND-HfO2) gate insulator. The Kr-plasma process is effective to decrease the plasma damage compared to the Ar-plasma process during the in-situ deposition of FeND-HfO2 and Pt gate electrode by RF-magnetron sputtering. The precise control such as less than 20 mV was realized which led to the conductance control for 10 states from 0 to $0.6~mu $ S/ $mu $ m both for potentiation and depression operations with the input pulses of $mathbf {pm 3}$ V/100 ns.
{"title":"Kr-Plasma Process for Conductance Control of MFSFET With FeND-HfO₂ Gate Insulator","authors":"S. Ohmi;M. Tanuma;J.W. Shin","doi":"10.1109/JEDS.2024.3462930","DOIUrl":"10.1109/JEDS.2024.3462930","url":null,"abstract":"In this work, we have investigated the conductance control of the metal-ferroelectrics-Si field-effect transistor (MFSFET) utilizing 5 nm thick ferroelectric nondoped \u0000<inline-formula> <tex-math>$rm HfO_{2}$ </tex-math></inline-formula>\u0000 (FeND-HfO2) gate insulator. The Kr-plasma process is effective to decrease the plasma damage compared to the Ar-plasma process during the in-situ deposition of FeND-HfO2 and Pt gate electrode by RF-magnetron sputtering. The precise control such as less than 20 mV was realized which led to the conductance control for 10 states from 0 to \u0000<inline-formula> <tex-math>$0.6~mu $ </tex-math></inline-formula>\u0000S/\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m both for potentiation and depression operations with the input pulses of \u0000<inline-formula> <tex-math>$mathbf {pm 3}$ </tex-math></inline-formula>\u0000 V/100 ns.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"775-778"},"PeriodicalIF":2.0,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10682993","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142253406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-17DOI: 10.1109/JEDS.2024.3462590
Wei-Cheng Wang;Ming-Dou Ker
When more circuit functions are integrated into a single chip fabricated by the GaN-on-Silicon process, the need for on-chip electrostatic discharge (ESD) protection design becomes crucial to safeguard GaN integrated circuits (ICs). In this work, the power-rail ESD clamp circuit with gate-coupled design, fabricated in a GaN-on-Silicon process, was investigated. By increasing the gate-coupled capacitance, ESD level of the power-rail ESD clamp circuit can be significantly improved. However, the increased capacitance induces transient leakage current during normal power-on operation. To overcome this issue, a new detection circuit was proposed, which can differentiate between the ESD event and the normal power-on transient operation. Therefore, incorporating this new proposed detection circuit with the gate-coupled design allows for good ESD robustness, while also preventing transient leakage current during normal power-on condition.
{"title":"Fully Integrated GaN-on-Silicon Power-Rail ESD Clamp Circuit Without Transient Leakage Current During Normal Power-on Operation","authors":"Wei-Cheng Wang;Ming-Dou Ker","doi":"10.1109/JEDS.2024.3462590","DOIUrl":"10.1109/JEDS.2024.3462590","url":null,"abstract":"When more circuit functions are integrated into a single chip fabricated by the GaN-on-Silicon process, the need for on-chip electrostatic discharge (ESD) protection design becomes crucial to safeguard GaN integrated circuits (ICs). In this work, the power-rail ESD clamp circuit with gate-coupled design, fabricated in a GaN-on-Silicon process, was investigated. By increasing the gate-coupled capacitance, ESD level of the power-rail ESD clamp circuit can be significantly improved. However, the increased capacitance induces transient leakage current during normal power-on operation. To overcome this issue, a new detection circuit was proposed, which can differentiate between the ESD event and the normal power-on transient operation. Therefore, incorporating this new proposed detection circuit with the gate-coupled design allows for good ESD robustness, while also preventing transient leakage current during normal power-on condition.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"760-769"},"PeriodicalIF":2.0,"publicationDate":"2024-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10681588","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142253407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-16DOI: 10.1109/JEDS.2024.3461169
Ahmad Khusro;Saddam Husain;Mohammad S. Hashmi
This paper uses the Adaptive Neuro-Fuzzy Inference System (ANFIS) to investigate and propose a new alternative behavioral modeling technique for microwave power transistors. Utilizing measured I-V characteristics, associated parameters like transconductance $(g_{text {m}})$ and output conductance $(g_{text {ds}})$ , etc., S-parameters characteristics, and RF performance parameters such as unity current gain frequency $(f_{text {T}})$ , maximum unilateral gain frequency $(f_{max })$ , ANFIS-based behavioral models are developed for Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) and validated. The models have been developed using two distinct devices with dimensions of $10times 200~mu m$ and $10times 250~mu m$ for multi-bias conditions and over a broad frequency range (0.5 to 43.5 GHz). Subsequently, the proposed model performance is validated on devices with geometries of $10times 220~mu m$ , $4times 100~mu m$ , and $2times 200~mu m$ to examine the interpolation accuracy, extrapolation potential, and scalability. Here, ANFIS utilizes the subtractive clustering method to process the measurement characteristics by computing the clusters and opts for the best-performing model using error and number of fuzzy rules as criteria. The parameters involved in the fuzzy representation are trained using neural network algorithms, namely gradient-descent and least squares estimate. The proposed models are subsequently incorporated in a commercial circuit simulator (Keysight’s ADS) and the class-F power amplifier’s gain and stability characteristics are computed and studied.
{"title":"Combining Intelligence With Rules for Device Modeling: Approximating the Behavior of AlGaN/GaN HEMTs Using a Hybrid Neural Network and Fuzzy Logic Inference System","authors":"Ahmad Khusro;Saddam Husain;Mohammad S. Hashmi","doi":"10.1109/JEDS.2024.3461169","DOIUrl":"10.1109/JEDS.2024.3461169","url":null,"abstract":"This paper uses the Adaptive Neuro-Fuzzy Inference System (ANFIS) to investigate and propose a new alternative behavioral modeling technique for microwave power transistors. Utilizing measured I-V characteristics, associated parameters like transconductance \u0000<inline-formula> <tex-math>$(g_{text {m}})$ </tex-math></inline-formula>\u0000 and output conductance \u0000<inline-formula> <tex-math>$(g_{text {ds}})$ </tex-math></inline-formula>\u0000, etc., S-parameters characteristics, and RF performance parameters such as unity current gain frequency \u0000<inline-formula> <tex-math>$(f_{text {T}})$ </tex-math></inline-formula>\u0000, maximum unilateral gain frequency \u0000<inline-formula> <tex-math>$(f_{max })$ </tex-math></inline-formula>\u0000, ANFIS-based behavioral models are developed for Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) and validated. The models have been developed using two distinct devices with dimensions of \u0000<inline-formula> <tex-math>$10times 200~mu m$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$10times 250~mu m$ </tex-math></inline-formula>\u0000 for multi-bias conditions and over a broad frequency range (0.5 to 43.5 GHz). Subsequently, the proposed model performance is validated on devices with geometries of \u0000<inline-formula> <tex-math>$10times 220~mu m$ </tex-math></inline-formula>\u0000, \u0000<inline-formula> <tex-math>$4times 100~mu m$ </tex-math></inline-formula>\u0000, and \u0000<inline-formula> <tex-math>$2times 200~mu m$ </tex-math></inline-formula>\u0000 to examine the interpolation accuracy, extrapolation potential, and scalability. Here, ANFIS utilizes the subtractive clustering method to process the measurement characteristics by computing the clusters and opts for the best-performing model using error and number of fuzzy rules as criteria. The parameters involved in the fuzzy representation are trained using neural network algorithms, namely gradient-descent and least squares estimate. The proposed models are subsequently incorporated in a commercial circuit simulator (Keysight’s ADS) and the class-F power amplifier’s gain and stability characteristics are computed and studied.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"723-737"},"PeriodicalIF":2.0,"publicationDate":"2024-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10680392","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142253410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-13DOI: 10.1109/JEDS.2024.3459872
Ji Hwan Lee;Kihwan Kim;Kyungjin Rim;Soogine Chong;Hyunbo Cho;Saeroonter Oh
Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology computer-aided design (TCAD) device simulation data of GAA field-effect transistors (FETs) subjected to both tensile and compressive strain in nMOS and pMOS devices. Strain was induced into the channel via lattice mismatch between the channel and source/drain epitaxial regions, as simulated by 3D TCAD process simulator. The transport models were calibrated against advanced Monte Carlo simulations to ensure accuracy. The resulting neural compact model demonstrated a close approximation to the original simulation results, achieving a minimal error of 1%. To assess the strain effect on circuit-level performance, SPICE simulations were conducted for a 5-stage ring oscillator and a 2-input NAND gate using the neural compact model. The propagation delay of the 5-stage ring oscillator improved from 3.60 ps to 2.85 ps when implementing strained GAA FETs. Also, strain enhanced the power-delay product of the 2-input NAND gate by 13.8% to 15.5%, depending on the input voltage sequence.
{"title":"Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach","authors":"Ji Hwan Lee;Kihwan Kim;Kyungjin Rim;Soogine Chong;Hyunbo Cho;Saeroonter Oh","doi":"10.1109/JEDS.2024.3459872","DOIUrl":"10.1109/JEDS.2024.3459872","url":null,"abstract":"Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology computer-aided design (TCAD) device simulation data of GAA field-effect transistors (FETs) subjected to both tensile and compressive strain in nMOS and pMOS devices. Strain was induced into the channel via lattice mismatch between the channel and source/drain epitaxial regions, as simulated by 3D TCAD process simulator. The transport models were calibrated against advanced Monte Carlo simulations to ensure accuracy. The resulting neural compact model demonstrated a close approximation to the original simulation results, achieving a minimal error of 1%. To assess the strain effect on circuit-level performance, SPICE simulations were conducted for a 5-stage ring oscillator and a 2-input NAND gate using the neural compact model. The propagation delay of the 5-stage ring oscillator improved from 3.60 ps to 2.85 ps when implementing strained GAA FETs. Also, strain enhanced the power-delay product of the 2-input NAND gate by 13.8% to 15.5%, depending on the input voltage sequence.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"770-774"},"PeriodicalIF":2.0,"publicationDate":"2024-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10680295","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142253411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Computing-In-Memory (CIM) is widely applied in neural networks due to its unique capability to perform multiply-and-accumulate operations within a circuit array. This process directly obtains the current value through the product of voltage and conductance, accumulating it on the bit line, thus realizing storage and computing functionalities simultaneously within a single array. This significantly reduces the power consumption and time delay in data processing. Unfortunately, implementing general-purpose logic computations in large-scale memory arrays with CIM remains a challenge. This paper introduced a novel device concept, the programmable diode—a special type of memristor with a high switching window, ideally suited for memory arrays to reduce power consumption. A compact SPICE model was developed to enable circuit-level simulations in EDA tools. We also proposed a method to efficiently control the programmable diode for logic operations in memory arrays, and in this way, we constructed a parallel 8-bit full adder to verify the feasibility of the proposed method. Finally, based on the 8-bit full adder, we built a 5KB in-memory logic array capable of executing logic computations and simulated it using EDA tools. The simulation results demonstrated that the 5KB in-memory logic array can perform fundamental Boolean logic and arithmetic operations with high repeatability and parallelism, perfectly realizing the functionality of in-memory logic computation. Our work can provide a feasible scheme for realizing large-scale general logic computation systems based on CIM.
{"title":"A Novel Parallel In-Memory Logic Array Based on Programmable Diodes","authors":"Jiabao Ye;Junyu Zhu;Jifang Cao;Haoxiong Bi;Yong Ding;Bing Chen","doi":"10.1109/JEDS.2024.3457021","DOIUrl":"10.1109/JEDS.2024.3457021","url":null,"abstract":"Computing-In-Memory (CIM) is widely applied in neural networks due to its unique capability to perform multiply-and-accumulate operations within a circuit array. This process directly obtains the current value through the product of voltage and conductance, accumulating it on the bit line, thus realizing storage and computing functionalities simultaneously within a single array. This significantly reduces the power consumption and time delay in data processing. Unfortunately, implementing general-purpose logic computations in large-scale memory arrays with CIM remains a challenge. This paper introduced a novel device concept, the programmable diode—a special type of memristor with a high switching window, ideally suited for memory arrays to reduce power consumption. A compact SPICE model was developed to enable circuit-level simulations in EDA tools. We also proposed a method to efficiently control the programmable diode for logic operations in memory arrays, and in this way, we constructed a parallel 8-bit full adder to verify the feasibility of the proposed method. Finally, based on the 8-bit full adder, we built a 5KB in-memory logic array capable of executing logic computations and simulated it using EDA tools. The simulation results demonstrated that the 5KB in-memory logic array can perform fundamental Boolean logic and arithmetic operations with high repeatability and parallelism, perfectly realizing the functionality of in-memory logic computation. Our work can provide a feasible scheme for realizing large-scale general logic computation systems based on CIM.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"738-744"},"PeriodicalIF":2.0,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10674001","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142198876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-06DOI: 10.1109/JEDS.2024.3455256
Boseong Son;Huijin Kim;Young-Woong Lee;Purusottam Reddy Bommireddy;Si-Hyun Park
We developed a monolithically integrated device consisting of a single GaN LED and two p-GaN-depletion MOSFETs on a GaN LED epitaxial layer. The p-GaN-depletion MOSFETs exhibited a subthreshold slope of 1 V/decade and a threshold voltage of –2 V, whereas the LED exhibited a forward voltage of 3.5 V at 1 mA and an electroluminescence peak of 445 nm. The device could be controlled by the scan voltage, with $V_{DD}$ ranging from 1 to 2 V, and cut off the total current with an applied scan voltage greater than 3 V. This work represents an important step towards the monolithic integration of LED and transistors for use in active-matrix micro-LED displays.
我们开发了一种单片集成器件，包括一个氮化镓发光二极管和两个位于氮化镓发光二极管外延层上的p-氮化镓损耗MOSFET。对氮化镓损耗 MOSFET 的阈下斜率为 1 V/decade，阈值电压为 -2 V，而 LED 在 1 mA 电流下的正向电压为 3.5 V，电致发光峰值为 445 nm。该器件可由扫描电压控制，$V_{DD}$范围为 1 至 2 V，并可在扫描电压大于 3 V 时切断总电流。
{"title":"Wafer-Scale Monolithic Integration of LEDs with p-GaN-Depletion MOSFETs on a GaN LED Epitaxial Layer","authors":"Boseong Son;Huijin Kim;Young-Woong Lee;Purusottam Reddy Bommireddy;Si-Hyun Park","doi":"10.1109/JEDS.2024.3455256","DOIUrl":"10.1109/JEDS.2024.3455256","url":null,"abstract":"We developed a monolithically integrated device consisting of a single GaN LED and two p-GaN-depletion MOSFETs on a GaN LED epitaxial layer. The p-GaN-depletion MOSFETs exhibited a subthreshold slope of 1 V/decade and a threshold voltage of –2 V, whereas the LED exhibited a forward voltage of 3.5 V at 1 mA and an electroluminescence peak of 445 nm. The device could be controlled by the scan voltage, with \u0000<inline-formula> <tex-math>$V_{DD}$ </tex-math></inline-formula>\u0000 ranging from 1 to 2 V, and cut off the total current with an applied scan voltage greater than 3 V. This work represents an important step towards the monolithic integration of LED and transistors for use in active-matrix micro-LED displays.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"905-911"},"PeriodicalIF":2.0,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10668404","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-04DOI: 10.1109/JEDS.2024.3454334
Manuel Fregolent;Mirco Boito;Michele Disarò;Carlo De Santi;Matteo Buffolo;Eleonora Canato;Michele Gallo;Cristina Miccoli;Isabella Rossetto;Giansalvo Pizzo;Alfio Russo;Ferdinando Iucolano;Gaudenzio Meneghesso;Enrico Zanoni;Matteo Meneghini
For the first time, we use electrical characterization, spectrally-resolved electroluminescence measurements and degradation tests to explain the negative activation energy of gate reliability in power GaN HEMTs with p-GaN Schottky gate. First, the origin of gate leakage current was modeled. The results indicate that the gate leakage current originates from three different mechanisms: (i) thermionic emission of electrons from the uid-GaN layer across the AlGaN barrier, for gate voltages below threshold $(V_{G} lt V_{TH})$ , (ii) thermionic emission of electrons from the channel to the p-GaN layer $(V_{TH} lt V_{G} lt 4.5 V)$ and (iii) trap-assisted-tunneling of holes at the Schottky metal for higher gate voltages. Then, the analysis of the reliability as function of gate bias demonstrated a negative activation energy (longer lifetime at high temperature). By analyzing the electroluminescence spectra under high positive bias, the improved time to failure at high temperatures was ascribed to the increased hole injection and recombination, that reduces the overall number of electrons that undergo avalanche multiplication, leading to the breakdown. Finally, the model was validated by comparing the electrical properties and conduction model of the devices pre- and post-stress.
{"title":"Negative Activation Energy of Gate Reliability in Schottky-Gate p-GaN HEMTs: Combined Gate Leakage Current Modeling and Spectral Electroluminescence Investigation","authors":"Manuel Fregolent;Mirco Boito;Michele Disarò;Carlo De Santi;Matteo Buffolo;Eleonora Canato;Michele Gallo;Cristina Miccoli;Isabella Rossetto;Giansalvo Pizzo;Alfio Russo;Ferdinando Iucolano;Gaudenzio Meneghesso;Enrico Zanoni;Matteo Meneghini","doi":"10.1109/JEDS.2024.3454334","DOIUrl":"10.1109/JEDS.2024.3454334","url":null,"abstract":"For the first time, we use electrical characterization, spectrally-resolved electroluminescence measurements and degradation tests to explain the negative activation energy of gate reliability in power GaN HEMTs with p-GaN Schottky gate. First, the origin of gate leakage current was modeled. The results indicate that the gate leakage current originates from three different mechanisms: (i) thermionic emission of electrons from the uid-GaN layer across the AlGaN barrier, for gate voltages below threshold \u0000<inline-formula> <tex-math>$(V_{G} lt V_{TH})$ </tex-math></inline-formula>\u0000, (ii) thermionic emission of electrons from the channel to the p-GaN layer \u0000<inline-formula> <tex-math>$(V_{TH} lt V_{G} lt 4.5 V)$ </tex-math></inline-formula>\u0000 and (iii) trap-assisted-tunneling of holes at the Schottky metal for higher gate voltages. Then, the analysis of the reliability as function of gate bias demonstrated a negative activation energy (longer lifetime at high temperature). By analyzing the electroluminescence spectra under high positive bias, the improved time to failure at high temperatures was ascribed to the increased hole injection and recombination, that reduces the overall number of electrons that undergo avalanche multiplication, leading to the breakdown. Finally, the model was validated by comparing the electrical properties and conduction model of the devices pre- and post-stress.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"703-709"},"PeriodicalIF":2.0,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10664574","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a new pixel circuit for active matrix organic light-emitting diode (AMOLED) display that can achieve high uniformity in low gray levels and its driving method are proposed. The proposed circuit compensates for threshold voltage variation of thin-film-transistors (TFTs), with the structure that minimizes the loss of sensed threshold voltage. However, the high current error rate in extremely low gray level is unavoidable, as the driving TFT (DRT) operates in subthreshold region, where the current difference caused by the threshold voltage variation can be severe. To suppress high error rates in low gray levels, the operation region of DRT is restricted to the saturation region, by adopting duty ratio modulation (DRM) method. With the DRM method, low gray is expressed with high current value and short emission time. The viability of the proposed circuit and its operation are analyzed with HSPICE. Compared to the conventional driving method, DRM significantly reduces the current error rate in low gray area. The proposed circuit is fabricated within 220 $mu {mathrm {m}} times 440 mu {mathrm {m}}$ . The measurement of the circuit also verified the capability of the proposed circuit and the DRM method.
{"title":"Highly Uniform Low Gray AMOLED Pixel Using Stable Circuit and Duty Ratio Modulation Driving","authors":"Chanjin Park;Hee-Ok Kim;Jong-Heon Yang;Jae-Eun Pi;Yong-Duck Kim;Chun-Won Byun;Kyeong-Soo Kang;Ji-Hwan Park;Minji Kim;Hyoungsik Nam;Soo-Yeon Lee","doi":"10.1109/JEDS.2024.3452753","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3452753","url":null,"abstract":"In this paper, a new pixel circuit for active matrix organic light-emitting diode (AMOLED) display that can achieve high uniformity in low gray levels and its driving method are proposed. The proposed circuit compensates for threshold voltage variation of thin-film-transistors (TFTs), with the structure that minimizes the loss of sensed threshold voltage. However, the high current error rate in extremely low gray level is unavoidable, as the driving TFT (DRT) operates in subthreshold region, where the current difference caused by the threshold voltage variation can be severe. To suppress high error rates in low gray levels, the operation region of DRT is restricted to the saturation region, by adopting duty ratio modulation (DRM) method. With the DRM method, low gray is expressed with high current value and short emission time. The viability of the proposed circuit and its operation are analyzed with HSPICE. Compared to the conventional driving method, DRM significantly reduces the current error rate in low gray area. The proposed circuit is fabricated within 220 \u0000<inline-formula> <tex-math>$mu {mathrm {m}} times 440 mu {mathrm {m}}$ </tex-math></inline-formula>\u0000. The measurement of the circuit also verified the capability of the proposed circuit and the DRM method.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"12 ","pages":"668-676"},"PeriodicalIF":2.0,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10663295","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142159891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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