Flexible photodetector is crucial for the intelligent industrial applications. However, the optical-sensitive materials are usually grown in a high temperature and then transferred onto the flexible substrate. This paper reported a directly fabricated flexible photodetector based on TiO2-doped Graphene Nanosheets Embedded Carbon (GNEC)film. An Electron Cyclotron Resonance (ECR) system was employed to in-situ deposit TiO2-doped GNEC film on a polyimide substrate, which were subsequently sensitized with N719 dye to fabricate the TiO2@GNEC photodetector. The GNEC film contains vertically aligned Graphene Nanosheets (GNs), which exhibit high-density edge states. The edge states suppress the recombination rate of photo-generated electron-hole pairs, thereby significantly enhancing the photo-responsive performance. The photodetector demonstrates a high photo responsivity of 0.82 mA/W and a response time of 1.93 seconds. Due to the in-situ manufacturing capabilities of the ECR system, which avoids defects from secondary material transfers, the photodetector array exhibits excellent consistency and achieves clear recognition of light patterns in both flat and bent states.
{"title":"Directly Fabricated Flexible Photodetector Based on TiO₂-Doped Carbon Nanosheets Film","authors":"Yunlong Zhang;Xiaolin Li;Zhipeng Cao;Qiang Wu;Gong Chen;Bo Wen;Dongfeng Diao;Xi Zhang","doi":"10.1109/JEDS.2024.3422292","DOIUrl":"10.1109/JEDS.2024.3422292","url":null,"abstract":"Flexible photodetector is crucial for the intelligent industrial applications. However, the optical-sensitive materials are usually grown in a high temperature and then transferred onto the flexible substrate. This paper reported a directly fabricated flexible photodetector based on TiO2-doped Graphene Nanosheets Embedded Carbon (GNEC)film. An Electron Cyclotron Resonance (ECR) system was employed to in-situ deposit TiO2-doped GNEC film on a polyimide substrate, which were subsequently sensitized with N719 dye to fabricate the TiO2@GNEC photodetector. The GNEC film contains vertically aligned Graphene Nanosheets (GNs), which exhibit high-density edge states. The edge states suppress the recombination rate of photo-generated electron-hole pairs, thereby significantly enhancing the photo-responsive performance. The photodetector demonstrates a high photo responsivity of 0.82 mA/W and a response time of 1.93 seconds. Due to the in-situ manufacturing capabilities of the ECR system, which avoids defects from secondary material transfers, the photodetector array exhibits excellent consistency and achieves clear recognition of light patterns in both flat and bent states.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10580991","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141511541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-01DOI: 10.1109/JEDS.2024.3421612
Shuxin Lin;Emad Iranmanesh;Lin Zhao;Weiwei Li;Haris Doumanidis;Hang Zhou;Kai Wang
This paper reports on an all-oxide thin film piezotronic P-N heterojunction diode incorporating vertically-stacked structure of N+-ITO/P-type nickel oxide/N-type zinc oxide as a flexible energy scavenger and its diode characteristics on signal regulation which simplifies an essential element for harvesting which is signal rectification circuitry. An energy band diagram, theoretical modeling and equivalent small-signal circuit elaborate its working principle and device physics. Signal amplification due to introduction of in-series capacitances related to junction formation has also been addressed. A preliminary experimental study demonstrates applicability of such a flexible energy scavenger in various gratis non-stop thrusts originating from human body motions such as: simple tapping (as in typing) and walking actions for generating $mu $ W-range power. Moreover, focusing on a simple power management system along with analysis of voltage waveforms in response to both resistive and capacitive loads unveils that the device is capable of quickly charging a capacitor and discharging it slowly allowing for possible energy storage. The estimation on generated power by a pixelated array that is obtainable due to ease of large-area fabrication processes and a single-pixel strip-based device exabits its feasibility as an energy source to power up some IoT nodes.
本文介绍了一种全氧化物薄膜压电 P-N 异质结二极管，它采用 N+-ITO/P 型氧化镍/N 型氧化锌的垂直叠层结构作为柔性能量清除器，其二极管在信号调节方面的特性简化了信号整流电路这一采集的基本要素。能带图、理论建模和等效小信号电路阐述了其工作原理和器件物理特性。此外，还讨论了由于引入与结形成相关的串联电容而导致的信号放大。初步实验研究表明，这种柔性能量清除器适用于源于人体运动的各种无偿不间断推力，例如：简单的敲击（如打字）和行走动作，以产生 $mu $ W 范围的功率。此外，对简单电源管理系统的关注，以及对响应电阻和电容负载的电压波形的分析，揭示了该设备能够对电容器快速充电和缓慢放电，从而实现可能的能量存储。由于大面积制造工艺和基于单像素条带的设备非常容易实现，因此对像素阵列产生的功率进行了估算，从而证明了其作为一种能源为某些物联网节点供电的可行性。
{"title":"Piezotronic N+ -ITO/P-NiO/N-ZnO Heterojunction Thin-Film Diode as a Flexible Energy Scavenger","authors":"Shuxin Lin;Emad Iranmanesh;Lin Zhao;Weiwei Li;Haris Doumanidis;Hang Zhou;Kai Wang","doi":"10.1109/JEDS.2024.3421612","DOIUrl":"10.1109/JEDS.2024.3421612","url":null,"abstract":"This paper reports on an all-oxide thin film piezotronic P-N heterojunction diode incorporating vertically-stacked structure of N+-ITO/P-type nickel oxide/N-type zinc oxide as a flexible energy scavenger and its diode characteristics on signal regulation which simplifies an essential element for harvesting which is signal rectification circuitry. An energy band diagram, theoretical modeling and equivalent small-signal circuit elaborate its working principle and device physics. Signal amplification due to introduction of in-series capacitances related to junction formation has also been addressed. A preliminary experimental study demonstrates applicability of such a flexible energy scavenger in various gratis non-stop thrusts originating from human body motions such as: simple tapping (as in typing) and walking actions for generating \u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 W-range power. Moreover, focusing on a simple power management system along with analysis of voltage waveforms in response to both resistive and capacitive loads unveils that the device is capable of quickly charging a capacitor and discharging it slowly allowing for possible energy storage. The estimation on generated power by a pixelated array that is obtainable due to ease of large-area fabrication processes and a single-pixel strip-based device exabits its feasibility as an energy source to power up some IoT nodes.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10579821","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141511542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-24DOI: 10.1109/JEDS.2024.3417994
Ji-Hwan Park;Kyeong-Soo Kang;Chanjin Park;Soo-Yeon Lee
In this paper, we proposed a new low-temperature polycrystalline oxide (LTPO) thin-film transistor (TFT) pixel circuit for micro light-emitting diode (μ LED) displays that produces a highly stable and uniform driving current. The proposed pixel circuit suppresses the current level change along with the sweep signal due to the parasitic capacitances and compensates for the TFT's threshold voltage (VTH) variation-induced current error, including even falling shape. In addition, the proposed circuit produces a constant current regardless of the data voltage. As a result, a relative current error rate of less than 2% was achieved across all gray levels under the ±0.5 V VTH fluctuation. The proposed circuit was verified using HSPICE with a low-temperature polycrystalline silicon (LTPS) TFT and amorphous indium-galliumzinc- oxide (a-IGZO) TFT model based on the measured data. The simulation analysis confirmed that the optimal sweep signal input position and pulse width modulation (PWM) and constant current generation (CCG) parts connecting method were key design points for stable and uniform performance.
{"title":"A New 13T4C LTPO MicroLED Pixel Circuit Producing Highly Stable Driving Current by Minimizing Effect of Parasitic Capacitors and Stabilizing Capacitor Nodes","authors":"Ji-Hwan Park;Kyeong-Soo Kang;Chanjin Park;Soo-Yeon Lee","doi":"10.1109/JEDS.2024.3417994","DOIUrl":"10.1109/JEDS.2024.3417994","url":null,"abstract":"In this paper, we proposed a new low-temperature polycrystalline oxide (LTPO) thin-film transistor (TFT) pixel circuit for micro light-emitting diode (μ LED) displays that produces a highly stable and uniform driving current. The proposed pixel circuit suppresses the current level change along with the sweep signal due to the parasitic capacitances and compensates for the TFT's threshold voltage (VTH) variation-induced current error, including even falling shape. In addition, the proposed circuit produces a constant current regardless of the data voltage. As a result, a relative current error rate of less than 2% was achieved across all gray levels under the ±0.5 V VTH fluctuation. The proposed circuit was verified using HSPICE with a low-temperature polycrystalline silicon (LTPS) TFT and amorphous indium-galliumzinc- oxide (a-IGZO) TFT model based on the measured data. The simulation analysis confirmed that the optimal sweep signal input position and pulse width modulation (PWM) and constant current generation (CCG) parts connecting method were key design points for stable and uniform performance.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10568954","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141608753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Using a 3-D monolithic stacking memory technology of crystalline oxide semiconductor (OS) transistors, we fabricated a test chip having AI accelerator (ACC) memory for weight data of a neural network (NN), backup memory of flip-flops (FF), and CPU memory storing instructions and data. These memories are composed of two-layer OS transistors on Si CMOS, where memories in each layer correspond to a bank. In this structure, bank switching of the ACC memory and the FF backup memory work together, and thus inference of different NNs is switched with low latency and low power so that the power gating standby time can be extended. Consequently, a 92% reduction in power consumption is achieved in inference at a frame rate of 60 fps as compared with a chip using static random access memory (SRAM) as the ACC memory.
利用晶体氧化物半导体（OS）晶体管的三维单片堆叠存储器技术，我们制造出了一款测试芯片，其中包括用于神经网络（NN）权重数据的人工智能加速器（ACC）存储器、触发器（FF）备份存储器以及存储指令和数据的 CPU 存储器。这些存储器由 Si CMOS 上的两层 OS 晶体管组成，每一层的存储器对应一个组。在这种结构中，ACC 存储器和 FF 备用存储器的组切换是协同工作的，因此不同 NN 的推理切换具有低延迟和低功耗的特点，从而延长了电源门控的待机时间。因此，与使用静态随机存取存储器（SRAM）作为 ACC 存储器的芯片相比，在帧速率为 60 fps 的推理过程中，功耗降低了 92%。
{"title":"A 3-D Bank Memory System for Low-Power Neural Network Processing Achieved by Instant Context Switching and Extended Power Gating Time","authors":"Kouhei Toyotaka;Yuto Yakubo;Kazuma Furutani;Haruki Katagiri;Masashi Fujita;Yoshinori Ando;Toru Nakura;Shunpei Yamazaki","doi":"10.1109/JEDS.2024.3418036","DOIUrl":"10.1109/JEDS.2024.3418036","url":null,"abstract":"Using a 3-D monolithic stacking memory technology of crystalline oxide semiconductor (OS) transistors, we fabricated a test chip having AI accelerator (ACC) memory for weight data of a neural network (NN), backup memory of flip-flops (FF), and CPU memory storing instructions and data. These memories are composed of two-layer OS transistors on Si CMOS, where memories in each layer correspond to a bank. In this structure, bank switching of the ACC memory and the FF backup memory work together, and thus inference of different NNs is switched with low latency and low power so that the power gating standby time can be extended. Consequently, a 92% reduction in power consumption is achieved in inference at a frame rate of 60 fps as compared with a chip using static random access memory (SRAM) as the ACC memory.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10568946","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141530352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-24DOI: 10.1109/JEDS.2024.3418212
Eunyoung Park;Hyun-Yong Yu
Recently, a new structure called PUC has been introduced, in which the periphery is located below the NAND cell to reduce chip area. However, as the SiN-based cell alloy process progresses during the NAND manufacturing process, there is a problem in that excess hydrogen is injected into the peripheral transistor, resulting in degradation of reliability. Therefore, we propose the hydrogen diffusion model in PUC to investigate the degradation of peripheral transistor by excess hydrogen using Sentaurus 3D technology Computer-Aided Design (TCAD) and suggest an optimal process to improve reliability. As a result, by applying the bonding process and adjusting the cell alloy process sequence, the amount of excess hydrogen injection is reduced by 87% and the NBTI lifetime showed about 8.3 times greater result and TDDB breakdown time improved more than 9.1 times compared to the PUC structure made through a sequential process. Additionally, this process effectively alleviates excess hydrogen injection in the NAND cell with an increased number of WL. These results could provide critical insight for designing a PUC that ensures the reliability of peripheral transistor.
{"title":"Effective Reduction of Hydrogen Diffusion and Reliability Degradation in Peripheral Transistor of Peripheral-Under-Cell (PUC) NAND Flash Memory","authors":"Eunyoung Park;Hyun-Yong Yu","doi":"10.1109/JEDS.2024.3418212","DOIUrl":"10.1109/JEDS.2024.3418212","url":null,"abstract":"Recently, a new structure called PUC has been introduced, in which the periphery is located below the NAND cell to reduce chip area. However, as the SiN-based cell alloy process progresses during the NAND manufacturing process, there is a problem in that excess hydrogen is injected into the peripheral transistor, resulting in degradation of reliability. Therefore, we propose the hydrogen diffusion model in PUC to investigate the degradation of peripheral transistor by excess hydrogen using Sentaurus 3D technology Computer-Aided Design (TCAD) and suggest an optimal process to improve reliability. As a result, by applying the bonding process and adjusting the cell alloy process sequence, the amount of excess hydrogen injection is reduced by 87% and the NBTI lifetime showed about 8.3 times greater result and TDDB breakdown time improved more than 9.1 times compared to the PUC structure made through a sequential process. Additionally, this process effectively alleviates excess hydrogen injection in the NAND cell with an increased number of WL. These results could provide critical insight for designing a PUC that ensures the reliability of peripheral transistor.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10568956","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-20DOI: 10.1109/JEDS.2024.3417521
Chanwoo Park;Seungjun Lee;Junghwan Park;Kyungjin Rim;Jihun Park;Seonggook Cho;Jongwook Jeon;Hyunbo Cho
We address the challenges associated with traditional analytical models, such as BSIM, in semiconductor device modeling. These models often face limitations in accurately representing the complex behaviors of miniaturized devices. As an alternative, Neural Compact Models (NCMs) offer improved modeling capabilities, but their effectiveness is constrained by a reliance on extensive datasets for accurate performance. In real-world scenarios, where measurements for device modeling are often limited, this dependence becomes a significant hindrance. In response, this work presents a large-scale pre-training approach for NCMs. By utilizing extensive datasets across various technology nodes, our method enables NCMs to develop a more detailed understanding of device behavior, thereby enhancing the accuracy and adaptability of MOSFET device simulations, particularly when data availability is limited. Our study illustrates the potential benefits of large-scale pre-training in enhancing the capabilities of NCMs, offering a practical solution to one of the key challenges in current device modeling practices.
{"title":"Large-Scale Training in Neural Compact Models for Accurate and Adaptable MOSFET Simulation","authors":"Chanwoo Park;Seungjun Lee;Junghwan Park;Kyungjin Rim;Jihun Park;Seonggook Cho;Jongwook Jeon;Hyunbo Cho","doi":"10.1109/JEDS.2024.3417521","DOIUrl":"10.1109/JEDS.2024.3417521","url":null,"abstract":"We address the challenges associated with traditional analytical models, such as BSIM, in semiconductor device modeling. These models often face limitations in accurately representing the complex behaviors of miniaturized devices. As an alternative, Neural Compact Models (NCMs) offer improved modeling capabilities, but their effectiveness is constrained by a reliance on extensive datasets for accurate performance. In real-world scenarios, where measurements for device modeling are often limited, this dependence becomes a significant hindrance. In response, this work presents a large-scale pre-training approach for NCMs. By utilizing extensive datasets across various technology nodes, our method enables NCMs to develop a more detailed understanding of device behavior, thereby enhancing the accuracy and adaptability of MOSFET device simulations, particularly when data availability is limited. Our study illustrates the potential benefits of large-scale pre-training in enhancing the capabilities of NCMs, offering a practical solution to one of the key challenges in current device modeling practices.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10566861","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141511543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-19DOI: 10.1109/JEDS.2024.3416441
Musaib Rafiq;Yogesh Singh Chauhan;Shubham Sahay
The developments in the nascent field of artificial-intelligence-of-things (AIoT) relies heavily on the availability of high-quality multi-dimensional data. A huge amount of data is being collected in this era of big data, predominantly for AI/ML algorithms and emerging applications. Considering such voluminous quantities, the collected data may contain a substantial number of outliers which must be detected before utilizing them for data mining or computations. Therefore, outlier detection techniques such as Mahalanobis distance computation have gained significant popularity recently. Mahalanobis distance, the multivariate equivalent of the Euclidean distance, is used to detect the outliers in the correlated data accurately and finds widespread application in fault identification, data clustering, singleclass classification, information security, data mining, etc. However, traditional CMOS-based approaches to compute Mahalanobis distance are bulky and consume a huge amount of energy. Therefore, there is an urgent need for a compact and energy-efficient implementation of an outlier detection technique which may be deployed on AIoT primitives, including wireless sensor nodes for in-situ outlier detection and generation of high-quality data. To this end, in this paper, for the first time, we have proposed an efficient Ferroelectric FinFET-based implementation for detecting outliers in correlated multivariate data using Mahalanobis distance. The proposed implementation utilizes two crossbar arrays of ferroelectric FinFETs to calculate the Mahalanobis distance and detect outliers in the popular Wisconsin breast cancer dataset using a novel inverter-based threshold circuit. Our implementation exhibits an accuracy of 94.1% which is comparable to the software implementations while consuming a significantly low energy (27.2 pJ).
{"title":"Efficient Implementation of Mahalanobis Distance on Ferroelectric FinFET Crossbar for Outlier Detection","authors":"Musaib Rafiq;Yogesh Singh Chauhan;Shubham Sahay","doi":"10.1109/JEDS.2024.3416441","DOIUrl":"10.1109/JEDS.2024.3416441","url":null,"abstract":"The developments in the nascent field of artificial-intelligence-of-things (AIoT) relies heavily on the availability of high-quality multi-dimensional data. A huge amount of data is being collected in this era of big data, predominantly for AI/ML algorithms and emerging applications. Considering such voluminous quantities, the collected data may contain a substantial number of outliers which must be detected before utilizing them for data mining or computations. Therefore, outlier detection techniques such as Mahalanobis distance computation have gained significant popularity recently. Mahalanobis distance, the multivariate equivalent of the Euclidean distance, is used to detect the outliers in the correlated data accurately and finds widespread application in fault identification, data clustering, singleclass classification, information security, data mining, etc. However, traditional CMOS-based approaches to compute Mahalanobis distance are bulky and consume a huge amount of energy. Therefore, there is an urgent need for a compact and energy-efficient implementation of an outlier detection technique which may be deployed on AIoT primitives, including wireless sensor nodes for in-situ outlier detection and generation of high-quality data. To this end, in this paper, for the first time, we have proposed an efficient Ferroelectric FinFET-based implementation for detecting outliers in correlated multivariate data using Mahalanobis distance. The proposed implementation utilizes two crossbar arrays of ferroelectric FinFETs to calculate the Mahalanobis distance and detect outliers in the popular Wisconsin breast cancer dataset using a novel inverter-based threshold circuit. Our implementation exhibits an accuracy of 94.1% which is comparable to the software implementations while consuming a significantly low energy (27.2 pJ).","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10563982","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141867461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present chemical beam vapor deposition (CBVD) as a valuable technique for the fabrication of good quality HfO2-based memristors. This deposition technique gives the opportunity to rapidly screen material properties in combinatorial mode and to reproduce the optimized conditions homogenously on large substrates. Cu/HfO2/Pt memory devices with three different oxide thicknesses were fabricated and electrically characterized. A bipolar resistive switching and forming free behavior was seen in all the tested devices. Lower switching voltages than similar devices fabricated by employing different deposition techniques were observed. The conduction mechanism in the low resistance state can be ascribed to filamentary copper, while a trap-controlled space charge limited current conduction was observed in the high resistance state. The comparative evaluation of devices with different oxide thicknesses allows to infer that devices with thicker HfO2 film (25 nm) are more performing in terms of ROFF/RON ratio ( $10{^{{6}}}$ ), and reproducible resistive switching over more than 100 cycles in both low and high resistance states. Thinner oxide devices (20 nm and 16 nm), despite similar long retention time ( $10{^{{4}}}$ s), and lower SET/RESET voltages show instead a smaller memory window and a switching instability. These results, compared also with other reported in literature for similar memristive structures realized with other deposition techniques, show that CBVD can be considered as a promising technique for realizing HfO2-based non-volatile memory devices with good performance.
{"title":"HfO₂ Thin Films by Chemical Beam Vapor Deposition for Large Resistive Switching Memristors","authors":"Federico Vittorio Lupo;Mauro Mosca;Sarunas Bagdzevicius;Rashmi Rani;William Maudez;Estelle Wagner;Maria Pia Casaletto;Salvatore Basile;Giacomo Benvenuti;Isodiana Crupi;Roberto Macaluso","doi":"10.1109/JEDS.2024.3416516","DOIUrl":"10.1109/JEDS.2024.3416516","url":null,"abstract":"We present chemical beam vapor deposition (CBVD) as a valuable technique for the fabrication of good quality HfO2-based memristors. This deposition technique gives the opportunity to rapidly screen material properties in combinatorial mode and to reproduce the optimized conditions homogenously on large substrates. Cu/HfO2/Pt memory devices with three different oxide thicknesses were fabricated and electrically characterized. A bipolar resistive switching and forming free behavior was seen in all the tested devices. Lower switching voltages than similar devices fabricated by employing different deposition techniques were observed. The conduction mechanism in the low resistance state can be ascribed to filamentary copper, while a trap-controlled space charge limited current conduction was observed in the high resistance state. The comparative evaluation of devices with different oxide thicknesses allows to infer that devices with thicker HfO2 film (25 nm) are more performing in terms of ROFF/RON ratio (\u0000<inline-formula> <tex-math>$10{^{{6}}}$ </tex-math></inline-formula>\u0000), and reproducible resistive switching over more than 100 cycles in both low and high resistance states. Thinner oxide devices (20 nm and 16 nm), despite similar long retention time (\u0000<inline-formula> <tex-math>$10{^{{4}}}$ </tex-math></inline-formula>\u0000 s), and lower SET/RESET voltages show instead a smaller memory window and a switching instability. These results, compared also with other reported in literature for similar memristive structures realized with other deposition techniques, show that CBVD can be considered as a promising technique for realizing HfO2-based non-volatile memory devices with good performance.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10563993","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141780665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-18DOI: 10.1109/JEDS.2024.3416200
Murad G. K. Alabdullah;M. A. Elmessary;D. Nagy;N. Seoane;A. J. García-Loureiro;K. Kalna
The scaling of nanosheet (NS) field effect transistors (FETs) from the 12 nm gate length to the ultimate gate length of 10 nm for sub-2 nm nodes brings additional technological challenges. Here, 3D finite element Monte Carlo simulations are employed to explore how to alter the NS architecture to increase the drive current ( ${I}_{mathrm {mathbf { DD}}}$ ) because the gate scaling to 10 nm results in a decline of the current (by $mathbf {10.7}$ %). ${I}_{mathrm {mathbf {DD}}}$ of the 10 nm gate length NS FET will increase by 11% if the maximum n-type source/drain doping reaches $1times 10^{20} mathrm {cm^{-3}}$ , or increase by $mathbf {3.8}$ % if the high- $kappa $ dielectric layer equivalent oxide thickness (EOT) is less than $mathbf {1.0}$ nm. The reduction in the channel width below 40 nm or the reduction in the channel thickness below 5 nm will substantially decrease IDD. The sub-threshold figures of merit like the sub-threshold slope (SS) will decrease from 75 to 73 mV/dec, while the drain-induced barrier lowering (DIBL) will increase from 32 to 77 mV/V. Finally, the effect of strain to increase the drive current is strongly limited by quantum confinement. ${I}_{mathrm {mathbf {DD}}}$ will increase by 3% and by 14% in the 10 nm gate NS FET with the $langle 110rangle $ and $langle 100rangle $ channel orientations, respectively, when a strain of $mathbf {0.5}$ % is applied to the channel, with a negligible increase for larger strain values ( $mathbf {0.7}$ % and $mathbf {1.0}$ %).
{"title":"Scaling Challenges of Nanosheet Field-Effect Transistors Into Sub-2 nm Nodes","authors":"Murad G. K. Alabdullah;M. A. Elmessary;D. Nagy;N. Seoane;A. J. García-Loureiro;K. Kalna","doi":"10.1109/JEDS.2024.3416200","DOIUrl":"https://doi.org/10.1109/JEDS.2024.3416200","url":null,"abstract":"The scaling of nanosheet (NS) field effect transistors (FETs) from the 12 nm gate length to the ultimate gate length of 10 nm for sub-2 nm nodes brings additional technological challenges. Here, 3D finite element Monte Carlo simulations are employed to explore how to alter the NS architecture to increase the drive current (\u0000<inline-formula> <tex-math>${I}_{mathrm {mathbf { DD}}}$ </tex-math></inline-formula>\u0000) because the gate scaling to 10 nm results in a decline of the current (by \u0000<inline-formula> <tex-math>$mathbf {10.7}$ </tex-math></inline-formula>\u0000%). \u0000<inline-formula> <tex-math>${I}_{mathrm {mathbf {DD}}}$ </tex-math></inline-formula>\u0000 of the 10 nm gate length NS FET will increase by 11% if the maximum n-type source/drain doping reaches \u0000<inline-formula> <tex-math>$1times 10^{20} mathrm {cm^{-3}}$ </tex-math></inline-formula>\u0000, or increase by \u0000<inline-formula> <tex-math>$mathbf {3.8}$ </tex-math></inline-formula>\u0000% if the high-\u0000<inline-formula> <tex-math>$kappa $ </tex-math></inline-formula>\u0000 dielectric layer equivalent oxide thickness (EOT) is less than \u0000<inline-formula> <tex-math>$mathbf {1.0}$ </tex-math></inline-formula>\u0000 nm. The reduction in the channel width below 40 nm or the reduction in the channel thickness below 5 nm will substantially decrease IDD. The sub-threshold figures of merit like the sub-threshold slope (SS) will decrease from 75 to 73 mV/dec, while the drain-induced barrier lowering (DIBL) will increase from 32 to 77 mV/V. Finally, the effect of strain to increase the drive current is strongly limited by quantum confinement. \u0000<inline-formula> <tex-math>${I}_{mathrm {mathbf {DD}}}$ </tex-math></inline-formula>\u0000 will increase by 3% and by 14% in the 10 nm gate NS FET with the \u0000<inline-formula> <tex-math>$langle 110rangle $ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$langle 100rangle $ </tex-math></inline-formula>\u0000 channel orientations, respectively, when a strain of \u0000<inline-formula> <tex-math>$mathbf {0.5}$ </tex-math></inline-formula>\u0000% is applied to the channel, with a negligible increase for larger strain values (\u0000<inline-formula> <tex-math>$mathbf {0.7}$ </tex-math></inline-formula>\u0000% and \u0000<inline-formula> <tex-math>$mathbf {1.0}$ </tex-math></inline-formula>\u0000%).","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10561475","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141631061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-17DOI: 10.1109/JEDS.2024.3404595
Liufei Zhou;Fuchao He;Xiaojun Guo;Haihong Wang;Mingxin Wang;Yuning Zhang;Baoping Wang
In this paper, we propose a bidirectional gate driver on array (GOA) circuit design based on indium gallium zinc oxide (IGZO) thin-film transistor (TFT) to support time-division driving method (TDDM) for in-cell touch displays. The proposed circuit allows the touch panel to pause the display for touch sensing operations to achieve a touch reporting rate as twice as the frame rate of a display. A dual low-level maintaining unit design is used to suppress influence of the threshold voltage shift of TFTs through alternately turning on the devices. Owing to recovery of threshold voltage shift under negative bias, this design can maintain stable performance during long time operation. A narrow border 6.5” in-cell LCD panel of 90 Hz display with a 180 Hz touch reporting rate is finally demonstrated.
{"title":"Robust Bidirectional Gate Driver on Array Based on Indium Gallium Zinc Oxide Thin-Film Transistor for In-Cell Touch Displays","authors":"Liufei Zhou;Fuchao He;Xiaojun Guo;Haihong Wang;Mingxin Wang;Yuning Zhang;Baoping Wang","doi":"10.1109/JEDS.2024.3404595","DOIUrl":"10.1109/JEDS.2024.3404595","url":null,"abstract":"In this paper, we propose a bidirectional gate driver on array (GOA) circuit design based on indium gallium zinc oxide (IGZO) thin-film transistor (TFT) to support time-division driving method (TDDM) for in-cell touch displays. The proposed circuit allows the touch panel to pause the display for touch sensing operations to achieve a touch reporting rate as twice as the frame rate of a display. A dual low-level maintaining unit design is used to suppress influence of the threshold voltage shift of TFTs through alternately turning on the devices. Owing to recovery of threshold voltage shift under negative bias, this design can maintain stable performance during long time operation. A narrow border 6.5” in-cell LCD panel of 90 Hz display with a 180 Hz touch reporting rate is finally demonstrated.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2024-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10559899","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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