Pub Date : 2022-01-01DOI: 10.1587/elex.19.20220163
Peiyong Zhang, Yuquan Su, Yike Li, Kaitian Huang
Arc faults in power systems may cause significant damage to equipment and even lead to electrical fires and hazard for personnel if they are not detected and isolated promptly. The series arc fault in a distribution system can be more dangerous compared to the parallel arc fault, because its low fault current will hinder the circuit breakers from responding in a timely manner. Therefore, it is necessary to properly detect the series arc fault. In this paper, a system-on-chip (SoC) for series AC arc fault acquisition is presented, which is based on two channels of configurable sampling rate successive approximation register (SAR) analog-to-digital-converters (ADCs). As the arc faults with different loads have different characteristics and may need a higher sampling rate under some circumstances, the adjustable sampling rate can meet varying needs. The system is implemented using a 55 nm CMOS process with a die area of 4.683 mm 2 and power dissipation of 75.9 mW. The proposed SAR ADC design can achieve a good Schreier figure-of-merit (FoM) of 161 dB at 1 MS/s sampling rate. With this ADC design, the SoC can complete arc faults acquisition with high precision and configurable sampling rate at a low cost. Meanwhile, the system can sample voltage and current signals from the smart grid respectively to initially locate the arc fault. words:
{"title":"A system-on-chip for series arc fault acquisition in smart grid based on two configurable sampling rate SAR ADCs","authors":"Peiyong Zhang, Yuquan Su, Yike Li, Kaitian Huang","doi":"10.1587/elex.19.20220163","DOIUrl":"https://doi.org/10.1587/elex.19.20220163","url":null,"abstract":"Arc faults in power systems may cause significant damage to equipment and even lead to electrical fires and hazard for personnel if they are not detected and isolated promptly. The series arc fault in a distribution system can be more dangerous compared to the parallel arc fault, because its low fault current will hinder the circuit breakers from responding in a timely manner. Therefore, it is necessary to properly detect the series arc fault. In this paper, a system-on-chip (SoC) for series AC arc fault acquisition is presented, which is based on two channels of configurable sampling rate successive approximation register (SAR) analog-to-digital-converters (ADCs). As the arc faults with different loads have different characteristics and may need a higher sampling rate under some circumstances, the adjustable sampling rate can meet varying needs. The system is implemented using a 55 nm CMOS process with a die area of 4.683 mm 2 and power dissipation of 75.9 mW. The proposed SAR ADC design can achieve a good Schreier figure-of-merit (FoM) of 161 dB at 1 MS/s sampling rate. With this ADC design, the SoC can complete arc faults acquisition with high precision and configurable sampling rate at a low cost. Meanwhile, the system can sample voltage and current signals from the smart grid respectively to initially locate the arc fault. words:","PeriodicalId":13437,"journal":{"name":"IEICE Electron. Express","volume":"294 1","pages":"20220163"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79545257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To improve the steady-state performance of the dual three-phase permanent magnet synchronous motor with high torque ripple and high harmonic current, this paper proposes a hybrid voltage vector model predictive current control algorithm (MPCC). Firstly, based on the virtual voltage vectors synthesized using the vector characteristics of the fundamental and harmonic subspaces, hybrid voltage vectors are synthesized from the virtual voltage vectors and the zero vector to increase the voltage vector amplitude range to reduce torque ripple and to suppress harmonic currents. Then a vector selection method is proposed to reduce the number of alternative vectors and the calculation burden of the MPCC. Finally, the realization of corresponding PWM modulation is given. The simulation results show that the method effectively suppresses harmonic currents and torque ripple and increases the steady-state performance of the motor.
{"title":"Model predictive current control for dual three-phase PMSM with hybrid voltage vector","authors":"Fenghuang Cai, Fuyang Yang, Qinqin Chai, Jiahui Jiang","doi":"10.1587/elex.19.20220340","DOIUrl":"https://doi.org/10.1587/elex.19.20220340","url":null,"abstract":"To improve the steady-state performance of the dual three-phase permanent magnet synchronous motor with high torque ripple and high harmonic current, this paper proposes a hybrid voltage vector model predictive current control algorithm (MPCC). Firstly, based on the virtual voltage vectors synthesized using the vector characteristics of the fundamental and harmonic subspaces, hybrid voltage vectors are synthesized from the virtual voltage vectors and the zero vector to increase the voltage vector amplitude range to reduce torque ripple and to suppress harmonic currents. Then a vector selection method is proposed to reduce the number of alternative vectors and the calculation burden of the MPCC. Finally, the realization of corresponding PWM modulation is given. The simulation results show that the method effectively suppresses harmonic currents and torque ripple and increases the steady-state performance of the motor.","PeriodicalId":13437,"journal":{"name":"IEICE Electron. Express","volume":"20 1","pages":"20220340"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89540589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nowadays , data centers are critical infrastructure for the information industry. Thermal security is one of the most concerning problems of the data center efficiently providing service. The temperature prediction method is an effective way, which overcomes the lagging of the feedback control and rewards a high prediction accuracy. While the current LSTM based prediction methods are limited in accuracy and restricted in scalability due to the lack of knowledge of physical properties and consideration of time constant differences of features. To address this, we propose a data center temperature prediction model with two-segment LSTM for prediction separately for IT equipment load and other heat-related variables with different time constants. The model takes into account the physical properties of the equipment and achieves higher prediction accuracy. The experimental results show that the prediction accuracy of our method is 27.27% higher than the state-of-art single segment LSTM method.
{"title":"A two-segment LSTM based data center temperature prediction model","authors":"Yifei Kang, Chunping Ma, Simin Wang, Weiguo Wu, Kangning Zhao","doi":"10.1587/elex.19.20220291","DOIUrl":"https://doi.org/10.1587/elex.19.20220291","url":null,"abstract":"Nowadays , data centers are critical infrastructure for the information industry. Thermal security is one of the most concerning problems of the data center efficiently providing service. The temperature prediction method is an effective way, which overcomes the lagging of the feedback control and rewards a high prediction accuracy. While the current LSTM based prediction methods are limited in accuracy and restricted in scalability due to the lack of knowledge of physical properties and consideration of time constant differences of features. To address this, we propose a data center temperature prediction model with two-segment LSTM for prediction separately for IT equipment load and other heat-related variables with different time constants. The model takes into account the physical properties of the equipment and achieves higher prediction accuracy. The experimental results show that the prediction accuracy of our method is 27.27% higher than the state-of-art single segment LSTM method.","PeriodicalId":13437,"journal":{"name":"IEICE Electron. Express","volume":"30 1","pages":"20220291"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76687350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-01-01DOI: 10.1587/elex.19.20220280
Fuyue Qian, Ye Li, Xiaowei Zhang, Jianxiong Xi, Lenian He
{"title":"An all-digital CMOS temperature sensor with a wide supply voltage range","authors":"Fuyue Qian, Ye Li, Xiaowei Zhang, Jianxiong Xi, Lenian He","doi":"10.1587/elex.19.20220280","DOIUrl":"https://doi.org/10.1587/elex.19.20220280","url":null,"abstract":"","PeriodicalId":13437,"journal":{"name":"IEICE Electron. Express","volume":"40 1","pages":"20220280"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76825547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-01-01DOI: 10.1587/elex.19.20220390
Wenxin Yu, Lenian He, Jianxiong Xi, Quan Sun, Changyou Men
This paper presents a high-precision bandgap voltage reference (BGR) with a double-ended current trimming technique. A high-order curvature compensation method is adopted to compensate for the nonlinearity of V BE . The proposed trimming technique using the one-time programmable (OTP) programming cancels the errors caused by process variation and enables bulk production, which achieves a best TC of 2.2 ppm/℃ from -40 ℃ to 125 ℃. The proposed BGR is fabricated in a 0.18-um BCD process with an active area of 0.329 mm 2 . The line sensitivity is 0.18 %/V operating from 2.9 V to 3.6 V.
{"title":"A 2.2ppm/°C compensated bandgap voltage reference with a double-ended current trimming technique","authors":"Wenxin Yu, Lenian He, Jianxiong Xi, Quan Sun, Changyou Men","doi":"10.1587/elex.19.20220390","DOIUrl":"https://doi.org/10.1587/elex.19.20220390","url":null,"abstract":"This paper presents a high-precision bandgap voltage reference (BGR) with a double-ended current trimming technique. A high-order curvature compensation method is adopted to compensate for the nonlinearity of V BE . The proposed trimming technique using the one-time programmable (OTP) programming cancels the errors caused by process variation and enables bulk production, which achieves a best TC of 2.2 ppm/℃ from -40 ℃ to 125 ℃. The proposed BGR is fabricated in a 0.18-um BCD process with an active area of 0.329 mm 2 . The line sensitivity is 0.18 %/V operating from 2.9 V to 3.6 V.","PeriodicalId":13437,"journal":{"name":"IEICE Electron. Express","volume":"9 1","pages":"20220390"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73140373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-01-01DOI: 10.1587/elex.18.20210493
Chenji Liu, Lan Chen, Xiaoran Hao, Mao Ni
In order to reduce the main memory energy of the IoT terminal, STT-MRAM is used to replace DRAM to save refresh energy. However, the write performance of STT-MRAM cells is worse than that of DRAM. Our previous work proposed a hybrid DRAM/STT-MRAM main memory and fast data migration to reduce the adverse effects of poor write performance of STT-MRAM cells with negligible performance overhead. This article optimizes the migration algorithm and experiment scheme: 1. Reduce the storage overhead of the algorithm. 2. Realize the continuous work of the algorithm. 3. Consider the impact of system standby time on main memory energy. The results show that compared with our previous work, the storage overhead of the algorithm is reduced 99.8%. When the system standby time is zero, the energy of the hybrid main memory (including the energy of the algorithm) is reduced by 4% on average compared to DRAM. The longer the system standby time, the more energy saving.
{"title":"Optimized fast data migration for hybrid DRAM/STT-MRAM main memory","authors":"Chenji Liu, Lan Chen, Xiaoran Hao, Mao Ni","doi":"10.1587/elex.18.20210493","DOIUrl":"https://doi.org/10.1587/elex.18.20210493","url":null,"abstract":"In order to reduce the main memory energy of the IoT terminal, STT-MRAM is used to replace DRAM to save refresh energy. However, the write performance of STT-MRAM cells is worse than that of DRAM. Our previous work proposed a hybrid DRAM/STT-MRAM main memory and fast data migration to reduce the adverse effects of poor write performance of STT-MRAM cells with negligible performance overhead. This article optimizes the migration algorithm and experiment scheme: 1. Reduce the storage overhead of the algorithm. 2. Realize the continuous work of the algorithm. 3. Consider the impact of system standby time on main memory energy. The results show that compared with our previous work, the storage overhead of the algorithm is reduced 99.8%. When the system standby time is zero, the energy of the hybrid main memory (including the energy of the algorithm) is reduced by 4% on average compared to DRAM. The longer the system standby time, the more energy saving.","PeriodicalId":13437,"journal":{"name":"IEICE Electron. Express","volume":"12 1","pages":"20210493"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72722713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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