Pub Date : 2023-04-14DOI: 10.21820/23987073.2023.2.50
Sotaro Uemura
The detection and analysis of proteins is important for science and medicine and methods for sequencing and synthesising proteins have been developed to assist with this. The analysis of single molecules provides more detailed and targeted information and the development of single-molecule techniques has helped to advance molecular research. Professor Sotaro Uemura, The University of Tokyo, Japan, has over 20 years experience in this field of research, with a focus on singling out and measuring single-molecule proteins using optical tweezers, fluorescence imaging and other techniques. Labelling is a key technology that facilitates the detection of target molecules and molecular sorting by the labelling process provides numerous advantages. However, there are restrictions to this technique, leading to Uemura's involvement in utilising label-free technology to assist in the detection and measurement of single molecules. Nanopore measurement is interesting, especially in its use as a DNA sequencer but, using this method, it isn't possible to pinpoint which molecule each signal comes from. Uemura is interested in using Artificial Intelligence (AI) as an additional analysis method that can link the signals. He is working with collaborators to use machine learning to determine which molecules are producing the signals identified by nanopore measurement.
{"title":"Comprehensive quantitative analysis of single-molecule proteins using ribosome fusion nanopore technology","authors":"Sotaro Uemura","doi":"10.21820/23987073.2023.2.50","DOIUrl":"https://doi.org/10.21820/23987073.2023.2.50","url":null,"abstract":"The detection and analysis of proteins is important for science and medicine and methods for sequencing and synthesising proteins have been developed to assist with this. The analysis of single molecules provides more detailed and targeted information and the development of single-molecule techniques has helped to advance molecular research. Professor Sotaro Uemura, The University of Tokyo, Japan, has over 20 years experience in this field of research, with a focus on singling out and measuring single-molecule proteins using optical tweezers, fluorescence imaging and other techniques. Labelling is a key technology that facilitates the detection of target molecules and molecular sorting by the labelling process provides numerous advantages. However, there are restrictions to this technique, leading to Uemura's involvement in utilising label-free technology to assist in the detection and measurement of single molecules. Nanopore measurement is interesting, especially in its use as a DNA sequencer but, using this method, it isn't possible to pinpoint which molecule each signal comes from. Uemura is interested in using Artificial Intelligence (AI) as an additional analysis method that can link the signals. He is working with collaborators to use machine learning to determine which molecules are producing the signals identified by nanopore measurement.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"84 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135035036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.21820/23987073.2023.1.12
Toshikazu Ikeda
The continuous development of education is important in order to ensure it keeps growing and improving. Professor Toshikazu Ikeda, College of Education, Yokohama National University, Japan, is a Professor of Mathematics who is a proponent of revolutionary knowledge growth through overturning, expanding, and integrating acquired knowledge and skills. This is about progression through bridging the gap between a knowledge goal and the existing knowledge base through developing techniques and pathways to that goal. Ikeda believes that by inserting revolutionary knowledge growth into the mathematics curriculum in Japan, children can be encouraged towards more independent and problem solving based thinking. He has performed an analysis of current teaching materials which involved examining local teaching materials in a specific area, using lessons to analyse and evaluate those materials and looking at long-term global teaching materials that give a deeper examination of specific topics, focusing on how and where it can be used and how students react to the content. In his work, Ikeda uses modelling as a problem solving tool and to develop techniques to deepen learning and lead to revolutionary knowledge growth. Ikeda is collaborating with Professor Max Stephens, Melbourne University, to produce lectures centred on revolutionary growth knowledge for students at teacher training colleges. A key part of Ikeda's work is teaching mathematical modelling in order to help students understand the importance of mathematics and develop their abilities.
{"title":"Development research of arithmetic and mathematics curriculum incorporating revolutionary and cumulative knowledge growth","authors":"Toshikazu Ikeda","doi":"10.21820/23987073.2023.1.12","DOIUrl":"https://doi.org/10.21820/23987073.2023.1.12","url":null,"abstract":"The continuous development of education is important in order to ensure it keeps growing and improving. Professor Toshikazu Ikeda, College of Education, Yokohama National University, Japan, is a Professor of Mathematics who is a proponent of revolutionary knowledge growth through overturning, expanding, and integrating acquired knowledge and skills. This is about progression through bridging the gap between a knowledge goal and the existing knowledge base through developing techniques and pathways to that goal. Ikeda believes that by inserting revolutionary knowledge growth into the mathematics curriculum in Japan, children can be encouraged towards more independent and problem solving based thinking. He has performed an analysis of current teaching materials which involved examining local teaching materials in a specific area, using lessons to analyse and evaluate those materials and looking at long-term global teaching materials that give a deeper examination of specific topics, focusing on how and where it can be used and how students react to the content. In his work, Ikeda uses modelling as a problem solving tool and to develop techniques to deepen learning and lead to revolutionary knowledge growth. Ikeda is collaborating with Professor Max Stephens, Melbourne University, to produce lectures centred on revolutionary growth knowledge for students at teacher training colleges. A key part of Ikeda's work is teaching mathematical modelling in order to help students understand the importance of mathematics and develop their abilities.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136390826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-02DOI: 10.1080/2058802x.2023.2210453
{"title":"Universities Making an Impact","authors":"","doi":"10.1080/2058802x.2023.2210453","DOIUrl":"https://doi.org/10.1080/2058802x.2023.2210453","url":null,"abstract":"","PeriodicalId":13517,"journal":{"name":"Impact","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135799861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966632
Gary Tsai, Denis Chen
The modern communication system, data center and electronics devices deign, are facing increasing challenges in power delivery network design, besides the well-known signal integrity design challenges. In order to make sure the designed product works well to meet design quality, normally platform design guideline will be provided bt Chip suppliers to OEMs or ODMs before OEMs/ODMs product design phase.For Power Delivery Network design, the impedance curve Z(f) from simulation of power rails (like core power, graphic power or memory power…etc.) is required to meet Chip suppliers’ impedance curve Z(f) criteria in each generation of platform. Some customers may not perform Power Integrity (PI) simulation to check if the impedance curve Z(f) of the board power routings can pass Load Line (LL) specification due to resource limitation, no matter in tools or human resource. Instead of relying on actual validation to see if any issue is related to the power rail design.From PI simulation point of view, adding more power shapes/planes or de-coupling capacitors can help to reduce Z(f) value to meet the criteria easily and get better power design quality. If the customers don’t have resource to do PI simulation, they will try to modify the power rail routings in next board re-spin (to add more planes/shapes or de-coupling capacitors) to improved power design quality when the power validation had issue. It will cause additional time and money. If one small symbol pattern can be reserved in board power layout in advanced, it can help to save the PCB re-spin time if the power design hit validation issue.
{"title":"Impedance Implementation Pattern for PCB Design","authors":"Gary Tsai, Denis Chen","doi":"10.1109/IMPACT56280.2022.9966632","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966632","url":null,"abstract":"The modern communication system, data center and electronics devices deign, are facing increasing challenges in power delivery network design, besides the well-known signal integrity design challenges. In order to make sure the designed product works well to meet design quality, normally platform design guideline will be provided bt Chip suppliers to OEMs or ODMs before OEMs/ODMs product design phase.For Power Delivery Network design, the impedance curve Z(f) from simulation of power rails (like core power, graphic power or memory power…etc.) is required to meet Chip suppliers’ impedance curve Z(f) criteria in each generation of platform. Some customers may not perform Power Integrity (PI) simulation to check if the impedance curve Z(f) of the board power routings can pass Load Line (LL) specification due to resource limitation, no matter in tools or human resource. Instead of relying on actual validation to see if any issue is related to the power rail design.From PI simulation point of view, adding more power shapes/planes or de-coupling capacitors can help to reduce Z(f) value to meet the criteria easily and get better power design quality. If the customers don’t have resource to do PI simulation, they will try to modify the power rail routings in next board re-spin (to add more planes/shapes or de-coupling capacitors) to improved power design quality when the power validation had issue. It will cause additional time and money. If one small symbol pattern can be reserved in board power layout in advanced, it can help to save the PCB re-spin time if the power design hit validation issue.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"32 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74134016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966713
Dirack Lai, Marc Chin, Zoe Liu, Rani Chen
Tabbed lines have been proposed to reduce or eliminate far-end crosstalk (FEXT) and impedance management [1], [2], [3] with the ground void beneath SMT connector landing pad implementation for DDR5 channel from simulation and tabbed transmission line measurement by a VNA or TDR. In this paper, a method to quantify the tabbed lines and ground void impact on real DDR5 eye margin is proposed. This method starts with the test board design with fours zones of tabbed, non-tabbed, void and non-void ground and follow up with impedance check by a TDR. The final step is to perform four zones memory margin result as comparison to quantify the tabbed lines and ground void impact on real DDR5 eye margin. [4], [5]. The quantified results could be good indicators for tabbed lines implementation decision and ground plane void patch mechanism.
{"title":"Quantified tabbed lines and ground void impact on real DDR5 eye margin","authors":"Dirack Lai, Marc Chin, Zoe Liu, Rani Chen","doi":"10.1109/IMPACT56280.2022.9966713","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966713","url":null,"abstract":"Tabbed lines have been proposed to reduce or eliminate far-end crosstalk (FEXT) and impedance management [1], [2], [3] with the ground void beneath SMT connector landing pad implementation for DDR5 channel from simulation and tabbed transmission line measurement by a VNA or TDR. In this paper, a method to quantify the tabbed lines and ground void impact on real DDR5 eye margin is proposed. This method starts with the test board design with fours zones of tabbed, non-tabbed, void and non-void ground and follow up with impedance check by a TDR. The final step is to perform four zones memory margin result as comparison to quantify the tabbed lines and ground void impact on real DDR5 eye margin. [4], [5]. The quantified results could be good indicators for tabbed lines implementation decision and ground plane void patch mechanism.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"13 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74234473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966692
Wen‐Chun Hsiao, Hong-Sheng Huang, Cheng-Yu Ho, Sheng-Chi Hsieh, Chen-Chao Wang
This paper discusses a 2x2 broadband dual-polarized antenna array on the 4+2+4 cost-effective multilayer organic substrates with size of 13 x 13 x 0.87 mm3. Each antenna element consists of one driven patch, one stacked patch, and four parasitic elements. This work focuses on simulating and analyzing the effect of stacking ratio of driven patch and stacked patch on operating bandwidth, and adding parasitic elements to expand the bandwidth, which achieves broadband performance on a thin and cost-effective substrate. In a single antenna element, the simulated return loss of over 10dB is achieved a frequency range from 24.60 to 29.65 GHz and the realized antenna gain is more than 5.5dBi. After that, a 2x2 antenna array is designed, which each antenna element has dual feeding ports to implement dual-polarization features. In the 24.65 to 29.65 GHz range, the simulated realized gain of array in vertical polarization and horizontal polarization is from 10.7 to 12.4 dBi. The isolation levels of port-to-port and cross-polarization are better than 18dB and 14dB in the band, respectively. Finally, the 3D beam steering is simulated in four quadrants at 27GHz, and a maximum realized gain of 11.1dBi is achieved in the beam direction (θ=28°, Φ=312°) of quadrant IV. It shows that the beamforming can work properly by controlling the phase of signal in each antenna element. The cost-effective antenna structure provides a broadband benefit to cover all the 28GHz mmWave bands of 3GPP standard (n257, n258, and n261).
{"title":"A 2x2 Broadband Dual-Polarized Antenna Array using AiP Techniques for 5G mmWave Beamforming Systems","authors":"Wen‐Chun Hsiao, Hong-Sheng Huang, Cheng-Yu Ho, Sheng-Chi Hsieh, Chen-Chao Wang","doi":"10.1109/IMPACT56280.2022.9966692","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966692","url":null,"abstract":"This paper discusses a 2x2 broadband dual-polarized antenna array on the 4+2+4 cost-effective multilayer organic substrates with size of 13 x 13 x 0.87 mm3. Each antenna element consists of one driven patch, one stacked patch, and four parasitic elements. This work focuses on simulating and analyzing the effect of stacking ratio of driven patch and stacked patch on operating bandwidth, and adding parasitic elements to expand the bandwidth, which achieves broadband performance on a thin and cost-effective substrate. In a single antenna element, the simulated return loss of over 10dB is achieved a frequency range from 24.60 to 29.65 GHz and the realized antenna gain is more than 5.5dBi. After that, a 2x2 antenna array is designed, which each antenna element has dual feeding ports to implement dual-polarization features. In the 24.65 to 29.65 GHz range, the simulated realized gain of array in vertical polarization and horizontal polarization is from 10.7 to 12.4 dBi. The isolation levels of port-to-port and cross-polarization are better than 18dB and 14dB in the band, respectively. Finally, the 3D beam steering is simulated in four quadrants at 27GHz, and a maximum realized gain of 11.1dBi is achieved in the beam direction (θ=28°, Φ=312°) of quadrant IV. It shows that the beamforming can work properly by controlling the phase of signal in each antenna element. The cost-effective antenna structure provides a broadband benefit to cover all the 28GHz mmWave bands of 3GPP standard (n257, n258, and n261).","PeriodicalId":13517,"journal":{"name":"Impact","volume":"115 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75049217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/impact56280.2022.9966705
Chen-xi Xie, Jie-Guo, Mei-Juan Kuang
As the high-end rigid flexible board (R-F board) widely used in the automotive electronics, industry control systems and smart medical products, the reliability of R-F board is becoming more and more important. FCCL is a very important material in the stack up of R-F board. As we know, PI has excellent heat resistance, electric property, mechanical property and flame retardancy, because of the amazing physical property and chemical property, PI is broadly applied in all kinds of situation. However, the biggest disadvantage of PI is that it is easy to absorb moisture. When the R-F board undergoes reflow of SMT, the water in PI will tum into water vapor at high temperature, resulting in the delamination between PI and copper foil because of rapidly increased stress of water vapor. In this situation, not only it brings serious economic loss but also affect efficiency. This study is aiming at the root of delamination of FCCL. We mainly study the type of PI, design of grid copper, water absorption and baking before SMT with DOE analysis, to find how these factors affect the delamination of FCCL. We hope this paper can provide reference for engineers in the industry of PCB and SMT.
{"title":"Root Cause of Analysis on the FCCL Delamination of Rigid Flexible Board","authors":"Chen-xi Xie, Jie-Guo, Mei-Juan Kuang","doi":"10.1109/impact56280.2022.9966705","DOIUrl":"https://doi.org/10.1109/impact56280.2022.9966705","url":null,"abstract":"As the high-end rigid flexible board (R-F board) widely used in the automotive electronics, industry control systems and smart medical products, the reliability of R-F board is becoming more and more important. FCCL is a very important material in the stack up of R-F board. As we know, PI has excellent heat resistance, electric property, mechanical property and flame retardancy, because of the amazing physical property and chemical property, PI is broadly applied in all kinds of situation. However, the biggest disadvantage of PI is that it is easy to absorb moisture. When the R-F board undergoes reflow of SMT, the water in PI will tum into water vapor at high temperature, resulting in the delamination between PI and copper foil because of rapidly increased stress of water vapor. In this situation, not only it brings serious economic loss but also affect efficiency. This study is aiming at the root of delamination of FCCL. We mainly study the type of PI, design of grid copper, water absorption and baking before SMT with DOE analysis, to find how these factors affect the delamination of FCCL. We hope this paper can provide reference for engineers in the industry of PCB and SMT.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"75 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80499114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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