Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966684
Chun-Kai Liu, Tan-Yi Chang
Thermal management is a key bottleneck of technology development in data center systems. Immersion cooling eliminates the thermal interface material and packaging limitations of conventional cooling methods. Single-phase immersion liquid cooling is limited to lower heat transfer coefficients. However, two-phase immersion cooling has emerged as a potential solution to overcome thermal limitations by boiling the coolant directly from the electronic components, thereby increasing heat convection. In this paper, we study the thermal and flow characteristics of electronic components in single-phase and two-phase immersion cooling by numerical simulation. We simulated the multi-heat sources on PCB with different heating power. Dielectric fluid is used for direct liquid cooling of electronic components. The cooling performance of heat sources with single and two-phase immersion cooling are compared and studied.
{"title":"Thermal Performance of Single-Phase and Two-Phase Immersion Cooling in Data Center","authors":"Chun-Kai Liu, Tan-Yi Chang","doi":"10.1109/IMPACT56280.2022.9966684","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966684","url":null,"abstract":"Thermal management is a key bottleneck of technology development in data center systems. Immersion cooling eliminates the thermal interface material and packaging limitations of conventional cooling methods. Single-phase immersion liquid cooling is limited to lower heat transfer coefficients. However, two-phase immersion cooling has emerged as a potential solution to overcome thermal limitations by boiling the coolant directly from the electronic components, thereby increasing heat convection. In this paper, we study the thermal and flow characteristics of electronic components in single-phase and two-phase immersion cooling by numerical simulation. We simulated the multi-heat sources on PCB with different heating power. Dielectric fluid is used for direct liquid cooling of electronic components. The cooling performance of heat sources with single and two-phase immersion cooling are compared and studied.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"35 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82179342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966706
Ya-Huei Erica Chang, Dih-Yang Andy Kuo, Jhih Wei Gwako Liang, K. Yamazaki, Jay Zhang, Hitoshi Sakoda, Norio Kamitsubo
Anodic bonding has been extensively used to permanently bond glass to silicon (Si) wafer for MEMS (microelectromechanical systems)-based sensor applications. This approach involves the alkali ion migration (such as Li, Na, and K) under high-temperature, high pressure, and high voltage. Moreover, similar coefficients of thermal expansion (CTE) are required to bond these two heterogeneous substrates over a wide range of temperatures. However, some active or passive devices in MEMS are temperature sensitive and those alkali ions from glass could exhibit undesirable side effects to degrade the device performance when subjected to moisture and heat. The low-temperature direct bonding processes for an alkali-free glass wafer to another Si wafer hence has been studied recently.
{"title":"Low Temperature Fusion Bonding of Glass to Si Using Plasma Activation","authors":"Ya-Huei Erica Chang, Dih-Yang Andy Kuo, Jhih Wei Gwako Liang, K. Yamazaki, Jay Zhang, Hitoshi Sakoda, Norio Kamitsubo","doi":"10.1109/IMPACT56280.2022.9966706","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966706","url":null,"abstract":"Anodic bonding has been extensively used to permanently bond glass to silicon (Si) wafer for MEMS (microelectromechanical systems)-based sensor applications. This approach involves the alkali ion migration (such as Li, Na, and K) under high-temperature, high pressure, and high voltage. Moreover, similar coefficients of thermal expansion (CTE) are required to bond these two heterogeneous substrates over a wide range of temperatures. However, some active or passive devices in MEMS are temperature sensitive and those alkali ions from glass could exhibit undesirable side effects to degrade the device performance when subjected to moisture and heat. The low-temperature direct bonding processes for an alkali-free glass wafer to another Si wafer hence has been studied recently.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"77 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89035762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Insertion loss of a testing vehicle is widely referred for the material estimation, the differential pair and single-end striplines are generally employed for the high-speed digital applications. In addition to the matte side, the shiny side with the surface treatment of the inner layer is the critical issue for the insertion-loss improvement. In general, the inner-layer roughness is determined by the cross-section scanning electron or optical microscope photo with the manual defining of the average line. Therefore, the tolerance is produced from personal operation or gage repeatability and reproducibility (Gage R and R). In this study, a mathematical morphology algorithm is proposed for automatically detecting the roughness of the striplines. Basing on the algorithm and operating flow, the detected Rz and Rq values of the copper-foil roughness are applied in 3D simulation tool for the insertion-loss validation and comparison.
{"title":"Copper Surface Roughness Analysis in Mathematical Morphology Algorithm for the Insertion-Loss Validation","authors":"Li-Chi Chang, Yu-Sen Yang, Yu-Tian Lee, Shao-Wei Hsu, Chieh-Sen Lee, Ming-Chuan Chang","doi":"10.1109/IMPACT56280.2022.9966669","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966669","url":null,"abstract":"Insertion loss of a testing vehicle is widely referred for the material estimation, the differential pair and single-end striplines are generally employed for the high-speed digital applications. In addition to the matte side, the shiny side with the surface treatment of the inner layer is the critical issue for the insertion-loss improvement. In general, the inner-layer roughness is determined by the cross-section scanning electron or optical microscope photo with the manual defining of the average line. Therefore, the tolerance is produced from personal operation or gage repeatability and reproducibility (Gage R and R). In this study, a mathematical morphology algorithm is proposed for automatically detecting the roughness of the striplines. Basing on the algorithm and operating flow, the detected Rz and Rq values of the copper-foil roughness are applied in 3D simulation tool for the insertion-loss validation and comparison.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"7 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87258385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/impact56280.2022.9966639
Chen-xi Xie, Jie-Guo, Mei-Juan Kuang
With the invention and development of PCB and FPC, Rigidflexible (referred as R-F in the following text) board was designed and realized naturally by engineers. We combine flex and rigid materials by laminating with certain stack-up, these materials contain FCCL, CVL, LF PP, CCL and so on. Due to the great difference of CTE (coefficient of thermal expansion) between these materials, the defect of hole copper crack happens frequently during thermal cycle test (as known as TCT) for R-F board. Normally rigid PCB can survive after more than 1000 cycles of TCT test with condition of - 40°/30min to 125°/30min, however the R-F board will fail within 600 ~ 700 cycles. After a change of resistance more than 10% detected, engineers will find out the crack of copper mainly in the contact surface of LF PP and PI layer of FCCL, which is resulted from the obvious difference between CTE of LF PP and PI. This paper mainly starts from three factors, different kinds of PP with different CTE, through hole copper thickness and copper elongation, to research how these factors affect the life of R-F board enduring TCT with DOE method. Through this paper, we hope to give some suggestions to engineers who wants to enhance the cycles of TCT test of R-F board in PCB industry.
{"title":"Research on the Thermal Cycle Test Performance Improving in Automotive R-F PCB","authors":"Chen-xi Xie, Jie-Guo, Mei-Juan Kuang","doi":"10.1109/impact56280.2022.9966639","DOIUrl":"https://doi.org/10.1109/impact56280.2022.9966639","url":null,"abstract":"With the invention and development of PCB and FPC, Rigidflexible (referred as R-F in the following text) board was designed and realized naturally by engineers. We combine flex and rigid materials by laminating with certain stack-up, these materials contain FCCL, CVL, LF PP, CCL and so on. Due to the great difference of CTE (coefficient of thermal expansion) between these materials, the defect of hole copper crack happens frequently during thermal cycle test (as known as TCT) for R-F board. Normally rigid PCB can survive after more than 1000 cycles of TCT test with condition of - 40°/30min to 125°/30min, however the R-F board will fail within 600 ~ 700 cycles. After a change of resistance more than 10% detected, engineers will find out the crack of copper mainly in the contact surface of LF PP and PI layer of FCCL, which is resulted from the obvious difference between CTE of LF PP and PI. This paper mainly starts from three factors, different kinds of PP with different CTE, through hole copper thickness and copper elongation, to research how these factors affect the life of R-F board enduring TCT with DOE method. Through this paper, we hope to give some suggestions to engineers who wants to enhance the cycles of TCT test of R-F board in PCB industry.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"61 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84713420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/impact56280.2022.9966726
Boyin Wu, M. Kuo, Y. Chiang, Jeffrey Yang, Jen-Kuang Fang
The quality of redistribution layer (RDL) dominates the electrical performance of semiconductor package. Theoretically, the RDL thickness uniformity control becomes more challenge as increasing the substrate size, especially on the 600mm panel platform. In this study, the dummy pattern around and across the panel, called as firewall, have been used to influence the electrical distribution, to overcome the electroplating copper thickness uniformity problem around the blank area, which is used to develop the high-quality fan-out panel level packaging (FOPLP). The experiment results show the RDL thickness non-uniformity can be improved by 21% and 30% by tuning the area and the metal density of firewall, respectively. This firewall tuning technology is useful to diminish the RDL thickness difference among all dies within the panel, which can be adopted in any high-performance large size panel level packaging.
{"title":"Firewall Design for High Quality Electroplating Redistribution Layers on 600mm Panel","authors":"Boyin Wu, M. Kuo, Y. Chiang, Jeffrey Yang, Jen-Kuang Fang","doi":"10.1109/impact56280.2022.9966726","DOIUrl":"https://doi.org/10.1109/impact56280.2022.9966726","url":null,"abstract":"The quality of redistribution layer (RDL) dominates the electrical performance of semiconductor package. Theoretically, the RDL thickness uniformity control becomes more challenge as increasing the substrate size, especially on the 600mm panel platform. In this study, the dummy pattern around and across the panel, called as firewall, have been used to influence the electrical distribution, to overcome the electroplating copper thickness uniformity problem around the blank area, which is used to develop the high-quality fan-out panel level packaging (FOPLP). The experiment results show the RDL thickness non-uniformity can be improved by 21% and 30% by tuning the area and the metal density of firewall, respectively. This firewall tuning technology is useful to diminish the RDL thickness difference among all dies within the panel, which can be adopted in any high-performance large size panel level packaging.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76825798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966629
Siying Wu, Shwu Miin Tan, J. Xue, Cheong Huat Ng, Zhigang Li
With the evolution of electronic and automotive field, the reliability requirement of package is getting stringent. The package is required to withstand the extreme conditions while maintaining good electrical performance. Interfacial delamination is one of the key factors that impacts the reliability of electronic package. When the delamination occurs between lead frame (LF) and epoxy molding compound (EMC), the moisture will ingress into the package and cause bond pad or wedge corrosion, which leads to electrical failure.To verify the robustness of Dual Flat Non-leaded (DFN) package, the effects of package singulation parameters on package delamination performance were investigated in this study, dicing blade types, saw method, spindle speed, feed speed, and cooling water flow rate. As the result shown, the blade with small grit size had better cutting quality and induced less stress than large grit size blade. Reducing the cutting stress was beneficial to improve the delamination performance. And the cutting methods also influenced on delamination performance. The chopper cut and normal cut method were used in the same type of package to compare the delamination performance. The results of C-SAM shown the normal cut had better delamination performance than chopper cut. In addition, the delamination performance deteriorated with increasing spindle speed, which was related to the adverse impact of blade at high spindle speed and heat generation of friction. And the feed rate also had a small effect on delamination. Besides, hundred-degree celsius temperature of heat will be generated during blade cutting, which will reduce the adhesion strength and cause the expand and contract of EMC and LF. Therefore, cooling the blade with high cooling water rate could help in delamination.In summary, the effect of package singulation on delamination defects was investigated in this paper. The delamination performance could be optimized by selecting suitable EMC, LF surface treatment & design, dicing blade, cutting method and singulation parameters.
{"title":"Effect of Package Singulation Parameters on Dual Flat Non-leaded Package Delamination","authors":"Siying Wu, Shwu Miin Tan, J. Xue, Cheong Huat Ng, Zhigang Li","doi":"10.1109/IMPACT56280.2022.9966629","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966629","url":null,"abstract":"With the evolution of electronic and automotive field, the reliability requirement of package is getting stringent. The package is required to withstand the extreme conditions while maintaining good electrical performance. Interfacial delamination is one of the key factors that impacts the reliability of electronic package. When the delamination occurs between lead frame (LF) and epoxy molding compound (EMC), the moisture will ingress into the package and cause bond pad or wedge corrosion, which leads to electrical failure.To verify the robustness of Dual Flat Non-leaded (DFN) package, the effects of package singulation parameters on package delamination performance were investigated in this study, dicing blade types, saw method, spindle speed, feed speed, and cooling water flow rate. As the result shown, the blade with small grit size had better cutting quality and induced less stress than large grit size blade. Reducing the cutting stress was beneficial to improve the delamination performance. And the cutting methods also influenced on delamination performance. The chopper cut and normal cut method were used in the same type of package to compare the delamination performance. The results of C-SAM shown the normal cut had better delamination performance than chopper cut. In addition, the delamination performance deteriorated with increasing spindle speed, which was related to the adverse impact of blade at high spindle speed and heat generation of friction. And the feed rate also had a small effect on delamination. Besides, hundred-degree celsius temperature of heat will be generated during blade cutting, which will reduce the adhesion strength and cause the expand and contract of EMC and LF. Therefore, cooling the blade with high cooling water rate could help in delamination.In summary, the effect of package singulation on delamination defects was investigated in this paper. The delamination performance could be optimized by selecting suitable EMC, LF surface treatment & design, dicing blade, cutting method and singulation parameters.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"7 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78510509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966643
S. Chang, Tae-Kyu Lee, Wei Li, K. Loh, E. Ibe, Simon Wang
Low melting temperature solder, which enables a lower temperature assembly process comes with significant benefits for less warpage and lower component defect risk, but at a cost of a potentially inferior thermal cycling performance due to higher creep rate at an elevated temperature environment.The creep rate can be reduced by dispensing underfill between BGA and PCB to lower thermal stress concentrated on the corner. Thus, the thermal cycling performance would be improved. However, this would increase difficulty when replacing the BGA. For this reason, applying edgebond on the peripheral of the BGA in the assembly process makes it easier to operate on during the rework process. Additionally, it will reduce material consumption dramatically for big BGAs.In this study, we evaluate the reliability of low-temperature solders, Sn-58Bi, used in the BGA, 12mm*12mm, assembly without edgebond and with edgebond. Comparing the characteristic life cycle number of 3328 cycles with Sn-58Bi solder, the full edgebond BGAs’ does not show any failures up to the test completion at 4050 cycles.To extend edgebond applications for the strong need for extra-large BGA in today’s electronics industry, we use simulation methods to compare the thermal stress of the solder joints when BGA size increases from 12mm by 12mm to 70mm by 70mm, and up to 100*100mm. These include the BGA assembly without edgebond and with edgebond. As thermal stress increases, the thermal cycle reliability shortens. From simulated thermal stress results, we can predict the edgebond’s significant benefit for the thermal cycling reliability of extra-large BGA on the board level assembly.
{"title":"Edgebond adhesive enhances the reliability of low-temperature solder in board-level assembly (IMPACT 2022)","authors":"S. Chang, Tae-Kyu Lee, Wei Li, K. Loh, E. Ibe, Simon Wang","doi":"10.1109/IMPACT56280.2022.9966643","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966643","url":null,"abstract":"Low melting temperature solder, which enables a lower temperature assembly process comes with significant benefits for less warpage and lower component defect risk, but at a cost of a potentially inferior thermal cycling performance due to higher creep rate at an elevated temperature environment.The creep rate can be reduced by dispensing underfill between BGA and PCB to lower thermal stress concentrated on the corner. Thus, the thermal cycling performance would be improved. However, this would increase difficulty when replacing the BGA. For this reason, applying edgebond on the peripheral of the BGA in the assembly process makes it easier to operate on during the rework process. Additionally, it will reduce material consumption dramatically for big BGAs.In this study, we evaluate the reliability of low-temperature solders, Sn-58Bi, used in the BGA, 12mm*12mm, assembly without edgebond and with edgebond. Comparing the characteristic life cycle number of 3328 cycles with Sn-58Bi solder, the full edgebond BGAs’ does not show any failures up to the test completion at 4050 cycles.To extend edgebond applications for the strong need for extra-large BGA in today’s electronics industry, we use simulation methods to compare the thermal stress of the solder joints when BGA size increases from 12mm by 12mm to 70mm by 70mm, and up to 100*100mm. These include the BGA assembly without edgebond and with edgebond. As thermal stress increases, the thermal cycle reliability shortens. From simulated thermal stress results, we can predict the edgebond’s significant benefit for the thermal cycling reliability of extra-large BGA on the board level assembly.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"62 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80670845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966695
April Joy H. Garete, Shwu Miin Tan, Weimei Cai, Zhiwen Li
In this study, different molding compounds and pre-plated leadframe surface combinations were characterized in terms of adhesion and its impact on package delamination. Furthermore, Au and Cu wire bonded devices assembled using different EMC and leadframe surface treatment combinations were also assessed to evaluate the quality and reliability performance of these BOM as packaging materials for a DFN package. Key features of the different molding compound materials investigated in this study includes advanced formulation for improved delamination resistance, better fluidity, and copper wire compatibility. Full material characterization was conducted to compare the physical and thermo-mechanical properties of the EMCs. Button shear test on standard and rough pre-plated lead frame surfaces and tab pull test on PPF, Au and Cu substrates were performed to compare the interfacial adhesion performance and typical shear failure modes of various molding compounds. Adhesion data was further supported by subjecting the assembled of DFN package with different BOM combination to Moisture Sensitivity Level 1 (MSLI). Scanning Acoustic Microscopy (SAM) was then used to check the delamination performance on all mold interfaces at zero hour and after MSLI. The delamination level difference between samples built with different EMC types and pre-plated leadframe combinations were summarized in this study. A 23um diameter Au-wire and Cu-wire bonded transistor was used as test vehicle to evaluate the material reliability performance on package level. Moldability check was done to inspect any external voids, incomplete fill, or wire sweep occurrence for all BOM combinations. Reliability performance was assessed by subjecting the assembled units to 1000 cycles Temperature Cycling Test (TCT), 96 hours Highly Accelerated Stress Test (HAST), and 1000 hours High Temperature Reverse Bias (HTRB) at a junction temperature of 150°C. Overall, the material study was able to successfully assess the adhesion, moldability, delamination and reliability performance of different molding compounds and pre-plated leadframe combinations on Au-wire and Cu-wire bonded DFN package.
{"title":"Adhesion and Reliability Study of Different EMC and Pre-plated Leadframe Surface Combination for Au and Cu Wire Bonded Leadless Package","authors":"April Joy H. Garete, Shwu Miin Tan, Weimei Cai, Zhiwen Li","doi":"10.1109/IMPACT56280.2022.9966695","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966695","url":null,"abstract":"In this study, different molding compounds and pre-plated leadframe surface combinations were characterized in terms of adhesion and its impact on package delamination. Furthermore, Au and Cu wire bonded devices assembled using different EMC and leadframe surface treatment combinations were also assessed to evaluate the quality and reliability performance of these BOM as packaging materials for a DFN package. Key features of the different molding compound materials investigated in this study includes advanced formulation for improved delamination resistance, better fluidity, and copper wire compatibility. Full material characterization was conducted to compare the physical and thermo-mechanical properties of the EMCs. Button shear test on standard and rough pre-plated lead frame surfaces and tab pull test on PPF, Au and Cu substrates were performed to compare the interfacial adhesion performance and typical shear failure modes of various molding compounds. Adhesion data was further supported by subjecting the assembled of DFN package with different BOM combination to Moisture Sensitivity Level 1 (MSLI). Scanning Acoustic Microscopy (SAM) was then used to check the delamination performance on all mold interfaces at zero hour and after MSLI. The delamination level difference between samples built with different EMC types and pre-plated leadframe combinations were summarized in this study. A 23um diameter Au-wire and Cu-wire bonded transistor was used as test vehicle to evaluate the material reliability performance on package level. Moldability check was done to inspect any external voids, incomplete fill, or wire sweep occurrence for all BOM combinations. Reliability performance was assessed by subjecting the assembled units to 1000 cycles Temperature Cycling Test (TCT), 96 hours Highly Accelerated Stress Test (HAST), and 1000 hours High Temperature Reverse Bias (HTRB) at a junction temperature of 150°C. Overall, the material study was able to successfully assess the adhesion, moldability, delamination and reliability performance of different molding compounds and pre-plated leadframe combinations on Au-wire and Cu-wire bonded DFN package.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82223819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966711
H. L. Chen, B. Chen, K. Chiang
Moore’s law was proposed by Gordon Earle Moore, who believes that the number of transistors that can be accommodated on an integrated circuit would double about every 18 months. Since it is approaching the physical limit, Moore’s law is no longer applicable. Packaging technology becomes more important in the post Moore era. The development of electronic packaging can be roughly divided into five stages, namely TO-CAN, DIP (Dual In-line Package), PQFP (Plastic Quad Flat Pack), PBGA (Plastic Ball Grid Array) and the CSP (Chip Scale Package) used in this research. The evolutions are to improve signal transmission speed, storage capacity and the pursuit of higher packaging density. The reliability of packages is very important. Different sizes or manufacturing methods will affect their lifetime. Before these packages are put on the market, they must be tested and experimented to ensure their reliability. However, it will waste a lot of resources and time costs, resulting in less profit.Finite element analysis is a numerical method that can subdivide a large physical system into a finite number of smaller and simpler elements. The study uses ANSYS to simulate WLCSP (Wafer Level Chip Scale Packaging) through thermal cycling test, and used empirical formulas to estimate the lifetime of solder balls. Also, the mesh size at the maximum DNP (Distance from Neutral Point) is fixed. Make the simulation closer to the experiment results. After the verification of simulation and experimental data, the feasibility of the model is established, thereby saving the huge time cost of packaging testing and experimentation.However, finite element analysis will produce different results depending on the researcher. In order to avoid this factor and save the time spent in constructing the model, this research introduces artificial intelligence and combines supervised learning and unsupervised learning to estimate the solder ball lifetime. In this study, we used the verified finite element model to obtain different lifetime according to different sizes, and then introduced a large amount of data into AI algorithms [1] to achieve the purpose of quickly predicting the reliability of the package.The algorithm used in this study is KNN (K-Nearest Neighbors) which can be used for classification and regression, and uses different data numbers, different preprocessing methods, different distance definitions, and different weighting methods to compare the impact of the algorithm’s predictions on the lifetime of our packages. In addition, we combine unsupervised learning methods like K-means to assign data of the same characteristic into each cluster. Try to simplify the complexity of the model, save calculation time and improve the performance of KNN.
{"title":"Predict the Reliability Life of Wafer Level Packaging using K-Nearest Neighbors algorithm with Cluster Analysis","authors":"H. L. Chen, B. Chen, K. Chiang","doi":"10.1109/IMPACT56280.2022.9966711","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966711","url":null,"abstract":"Moore’s law was proposed by Gordon Earle Moore, who believes that the number of transistors that can be accommodated on an integrated circuit would double about every 18 months. Since it is approaching the physical limit, Moore’s law is no longer applicable. Packaging technology becomes more important in the post Moore era. The development of electronic packaging can be roughly divided into five stages, namely TO-CAN, DIP (Dual In-line Package), PQFP (Plastic Quad Flat Pack), PBGA (Plastic Ball Grid Array) and the CSP (Chip Scale Package) used in this research. The evolutions are to improve signal transmission speed, storage capacity and the pursuit of higher packaging density. The reliability of packages is very important. Different sizes or manufacturing methods will affect their lifetime. Before these packages are put on the market, they must be tested and experimented to ensure their reliability. However, it will waste a lot of resources and time costs, resulting in less profit.Finite element analysis is a numerical method that can subdivide a large physical system into a finite number of smaller and simpler elements. The study uses ANSYS to simulate WLCSP (Wafer Level Chip Scale Packaging) through thermal cycling test, and used empirical formulas to estimate the lifetime of solder balls. Also, the mesh size at the maximum DNP (Distance from Neutral Point) is fixed. Make the simulation closer to the experiment results. After the verification of simulation and experimental data, the feasibility of the model is established, thereby saving the huge time cost of packaging testing and experimentation.However, finite element analysis will produce different results depending on the researcher. In order to avoid this factor and save the time spent in constructing the model, this research introduces artificial intelligence and combines supervised learning and unsupervised learning to estimate the solder ball lifetime. In this study, we used the verified finite element model to obtain different lifetime according to different sizes, and then introduced a large amount of data into AI algorithms [1] to achieve the purpose of quickly predicting the reliability of the package.The algorithm used in this study is KNN (K-Nearest Neighbors) which can be used for classification and regression, and uses different data numbers, different preprocessing methods, different distance definitions, and different weighting methods to compare the impact of the algorithm’s predictions on the lifetime of our packages. In addition, we combine unsupervised learning methods like K-means to assign data of the same characteristic into each cluster. Try to simplify the complexity of the model, save calculation time and improve the performance of KNN.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"116 2","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91500488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966708
Y. Kobayashi, H. Tamaru, K. Sakaue, H. Sakurai, Kohei Shimahara, Tsubasa Endo, S. Tani
The process rule of a semiconductor is getting smaller and smaller. Accordingly, the size of a via hole or line and space in a package is also becoming smaller. In addition, yearly evolving materials are being tested as substrate materials for the next-generation higher-frequency circuit boards or buildup substrates. The laser micro-hole drilling is a key technology for realizing these demands, and development of lasers with higher output power and shorter wavelengths is being vigorously conducted in order to drill smaller holes at higher speeds. On the other hand, significant challenges exist for drilling small holes in newly emerging materials. Depending on the parameters, drilling can damage the copper film behind the hole or chip the material due to its own brittleness. Therefore, it is necessary to optimize various processing parameters such as laser pulse width, pulse energy, repetition frequency, irradiation time, wavelength, and beam trajectory according to the required design, including hole diameter, aspect ratio, and pitch. Currently, parameter optimization is being done manually in a trial- and-error manner, which could take several months or even years for new materials or designs. The time required for feasibility testing can slow down the design process, and also forces material manufacturers to spend a great deal of time examining what kind of material composition will actually be used.
{"title":"Cyber-Physical System of laser micro processing for semiconductor package fabrication","authors":"Y. Kobayashi, H. Tamaru, K. Sakaue, H. Sakurai, Kohei Shimahara, Tsubasa Endo, S. Tani","doi":"10.1109/IMPACT56280.2022.9966708","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966708","url":null,"abstract":"The process rule of a semiconductor is getting smaller and smaller. Accordingly, the size of a via hole or line and space in a package is also becoming smaller. In addition, yearly evolving materials are being tested as substrate materials for the next-generation higher-frequency circuit boards or buildup substrates. The laser micro-hole drilling is a key technology for realizing these demands, and development of lasers with higher output power and shorter wavelengths is being vigorously conducted in order to drill smaller holes at higher speeds. On the other hand, significant challenges exist for drilling small holes in newly emerging materials. Depending on the parameters, drilling can damage the copper film behind the hole or chip the material due to its own brittleness. Therefore, it is necessary to optimize various processing parameters such as laser pulse width, pulse energy, repetition frequency, irradiation time, wavelength, and beam trajectory according to the required design, including hole diameter, aspect ratio, and pitch. Currently, parameter optimization is being done manually in a trial- and-error manner, which could take several months or even years for new materials or designs. The time required for feasibility testing can slow down the design process, and also forces material manufacturers to spend a great deal of time examining what kind of material composition will actually be used.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"52 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87605140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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