Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966715
C. Kung, Hung-Yi Lin, Chin-Cheng Kuo, Cheng-Syuan Wu, Yu-Ting Chen, Meng-Wei Hsieh, Yu-Chang Hsieh, Pao-Nan Lee
Higher performance and smaller form factor are always the critical subjects for mobile device in recent years. To meet this demand, System-In-Package (SiP) has become a certain path for innovation and an unstoppable trend for decade. In this study, the benefits of evolving SiP with organic substrate to Fan-Out SiP (FOSiP) for new generation mobile RF module with higher performance and smaller form factor has been illustrated. A designed and manufactured FOSiP module with 6 RF devices integrated by several core features and building blocks would be demonstrated, including chip-last RDL manufacturing, carrier system, wafer level assembly and shielding sputtering.
{"title":"RF Devices Integrated by Fan-Out and System-In-Package Technology","authors":"C. Kung, Hung-Yi Lin, Chin-Cheng Kuo, Cheng-Syuan Wu, Yu-Ting Chen, Meng-Wei Hsieh, Yu-Chang Hsieh, Pao-Nan Lee","doi":"10.1109/IMPACT56280.2022.9966715","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966715","url":null,"abstract":"Higher performance and smaller form factor are always the critical subjects for mobile device in recent years. To meet this demand, System-In-Package (SiP) has become a certain path for innovation and an unstoppable trend for decade. In this study, the benefits of evolving SiP with organic substrate to Fan-Out SiP (FOSiP) for new generation mobile RF module with higher performance and smaller form factor has been illustrated. A designed and manufactured FOSiP module with 6 RF devices integrated by several core features and building blocks would be demonstrated, including chip-last RDL manufacturing, carrier system, wafer level assembly and shielding sputtering.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"26 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78239832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966718
S. Rajendran, Hyejun Kang, SeongMin Seo, J. Jung
With the progress in miniaturization and portability of consumer electronics, devices are expected to be compact and lightweight, demanding more input-output electrical transfer in less space via fine-pitch interconnections. The solder ball diameter used in the ball grid array (BGA) and Flip-chip ball grid array (FCBGA) for joining the integrated circuits, microprocessors, memory chips, etc., to printed circuit boards (PCB) is continuously downsized to meet the current market demands [1, 2].
{"title":"Ultrasonic dispersion of nanocomposite solder for microelectronic packaging","authors":"S. Rajendran, Hyejun Kang, SeongMin Seo, J. Jung","doi":"10.1109/IMPACT56280.2022.9966718","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966718","url":null,"abstract":"With the progress in miniaturization and portability of consumer electronics, devices are expected to be compact and lightweight, demanding more input-output electrical transfer in less space via fine-pitch interconnections. The solder ball diameter used in the ball grid array (BGA) and Flip-chip ball grid array (FCBGA) for joining the integrated circuits, microprocessors, memory chips, etc., to printed circuit boards (PCB) is continuously downsized to meet the current market demands [1, 2].","PeriodicalId":13517,"journal":{"name":"Impact","volume":"15 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89908889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966697
Chiung-Ying Kuo, H. Kuo, Ming-Fong Jhong, Chen-Chao Wang
In order to ensure the performance of high-frequency fan-out package design, especially at mmWave application, the influence of substrate dielectric characteristic is very serious. Polyimide (PI) material is common material used in Fan-out package. The moisture effect of PI is very obvious in stress and electrical performance. Sso this paper introduces the method of dielectric constant (Dk) and dissipation factor (Df) extraction. And then the moisture effect on transmission line loss and phase are also studied in this paper, the frequency is up to mmWave range.
{"title":"A Study of Material Extraction and Moisture Effect on mmWave Fan-out Package Design","authors":"Chiung-Ying Kuo, H. Kuo, Ming-Fong Jhong, Chen-Chao Wang","doi":"10.1109/IMPACT56280.2022.9966697","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966697","url":null,"abstract":"In order to ensure the performance of high-frequency fan-out package design, especially at mmWave application, the influence of substrate dielectric characteristic is very serious. Polyimide (PI) material is common material used in Fan-out package. The moisture effect of PI is very obvious in stress and electrical performance. Sso this paper introduces the method of dielectric constant (Dk) and dissipation factor (Df) extraction. And then the moisture effect on transmission line loss and phase are also studied in this paper, the frequency is up to mmWave range.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"75 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86287278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966699
Fred Chou, Alex Wei, Johnny Hsieh, Adolph Cheng, J. Hsu
As communication technology transits to 5G generation, it drives the development of AI ecology, such as new smart factories, smart warehousing, smart real-time monitoring platforms and other applications, which also tests the quality detection capability of high-speed channels in the data center printed circuit board(PCB), such as the loss of high-speed channels capability of measurement and impedance measurement and segmental analysis. The PCB manufacturers usually check the impedance by time-domain reflectometer (TDR) and channel loss of the PCB by vector network analyzer(VNA) according to the IPC standards [1] [2]. It is critical to have multi-zone analysis ability of the TDR impedance profile in the design and manufacture accurate perspective, such as how to identify correctly break out with the narrow trace routing, plating through hole (PTH) via and main routing impedance. In this paper, VNA with the calibration technology is proposed to not only analyze TDR impedance with multi-zones but also measure channel loss for quality risk assessment. The precision coaxial air lines are adopted as primary reference standards to assure impedance measurement verification, and traceability mechanism is conducted into the comparison experimental of impedance compensation capabilities for accurate and robust measurement. [3–5]
{"title":"Robust and Accurate Measurement Methodology for High-speed Channel Electrical Characterization","authors":"Fred Chou, Alex Wei, Johnny Hsieh, Adolph Cheng, J. Hsu","doi":"10.1109/IMPACT56280.2022.9966699","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966699","url":null,"abstract":"As communication technology transits to 5G generation, it drives the development of AI ecology, such as new smart factories, smart warehousing, smart real-time monitoring platforms and other applications, which also tests the quality detection capability of high-speed channels in the data center printed circuit board(PCB), such as the loss of high-speed channels capability of measurement and impedance measurement and segmental analysis. The PCB manufacturers usually check the impedance by time-domain reflectometer (TDR) and channel loss of the PCB by vector network analyzer(VNA) according to the IPC standards [1] [2]. It is critical to have multi-zone analysis ability of the TDR impedance profile in the design and manufacture accurate perspective, such as how to identify correctly break out with the narrow trace routing, plating through hole (PTH) via and main routing impedance. In this paper, VNA with the calibration technology is proposed to not only analyze TDR impedance with multi-zones but also measure channel loss for quality risk assessment. The precision coaxial air lines are adopted as primary reference standards to assure impedance measurement verification, and traceability mechanism is conducted into the comparison experimental of impedance compensation capabilities for accurate and robust measurement. [3–5]","PeriodicalId":13517,"journal":{"name":"Impact","volume":"16 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89996479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
There has been strong demand to increase I/O bandwidth for higher performance of semiconductor packages [1, 2, 3, 4]. Hybrid bonding is a very important interconnect technology not only to increase the I/O bandwidth but also to reduce signal delay and inter connect power loss for next generation High Performance Computing (HPC) requirements. Also hybrid bonding technology is key technology for 3D IC (Integrated Chiplets).
{"title":"A Laser Release Temporary Bonding Tape for Hybrid Bonding Having High Thermal Resistance and Excellent Thickness Uniformity","authors":"Izumi Daido, Ryoichi Watanabe, Toshio Takahashi, Masateru Fukuoka","doi":"10.1109/IMPACT56280.2022.9966704","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966704","url":null,"abstract":"There has been strong demand to increase I/O bandwidth for higher performance of semiconductor packages [1, 2, 3, 4]. Hybrid bonding is a very important interconnect technology not only to increase the I/O bandwidth but also to reduce signal delay and inter connect power loss for next generation High Performance Computing (HPC) requirements. Also hybrid bonding technology is key technology for 3D IC (Integrated Chiplets).","PeriodicalId":13517,"journal":{"name":"Impact","volume":"99 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79048257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966709
Huafang Ju, Xiang Li, J. Hsu, Shaohua Li, T. Su, Mo Liu, Kai Xiao
PCI-Express (PCIe) data rate continues to double generation by generation from PCIe 4.0 with 16Gbps, PCIe 5.0 with 32Gbps to PCIe 6.0 with 64Gbps in recent years. However, data center motherboard form factor and landing zone requirement remain the same, which implies all enablers in channel need to be improved to meet the maximum board routing length. Because PCB and connector are important components in the platform channel, besides their perspective performance, connector pin field PCB footprint design can also play a big role in channel solution space and PCB cost. In this paper, PCB routing optimization is addressed through the connector footprint optimization and the connector design innovation.
{"title":"Printed Circuit Board (PCB) Routing optimization with an Innovative Edge Connector for PCI-Express 5.0 and Beyond","authors":"Huafang Ju, Xiang Li, J. Hsu, Shaohua Li, T. Su, Mo Liu, Kai Xiao","doi":"10.1109/IMPACT56280.2022.9966709","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966709","url":null,"abstract":"PCI-Express (PCIe) data rate continues to double generation by generation from PCIe 4.0 with 16Gbps, PCIe 5.0 with 32Gbps to PCIe 6.0 with 64Gbps in recent years. However, data center motherboard form factor and landing zone requirement remain the same, which implies all enablers in channel need to be improved to meet the maximum board routing length. Because PCB and connector are important components in the platform channel, besides their perspective performance, connector pin field PCB footprint design can also play a big role in channel solution space and PCB cost. In this paper, PCB routing optimization is addressed through the connector footprint optimization and the connector design innovation.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"14 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85091137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fingerprint recognition is one of the most well-known digital identifications and has been widely used on forensic science, criminal investigation, financial services, electronic smart locks …etc. In this paper, latent fingerprint marks have been image segmentation and reconstruction based on the Unet method. In the first, latent fingerprint marks were collected on Ninhydrin reaction thermal-induced paper and the image of fingerprints were segmented using Unet algorithm. Secondly, mutilated fingerprints were image reconstructed for the whole loops and whorls on a finger. And lastly, a Receiver Operating Characteristic (ROC) curves scheme has been applied to analyzed classification accuracy of a statistical developed model.
{"title":"optimization fingerprint reconstruction using deep learning algorithm","authors":"Ming-Sie Pan, Chao-Hsin Fan, Yih-Lon Lin, Hsiang-Chen Hsu","doi":"10.1109/IMPACT56280.2022.9966693","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966693","url":null,"abstract":"Fingerprint recognition is one of the most well-known digital identifications and has been widely used on forensic science, criminal investigation, financial services, electronic smart locks …etc. In this paper, latent fingerprint marks have been image segmentation and reconstruction based on the Unet method. In the first, latent fingerprint marks were collected on Ninhydrin reaction thermal-induced paper and the image of fingerprints were segmented using Unet algorithm. Secondly, mutilated fingerprints were image reconstructed for the whole loops and whorls on a finger. And lastly, a Receiver Operating Characteristic (ROC) curves scheme has been applied to analyzed classification accuracy of a statistical developed model.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"21 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72792115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966630
T. Ouyang, Y. Hung, O. Lee, S. Y. Li, W. Chiu, T. Y. Hung, S. H. Wu, H. Chang
The through-silicon-via interposer is recommended to enable 3D integrated circuit integration. However, the electrical design and manufacture of high-density TSVs is a challenge and has low fabrication capability. In this report, we have demonstrated a novel concept about a pre-fabricated high-density TSV interposer. A commonly reusable TSV design can eliminate the concern of the compatibility issue to interconnecting with the RDL trace. A 3% open ratio TSV with the diameter-to-depth aspect ratio 1:10 over 300 mm wafer is ultimately produced based on the modification of the dry Si etch parameters and subtle electroplating conditions to achieve a straight and void-free TSV. The pass-through current density on the TSV array can be effectively enhanced for a high I/O pin count application. The signal can reserve the integrity and possess an 8 Gbps transmission rate at 20 GHz high frequency. A pre-fabricated high-density TSV interposer can effectively reduce the production time and promote the throughput in 3D integrated circuit applications.
{"title":"Pre-fabricated High-density TSV Interposer for Programmable IC Applications","authors":"T. Ouyang, Y. Hung, O. Lee, S. Y. Li, W. Chiu, T. Y. Hung, S. H. Wu, H. Chang","doi":"10.1109/IMPACT56280.2022.9966630","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966630","url":null,"abstract":"The through-silicon-via interposer is recommended to enable 3D integrated circuit integration. However, the electrical design and manufacture of high-density TSVs is a challenge and has low fabrication capability. In this report, we have demonstrated a novel concept about a pre-fabricated high-density TSV interposer. A commonly reusable TSV design can eliminate the concern of the compatibility issue to interconnecting with the RDL trace. A 3% open ratio TSV with the diameter-to-depth aspect ratio 1:10 over 300 mm wafer is ultimately produced based on the modification of the dry Si etch parameters and subtle electroplating conditions to achieve a straight and void-free TSV. The pass-through current density on the TSV array can be effectively enhanced for a high I/O pin count application. The signal can reserve the integrity and possess an 8 Gbps transmission rate at 20 GHz high frequency. A pre-fabricated high-density TSV interposer can effectively reduce the production time and promote the throughput in 3D integrated circuit applications.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"24 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75967778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/IMPACT56280.2022.9966631
A. Myalitsin, Z.-W. Chen, N. Araki, T. Nakamura, T. Fukuda, T. Ohba
The application of Raman spectroscopy to the silicon device manufacturing process was investigated for the first time. Confocal Raman imaging is a non-contact, non-destructive technique, which can be used for 3D-imaging of semiconductors. The depth resolution is particularly important for stacked devices, such as wafer-on-wafer. Further, Raman can visualize residual stress in the devices, which influences reliability of the final chip. Organic residues and contaminants are easily identified in the Raman spectra as well.
{"title":"Raman Spectroscopy and Hyperspectral Imaging for Wafer-On-Wafer (WOW) Processing","authors":"A. Myalitsin, Z.-W. Chen, N. Araki, T. Nakamura, T. Fukuda, T. Ohba","doi":"10.1109/IMPACT56280.2022.9966631","DOIUrl":"https://doi.org/10.1109/IMPACT56280.2022.9966631","url":null,"abstract":"The application of Raman spectroscopy to the silicon device manufacturing process was investigated for the first time. Confocal Raman imaging is a non-contact, non-destructive technique, which can be used for 3D-imaging of semiconductors. The depth resolution is particularly important for stacked devices, such as wafer-on-wafer. Further, Raman can visualize residual stress in the devices, which influences reliability of the final chip. Organic residues and contaminants are easily identified in the Raman spectra as well.","PeriodicalId":13517,"journal":{"name":"Impact","volume":"32 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75059952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-26DOI: 10.1109/impact56280.2022.9966716
{"title":"Welcome Message from Chih-I Wu, Conference General Chair","authors":"","doi":"10.1109/impact56280.2022.9966716","DOIUrl":"https://doi.org/10.1109/impact56280.2022.9966716","url":null,"abstract":"","PeriodicalId":13517,"journal":{"name":"Impact","volume":"216 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79621067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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