Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979657
K. Ehwald, B. Heinemann, W. Roepke, W. Winkler, H. Rucker, F. Fuernhammer, D. Knoll, R. Barth, B. Hunger, H. Wulf, R. Pazirandeh, N. Ilkov
We demonstrate high performance RF LDMOS transistors integrated into an advanced industrial 0.25 /spl mu/m BiCMOS process with only one additional mask level. These devices have minimum 0.25 /spl mu/m physical gate lengths, use the 5 nm standard gate oxide of the logic transistors, and show f/sub T/ and f/sub max/ values of up to 30 and 50 GHz, respectively. The breakdown voltages are between 26 V and 13 V depending on layout. The power-added efficiency (PAE) is 70% at 560 mW/2 GHz and 60% at 340 mW/5 GHz.
{"title":"High performance RF LDMOS transistors with 5 nm gate oxide in a 0.25 /spl mu/m SiGe:C BiCMOS technology","authors":"K. Ehwald, B. Heinemann, W. Roepke, W. Winkler, H. Rucker, F. Fuernhammer, D. Knoll, R. Barth, B. Hunger, H. Wulf, R. Pazirandeh, N. Ilkov","doi":"10.1109/IEDM.2001.979657","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979657","url":null,"abstract":"We demonstrate high performance RF LDMOS transistors integrated into an advanced industrial 0.25 /spl mu/m BiCMOS process with only one additional mask level. These devices have minimum 0.25 /spl mu/m physical gate lengths, use the 5 nm standard gate oxide of the logic transistors, and show f/sub T/ and f/sub max/ values of up to 30 and 50 GHz, respectively. The breakdown voltages are between 26 V and 13 V depending on layout. The power-added efficiency (PAE) is 70% at 560 mW/2 GHz and 60% at 340 mW/5 GHz.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"9 1","pages":"40.4.1-40.4.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75626580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979406
J. Wetzel, S.H. Lin, E. Mickler, J. Lee, B. Ahlbum, C. Jin, R. Fox, M. Tsai, W. Mlynko, K. Monnig, P. Winebarger
Technological challenges for selection and integration of ultra-low dielectric constant insulators are discussed. Correlations of material properties with their performance in 1 level-metal inlaid copper integration are established. Dielectric constants of candidate materials are estimated from line-to-line capacitance measurements and FEM. Implications regarding the changes in dielectric constant are discussed.
{"title":"Evaluation of material property requirements and performance of ultra-low dielectric constant insulators for inlaid copper metallization","authors":"J. Wetzel, S.H. Lin, E. Mickler, J. Lee, B. Ahlbum, C. Jin, R. Fox, M. Tsai, W. Mlynko, K. Monnig, P. Winebarger","doi":"10.1109/IEDM.2001.979406","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979406","url":null,"abstract":"Technological challenges for selection and integration of ultra-low dielectric constant insulators are discussed. Correlations of material properties with their performance in 1 level-metal inlaid copper integration are established. Dielectric constants of candidate materials are estimated from line-to-line capacitance measurements and FEM. Implications regarding the changes in dielectric constant are discussed.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"26 1","pages":"4.1.1-4.1.3"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80912602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979413
S. Sato, Z. Yasuda, M. Ishihara, N. Komai, H. Ohtorii, A. Yoshio, Y. Segawa, H. Horikoshi, Y. Ohoka, K. Tai, S. Takahashi, T. Nogami
A new principle for the copper removal process, Electro-Chemical-Polishing (ECP), to replace CMP is demonstrated. ECP which leverages electrochemical dissolution of copper has removal rates determined by the imposed current, higher than 8000 A/min, while "planarization" is made by wiping out copper complexes at a wiping pressure ten times lower than that for CMP to form erosion- and scratch-free damascene copper interconnects. ECP is a promising replacement for CMP suitable for copper inlaid in fragile low-k materials.
{"title":"Newly developed electro-chemical polishing process of copper as replacement of CMP suitable for damascene copper inlaid in fragile low-k dielectrics","authors":"S. Sato, Z. Yasuda, M. Ishihara, N. Komai, H. Ohtorii, A. Yoshio, Y. Segawa, H. Horikoshi, Y. Ohoka, K. Tai, S. Takahashi, T. Nogami","doi":"10.1109/IEDM.2001.979413","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979413","url":null,"abstract":"A new principle for the copper removal process, Electro-Chemical-Polishing (ECP), to replace CMP is demonstrated. ECP which leverages electrochemical dissolution of copper has removal rates determined by the imposed current, higher than 8000 A/min, while \"planarization\" is made by wiping out copper complexes at a wiping pressure ten times lower than that for CMP to form erosion- and scratch-free damascene copper interconnects. ECP is a promising replacement for CMP suitable for copper inlaid in fragile low-k materials.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"67 1","pages":"4.4.1-4.4.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89938356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979468
A. Chatterjee, D. Mosher, S. Sridhar, Y. Kim, M. Nandakumar, S. Aur, Z. Chen, P. Madhani, S. Tang, R. Aggarwal, S. Ashburn, H. Shichijo
This paper describes the integration of active and passive components to enable embedding analog circuits in an advanced digital CMOS technology developed for low standby power integrated circuits. Device design issues, device characteristics, and technology scaling are discussed in this context. The components include 1.5 V digital core CMOS, 1.5 V analog and 3.3 V I/O MOSFETs. In addition to these self-aligned MOSFETs we describe drain-extended transistors, DEnMOS and DEpMOS, where the drain extensions are formed using the well implants. A novel structure to improve the substrate collector, vertical pnp bipolar transistor is presented. The passive components described here are the n-poly on n-well capacitors and a polysilicon resistor with a low temperature coefficient of resistance, usually referred to as the zero-TCR resistor. The analog integration adds one extra mask used to block silicidation of the zero-TCR polysilicon resistor.
本文介绍了一种用于低待机功率集成电路的先进数字CMOS技术，该技术将有源和无源元件集成在一起，使嵌入模拟电路成为可能。器件设计问题，器件特性和技术缩放在此背景下进行了讨论。组件包括1.5 V数字核心CMOS, 1.5 V模拟和3.3 V I/O mosfet。除了这些自对准mosfet外，我们还描述了漏极扩展晶体管，DEnMOS和DEpMOS，其中漏极扩展是使用井植入物形成的。提出了一种改进衬底集电极的新型结构——垂直pnp双极晶体管。这里描述的无源元件是n-poly on n-well电容器和具有低温电阻系数的多晶硅电阻，通常称为零tcr电阻。模拟集成增加了一个额外的掩模，用于阻止零tcr多晶硅电阻的硅化。
{"title":"Analog integration in a 0.35 /spl mu/m Cu metal pitch, 0.1 /spl mu/m gate length, low-power digital CMOS technology","authors":"A. Chatterjee, D. Mosher, S. Sridhar, Y. Kim, M. Nandakumar, S. Aur, Z. Chen, P. Madhani, S. Tang, R. Aggarwal, S. Ashburn, H. Shichijo","doi":"10.1109/IEDM.2001.979468","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979468","url":null,"abstract":"This paper describes the integration of active and passive components to enable embedding analog circuits in an advanced digital CMOS technology developed for low standby power integrated circuits. Device design issues, device characteristics, and technology scaling are discussed in this context. The components include 1.5 V digital core CMOS, 1.5 V analog and 3.3 V I/O MOSFETs. In addition to these self-aligned MOSFETs we describe drain-extended transistors, DEnMOS and DEpMOS, where the drain extensions are formed using the well implants. A novel structure to improve the substrate collector, vertical pnp bipolar transistor is presented. The passive components described here are the n-poly on n-well capacitors and a polysilicon resistor with a low temperature coefficient of resistance, usually referred to as the zero-TCR resistor. The analog integration adds one extra mask used to block silicidation of the zero-TCR polysilicon resistor.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"15 1","pages":"10.1.1-10.1.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87758651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979466
A. O’Riordan, K. Dwane, G. Redmond
A novel technique for programmed integration of multiple GaAs based optoelectronic devices that exploits the response of these components to DC electric fields applied in nonaqueous solvents as a means to achieve their field assisted transport and site-selective localization has been developed. Application of the technique to heterogeneous integration of 50 and 80 micron diameter 650 nm emission GaAs based LEDs at silicon substrates is demonstrated.
{"title":"Programmed electrophoretic assembly and heterogeneous integration of optoelectronic devices at silicon substrates","authors":"A. O’Riordan, K. Dwane, G. Redmond","doi":"10.1109/IEDM.2001.979466","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979466","url":null,"abstract":"A novel technique for programmed integration of multiple GaAs based optoelectronic devices that exploits the response of these components to DC electric fields applied in nonaqueous solvents as a means to achieve their field assisted transport and site-selective localization has been developed. Application of the technique to heterogeneous integration of 50 and 80 micron diameter 650 nm emission GaAs based LEDs at silicon substrates is demonstrated.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"15 1","pages":"9.4.1-9.4.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87846055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979604
A. Naeemi, J.A. Davis, J. Meindl
New analytical models that describe distributed RLC interconnects with ideal and nonideal return paths are used to optimize the time delay and crosstalk of a state-of-the-art high-speed global interconnect structure that incorporates coplanar ground lines such that the delay and crosstalk are reduced by 12% and 38%, respectively.
{"title":"Analytical models for coupled distributed RLC lines with ideal and nonideal return paths","authors":"A. Naeemi, J.A. Davis, J. Meindl","doi":"10.1109/IEDM.2001.979604","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979604","url":null,"abstract":"New analytical models that describe distributed RLC interconnects with ideal and nonideal return paths are used to optimize the time delay and crosstalk of a state-of-the-art high-speed global interconnect structure that incorporates coplanar ground lines such that the delay and crosstalk are reduced by 12% and 38%, respectively.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"58 1","pages":"31.4.1-31.4.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86851191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979524
M. Gutsche, H. Seidl, J. Luetzen, A. Birner, T. Hecht, S. Jakschik, M. Kerber, M. Leonhardt, P. Moll, T. Pompl, H. Reisinger, S. Rongen, A. Saenger, U. Schroeder, B. Sell, A. Wahl, D. Schumann
Essential techniques that allow further scaling of trench DRAMs beyond 100 nm have been developed. Al/sub 2/O/sub 3/ was implemented as a high-k node dielectric in silicon-insulator-silicon trench capacitors. Al/sub 2/O/sub 3/ films were deposited by ALD with excellent step coverage at aspect ratios of up to AR/spl ap/60. Even after thermal stressing at 1050/spl deg/C an effective oxide thickness (=capacitance equivalent thickness) of t/sub ox/=3.6 nm and a leakage current of well below 1 fA/cell were obtained. Both selective and non-selective HSG Si was formed inside high-aspect ratio straight and bottled trenches. On fully integrated 0.17 /spl mu/m trench DRAMs, a storage capacitance of 45 fF/cell with acceptable leakage current was achieved. Both the aluminum oxide node dielectric and the HSG silicon have thus been proven to withstand the high thermal budget required for integration into trench DRAMs. In addition, a silicon etch process was developed that allows trench aspect ratios of AR/spl ap/60 at critical dimensions of CD=80 nm.
{"title":"Capacitance enhancement techniques for sub-100 nm trench DRAMs","authors":"M. Gutsche, H. Seidl, J. Luetzen, A. Birner, T. Hecht, S. Jakschik, M. Kerber, M. Leonhardt, P. Moll, T. Pompl, H. Reisinger, S. Rongen, A. Saenger, U. Schroeder, B. Sell, A. Wahl, D. Schumann","doi":"10.1109/IEDM.2001.979524","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979524","url":null,"abstract":"Essential techniques that allow further scaling of trench DRAMs beyond 100 nm have been developed. Al/sub 2/O/sub 3/ was implemented as a high-k node dielectric in silicon-insulator-silicon trench capacitors. Al/sub 2/O/sub 3/ films were deposited by ALD with excellent step coverage at aspect ratios of up to AR/spl ap/60. Even after thermal stressing at 1050/spl deg/C an effective oxide thickness (=capacitance equivalent thickness) of t/sub ox/=3.6 nm and a leakage current of well below 1 fA/cell were obtained. Both selective and non-selective HSG Si was formed inside high-aspect ratio straight and bottled trenches. On fully integrated 0.17 /spl mu/m trench DRAMs, a storage capacitance of 45 fF/cell with acceptable leakage current was achieved. Both the aluminum oxide node dielectric and the HSG silicon have thus been proven to withstand the high thermal budget required for integration into trench DRAMs. In addition, a silicon etch process was developed that allows trench aspect ratios of AR/spl ap/60 at critical dimensions of CD=80 nm.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"44 1","pages":"18.6.1-18.6.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88999152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979393
Y. Mochida, T. Takano, H. Gambe
The third generation mobile services using W-CDMA first began in Japan. Further research on next mobile systems has already been started. The paper briefly describes the history of cellular systems and then introduces a technical outline of new generation systems. A broadband wireless communication requires a wide frequency bandwidth, huge delay spread tolerance, big transmission power and subscriber capacity. In order to obtain a smart solution, further digital processing approaches with the most advanced CMOS technology will be a key issue as well as the low-distortion and high-frequency power devices.
{"title":"Future directions and technology requirements of wireless communications","authors":"Y. Mochida, T. Takano, H. Gambe","doi":"10.1109/IEDM.2001.979393","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979393","url":null,"abstract":"The third generation mobile services using W-CDMA first began in Japan. Further research on next mobile systems has already been started. The paper briefly describes the history of cellular systems and then introduces a technical outline of new generation systems. A broadband wireless communication requires a wide frequency bandwidth, huge delay spread tolerance, big transmission power and subscriber capacity. In order to obtain a smart solution, further digital processing approaches with the most advanced CMOS technology will be a key issue as well as the low-distortion and high-frequency power devices.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"54 1","pages":"1.3.1-1.3.8"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83857196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979449
Y. Mitani, H. Satake, A. Toriumi
Reports the study on the deuterium effect on the degradation of gate oxide under both channel hot electron (CHE) stress condition and Fowler-Nordheim (F-N) stress condition using n-MOSFETs having the deuterated gate oxides. The suppression of both interface-state generation and stress-induced leakage current (SILC) by the deuterium pyrogenic oxidation has been found not only under F-N stress condition but also under hot-hole injection condition. This result indicates that hydrogen-release process in SiO/sub 2/ correlates to the origin of SILC generation.
{"title":"Experimental evidence of hydrogen-related SILC generation in thin gate oxide","authors":"Y. Mitani, H. Satake, A. Toriumi","doi":"10.1109/IEDM.2001.979449","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979449","url":null,"abstract":"Reports the study on the deuterium effect on the degradation of gate oxide under both channel hot electron (CHE) stress condition and Fowler-Nordheim (F-N) stress condition using n-MOSFETs having the deuterated gate oxides. The suppression of both interface-state generation and stress-induced leakage current (SILC) by the deuterium pyrogenic oxidation has been found not only under F-N stress condition but also under hot-hole injection condition. This result indicates that hydrogen-release process in SiO/sub 2/ correlates to the origin of SILC generation.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"44 15","pages":"6.4.1-6.4.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91468650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979493
Wolfgang Fichtner, K. Esmark, Wolfgang Stadler
Electrostatic discharges (ESD) have always been a serious problem in the semiconductor industry. The presence of high electric fields and the amount of energy dissipated by the semiconductor devices during an ESD can give rise to electric breakdown of sensitive isolation layers as well as local melting, which leads to a latent damage or even breakdown of the whole integrated circuit (IC). One measure to prevent the breakdown of the IC is to provide the product with an adequate ESD robustness by implementing a kind of lightning conductor in the form of a protection element on the product itself. This methodology is called on-chip ESD protection.
{"title":"TCAD software for ESD on-chip protection design","authors":"Wolfgang Fichtner, K. Esmark, Wolfgang Stadler","doi":"10.1109/IEDM.2001.979493","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979493","url":null,"abstract":"Electrostatic discharges (ESD) have always been a serious problem in the semiconductor industry. The presence of high electric fields and the amount of energy dissipated by the semiconductor devices during an ESD can give rise to electric breakdown of sensitive isolation layers as well as local melting, which leads to a latent damage or even breakdown of the whole integrated circuit (IC). One measure to prevent the breakdown of the IC is to provide the product with an adequate ESD robustness by implementing a kind of lightning conductor in the form of a protection element on the product itself. This methodology is called on-chip ESD protection.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"19 1","pages":"14.1.1-14.1.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87103380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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