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International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)最新文献

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InP/InGaAs DHBTs with 341-GHz f/sub T/ at high current density of over 800 kA/cm/sup 2/ 在超过800 kA/cm/sup /的高电流密度下,具有341 ghz f/sub / T的InP/InGaAs dhbt
Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979630
M. Ida, K. Kurishima, N. Watanabe, T. Enoki
We describe MOVPE-grown InP/InGaAs DHBTs with a 150-nm-thick collector. The collector current blocking at the base/collector heterointerface is perfectly suppressed by the compositionally step-graded structure even at collector current density of over 1000 kA/cm/sup 2/. A cut-off frequency f/sub T/ of 341 GHz is obtained at high collector current density of 833 kA/cm/sup 2/ with practical on-state breakdown characteristics. This is the highest f/sub T/ every reported for any bipolar transistors.
我们描述了具有150nm厚收集器的movpe生长的InP/InGaAs dhbt。即使在集电极电流密度超过1000 kA/cm/sup /时,集电极电流在基极/集电极异质界面处的阻塞也被组成阶梯式梯度结构完全抑制。在高集电极电流密度为833 kA/cm/sup 2/时,获得了341 GHz的截止频率f/sub /,具有实用的导态击穿特性。这是任何双极晶体管报道的最高f/ T/ every。
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引用次数: 17
High-speed SiGe:C bipolar technology 高速SiGe:C双极技术
Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979508
J. Bock, H. Schafer, H. Knapp, D. Zoschg, K. Aufinger, M. Wurzer, S. Boguth, R. Stengl, R. Schreiter, T. Meister
A SiGe:C bipolar technology with a narrow base integrated into a double-polysilicon self-aligned transistor has been developed. A transit frequency of 106 GHz at a collector emitter breakdown voltage of 2.3 V, a maximum oscillation frequency of 145 GHz, and 6.5 ps gate delay demonstrate balanced transistor performance. State-of-the-art results for high-speed digital, analog, and low-power circuits are achieved.
开发了一种集成双多晶硅自对准晶体管的窄基SiGe:C双极技术。当集电极发射极击穿电压为2.3 V时,传输频率为106 GHz,最大振荡频率为145 GHz,栅极延迟为6.5 ps时,晶体管的性能达到平衡。实现了高速数字、模拟和低功耗电路的最先进结果。
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引用次数: 28
A comparative study of dielectric relaxation losses in alternative dielectrics 替代介质中介电松弛损耗的比较研究
Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979481
Hans Reisinger, G. Steinlesberger, S. Jakschik, M. Gutsche, T. Hecht, M. Leonhard, Uwe Schröder, H. Seidl, D. Schumann
This work is intended to draw attention to the effect of dielectric relaxation which is shown to severely influence the performance of alternative dielectrics in DRAM storage capacitors as well as of the gate dielectrics of MOSFETs. A comparison of the dielectric relaxation losses in standard insulators with those in most proposed high K dielectrics is presented.
这项工作旨在引起人们对介电松弛效应的关注,介电松弛效应严重影响DRAM存储电容器中替代介电体的性能以及mosfet的栅极介电体的性能。对标准绝缘体的介电松弛损耗与大多数提出的高K介电体的介电松弛损耗进行了比较。
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引用次数: 60
Triple-self-aligned, planar double-gate MOSFETs: devices and circuits 三自对准平面双栅mosfet:器件和电路
Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979527
K. Guarini, Paul M. Solomon, Yuan Zhang, Kevin K. Chan, E. C. Jones, Guy M. Cohen, A. Krasnoperova, M. Ronay, O. Dokumaci, J. J. Bucchignano, Cyril Cabral, Christian Lavoie, Victor Ku, Diane C. Boyd, K. Petrarca, I. V. Babich, J. Treichler, P. Kozlowski, J. Newbury, C. D'Emic, R. M. Sicina, Hon-Sum Philip Wong
We introduce a planar, triple-self-aligned double-gate FET structure ("PAGODA"). Device fabrication incorporates wafer bonding, front-end CMP, mixed optical/e-beam lithography, silicided silicon source/drain sidewalls, and back gate undercut and passivation. We demonstrate double-gate FET operation with good transport at both interfaces, inverter action, and NOR logic.
我们介绍了一种平面三自对准双栅极场效应管结构(“PAGODA”)。器件制造包括晶圆键合,前端CMP,混合光学/电子束光刻,硅化硅源/漏侧壁,以及后门凹边和钝化。我们演示了双栅极FET的工作,在两个接口,逆变器动作和NOR逻辑上都具有良好的传输。
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引用次数: 68
Advantage of silicon nitride gate insulator transistor by using microwave excited high-density plasma for applying 100nm technology node 采用微波激发高密度等离子体的氮化硅栅极绝缘体晶体管应用于100nm技术节点的优势
Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979639
S. Sugawa, I. Ohshima, H. Ishino, Y. Saito, M. Hirayama, T. Ohmi
We have succeeded to prepare a hgh quality silicon nitride gate insulator with lower gate leakage current in three orders of magnitude compared to that of conventional thermal oxide film, by using a Kr/NH3 mixed gas microwave-excited highdensity plasma with metal (TaN/Ta/TaN) gate. Moreover, we have evaluated the current drive capability dependence on the silicon surface orientation and found that the channel hole mobility on (110) surface at the channel-width direction of 13 5 degree from the (111) cut plane was 2.4 times hlgher than that of (100) surface. The CMOS transistor with the silicon nitride gate insulator formed by the microwave-excited plasma and TaN/Ta/TaN metal gate on (110) surface orientation silicon having a higher current drive capability and high integration density is the most practical candidate for lOOnm technology node and beyond.
利用Kr/NH3混合气体微波激发高密度等离子体和金属(TaN/Ta/TaN)栅极,成功制备了高质量的氮化硅栅极绝缘体,栅极漏电流比传统热氧化膜低3个数量级。此外,我们还评估了电流驱动能力与硅表面取向的关系,发现(110)表面在距离(111)切割平面13.5度的沟道宽度方向上的沟道孔迁移率是(100)表面的2.4倍。采用微波激发等离子体形成的氮化硅栅极绝缘体和(110)表面取向硅上的TaN/Ta/TaN金属栅极的CMOS晶体管具有更高的电流驱动能力和高集成度,是lOOnm技术节点及以后最实用的候选器件。
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引用次数: 25
MEMS fingerprint sensor with arrayed cavity structures 具有阵列空腔结构的MEMS指纹传感器
Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979661
N. Sato, K. Machida, H. Morimura, S. Shigematsu, K. Kudou, M. Yano, H. Kyuragi
We propose a MEMS (Micro Electro Mechanical Systems) fingerprint sensor whose pixels have novel cavity structures. Each cavity structure has a sensitive plane of a thin film on top, and a sensing circuit below it. Ridges on a finger surface bend the thin film mechanically, which is detected by the sensing circuit electronically. We fabricated the sensor using a CMOS compatible process with our sealing technique. The sensor can obtain fingerprint images of even dry or wet fingers. It also shows sufficient mechanical strength against finger pressure. These results confirm that the MEMS fingerprint sensor has the potential for wide practical application.
提出了一种基于MEMS(微机电系统)的指纹传感器,其像素具有新颖的空腔结构。每个腔体结构的顶部有一个薄膜的敏感平面,其下面有一个传感电路。手指表面的脊状物机械地弯曲薄膜,这由传感电路以电子方式检测。我们使用CMOS兼容工艺与我们的密封技术制造传感器。该传感器可以获得干燥或潮湿手指的指纹图像。它也显示出足够的机械强度抵抗手指压力。这些结果证实了MEMS指纹传感器具有广泛的实际应用潜力。
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引用次数: 5
Coupled Si and SiO/sub 2/ Monte Carlo device simulator for accurate gate current calculation 耦合Si和SiO/sub 2/蒙特卡罗器件模拟器,用于精确的栅极电流计算
Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979551
T. Ezaki, H. Nakasato, M. Hane
A new MOSFET device simulator has been developed based on a coupled Monte Carlo procedure for the carrier transport in both Si and SiO/sub 2/ regions. This simulator accounts for the image force effect that modulates potential barrier height for the electrons injected into the SiO/sub 2/. Gate currents are calculated combining both the hot carrier injection and the back-scattering from the SiO/sub 2/ region arising from the potential modulation. Flash memory cell simulations were performed by this method. The actual MOSFET gate currents and the programming characteristics of the flash memory cells could be reproduced quantitatively without using any adjustable parameters.
基于耦合蒙特卡罗程序开发了一种新的MOSFET器件模拟器,用于在Si和SiO/sub - 2/区域进行载流子传输。该模拟器考虑了像力效应,该效应调节了注入SiO/sub /的电子的势垒高度。结合热载流子注入和由电位调制引起的SiO/sub /区域的后向散射计算门电流。采用该方法对快闪存储单元进行了仿真。实际的MOSFET栅极电流和闪存单元的编程特性可以在不使用任何可调参数的情况下定量地再现。
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引用次数: 3
Novel direct-tunneling-current (DTC) method for channel length extraction beyond sub-50nm gate CMOS 基于直接隧道电流(DTC)的亚50nm栅极CMOS通道长度提取方法
Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979488
Sungkwon Hong, Yaohui Zhang, Y. Luo, T. Suligoj, Seong-Dong Kim, J. Woo, R. Li, B. Min, B. Hradsky, A. Vandooren, B. Nguyen, K. Wang
A novel method for accurate gate length extraction has been developed using direct tunneling current (DTC) through thin gate oxide. Applied to decanano CMOS devices, the proposed method is verified to be free from a severe assumption of unified effective mobility that is one of limitations of conventional method to sub-0.1 /spl mu/m. The DTC method is also insensitive to doping concentration and gate oxide thinning effect at the corner regions. In addition, we have studied the channel length dependence on gate line-edge roughness by comparing the DTC method and the conventional channel current method.
提出了一种利用直接隧道电流(DTC)通过薄栅极氧化物精确提取栅极长度的新方法。应用于decanano CMOS器件,验证了该方法摆脱了统一有效迁移率的严格假设,这是传统方法在0.1 /spl mu/m以下的限制之一。DTC方法对掺杂浓度和边角区栅氧化物减薄效应也不敏感。此外,我们还通过比较DTC方法和传统的通道电流方法,研究了通道长度与栅极线边缘粗糙度的关系。
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引用次数: 3
Statistical model for stress-induced leakage current and pre-breakdown current jumps in ultra-thin oxide layers 超薄氧化层中应力诱发泄漏电流和预击穿电流跳变的统计模型
Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979447
R. Degraeve, B. Kaczer, F. Schuler, M. Lorenzini, D. Wellekens, P. Hendrickx, J. van Houdt, L. Haspeslagh, G. Tempel, G. Groeseneken
We present a statistical, unified picture of Stress-Induced Leakage Current (SILC) generation, pre-breakdown current steps and breakdown in 2.4 nm oxide layers during a constant voltage stress. Pre-breakdown current steps were investigated through gate voltage ramp measurements and modeled by means of a percolation model with variable trap-trap distance. During oxide stress, first single-trap conduction paths are formed, followed by two-trap conduction paths which are identified as pre-breakdown current steps in small devices. Finally, a highly conducting path is formed which triggers breakdown.
我们提出了一个统计的,统一的图像应力引起的泄漏电流(SILC)的产生,预击穿电流步骤和击穿在2.4 nm氧化层在恒定电压应力。通过栅极电压斜坡测量研究了击穿前的电流阶跃,并通过具有可变陷阱-陷阱距离的渗透模型进行了建模。在氧化应力期间,首先形成单阱传导路径,随后形成双阱传导路径,这在小型器件中被确定为预击穿电流步骤。最后,形成一个高导通路触发击穿。
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引用次数: 23
Analytical model of the programming characteristics of scaled MONOS memories with a variety of trap densities and a proposal of a trap-density-modulated MONS memory 具有不同陷阱密度的缩放MONOS存储器的编程特性分析模型和陷阱密度调制MONOS存储器的方案
Pub Date : 2001-12-02 DOI: 10.1109/IEDM.2001.979489
K. Nomoto, U. Fujiwara, H. Aozasa, T. Terano, T. Kobayashi
Investigated the relation between the density of Si-H/N-H bonds and the programming characteristics of scaled metal-oxide-nitride-oxide-semiconductor (MONOS) memory devices and developed an analytical model for programming characteristics of the MONOS devices having a variety of trap densities. The model was validated experimentally. We apply the model to a metal-oxide-nitride-semiconductor (MONS) memory device with trap-density modulation in the nitride layer. The result shows the MONS memory is programmed faster and at lower-voltage than the conventional MONOS memory device.
研究了Si-H/N-H键密度与有刻度金属-氧化物-氮化物-氧化物半导体(MONOS)存储器件编程特性的关系,建立了具有不同陷阱密度的MONOS器件编程特性的分析模型。实验验证了模型的正确性。我们将该模型应用于在氮化层中具有陷阱密度调制的金属氧化物氮化半导体(MONS)存储器件。结果表明,与传统的MONOS存储器相比,MONOS存储器的编程速度更快,电压更低。
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引用次数: 3
期刊
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)
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