Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979630
M. Ida, K. Kurishima, N. Watanabe, T. Enoki
We describe MOVPE-grown InP/InGaAs DHBTs with a 150-nm-thick collector. The collector current blocking at the base/collector heterointerface is perfectly suppressed by the compositionally step-graded structure even at collector current density of over 1000 kA/cm/sup 2/. A cut-off frequency f/sub T/ of 341 GHz is obtained at high collector current density of 833 kA/cm/sup 2/ with practical on-state breakdown characteristics. This is the highest f/sub T/ every reported for any bipolar transistors.
{"title":"InP/InGaAs DHBTs with 341-GHz f/sub T/ at high current density of over 800 kA/cm/sup 2/","authors":"M. Ida, K. Kurishima, N. Watanabe, T. Enoki","doi":"10.1109/IEDM.2001.979630","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979630","url":null,"abstract":"We describe MOVPE-grown InP/InGaAs DHBTs with a 150-nm-thick collector. The collector current blocking at the base/collector heterointerface is perfectly suppressed by the compositionally step-graded structure even at collector current density of over 1000 kA/cm/sup 2/. A cut-off frequency f/sub T/ of 341 GHz is obtained at high collector current density of 833 kA/cm/sup 2/ with practical on-state breakdown characteristics. This is the highest f/sub T/ every reported for any bipolar transistors.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"75 1","pages":"35.4.1-35.4.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86100435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979508
J. Bock, H. Schafer, H. Knapp, D. Zoschg, K. Aufinger, M. Wurzer, S. Boguth, R. Stengl, R. Schreiter, T. Meister
A SiGe:C bipolar technology with a narrow base integrated into a double-polysilicon self-aligned transistor has been developed. A transit frequency of 106 GHz at a collector emitter breakdown voltage of 2.3 V, a maximum oscillation frequency of 145 GHz, and 6.5 ps gate delay demonstrate balanced transistor performance. State-of-the-art results for high-speed digital, analog, and low-power circuits are achieved.
{"title":"High-speed SiGe:C bipolar technology","authors":"J. Bock, H. Schafer, H. Knapp, D. Zoschg, K. Aufinger, M. Wurzer, S. Boguth, R. Stengl, R. Schreiter, T. Meister","doi":"10.1109/IEDM.2001.979508","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979508","url":null,"abstract":"A SiGe:C bipolar technology with a narrow base integrated into a double-polysilicon self-aligned transistor has been developed. A transit frequency of 106 GHz at a collector emitter breakdown voltage of 2.3 V, a maximum oscillation frequency of 145 GHz, and 6.5 ps gate delay demonstrate balanced transistor performance. State-of-the-art results for high-speed digital, analog, and low-power circuits are achieved.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"4 1","pages":"15.5.1-15.5.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83972337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979481
Hans Reisinger, G. Steinlesberger, S. Jakschik, M. Gutsche, T. Hecht, M. Leonhard, Uwe Schröder, H. Seidl, D. Schumann
This work is intended to draw attention to the effect of dielectric relaxation which is shown to severely influence the performance of alternative dielectrics in DRAM storage capacitors as well as of the gate dielectrics of MOSFETs. A comparison of the dielectric relaxation losses in standard insulators with those in most proposed high K dielectrics is presented.
{"title":"A comparative study of dielectric relaxation losses in alternative dielectrics","authors":"Hans Reisinger, G. Steinlesberger, S. Jakschik, M. Gutsche, T. Hecht, M. Leonhard, Uwe Schröder, H. Seidl, D. Schumann","doi":"10.1109/IEDM.2001.979481","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979481","url":null,"abstract":"This work is intended to draw attention to the effect of dielectric relaxation which is shown to severely influence the performance of alternative dielectrics in DRAM storage capacitors as well as of the gate dielectrics of MOSFETs. A comparison of the dielectric relaxation losses in standard insulators with those in most proposed high K dielectrics is presented.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"23 1","pages":"12.2.1-12.2.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86775042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979527
K. Guarini, Paul M. Solomon, Yuan Zhang, Kevin K. Chan, E. C. Jones, Guy M. Cohen, A. Krasnoperova, M. Ronay, O. Dokumaci, J. J. Bucchignano, Cyril Cabral, Christian Lavoie, Victor Ku, Diane C. Boyd, K. Petrarca, I. V. Babich, J. Treichler, P. Kozlowski, J. Newbury, C. D'Emic, R. M. Sicina, Hon-Sum Philip Wong
We introduce a planar, triple-self-aligned double-gate FET structure ("PAGODA"). Device fabrication incorporates wafer bonding, front-end CMP, mixed optical/e-beam lithography, silicided silicon source/drain sidewalls, and back gate undercut and passivation. We demonstrate double-gate FET operation with good transport at both interfaces, inverter action, and NOR logic.
{"title":"Triple-self-aligned, planar double-gate MOSFETs: devices and circuits","authors":"K. Guarini, Paul M. Solomon, Yuan Zhang, Kevin K. Chan, E. C. Jones, Guy M. Cohen, A. Krasnoperova, M. Ronay, O. Dokumaci, J. J. Bucchignano, Cyril Cabral, Christian Lavoie, Victor Ku, Diane C. Boyd, K. Petrarca, I. V. Babich, J. Treichler, P. Kozlowski, J. Newbury, C. D'Emic, R. M. Sicina, Hon-Sum Philip Wong","doi":"10.1109/IEDM.2001.979527","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979527","url":null,"abstract":"We introduce a planar, triple-self-aligned double-gate FET structure (\"PAGODA\"). Device fabrication incorporates wafer bonding, front-end CMP, mixed optical/e-beam lithography, silicided silicon source/drain sidewalls, and back gate undercut and passivation. We demonstrate double-gate FET operation with good transport at both interfaces, inverter action, and NOR logic.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"66 1","pages":"19.2.1-19.2.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90053433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979639
S. Sugawa, I. Ohshima, H. Ishino, Y. Saito, M. Hirayama, T. Ohmi
We have succeeded to prepare a hgh quality silicon nitride gate insulator with lower gate leakage current in three orders of magnitude compared to that of conventional thermal oxide film, by using a Kr/NH3 mixed gas microwave-excited highdensity plasma with metal (TaN/Ta/TaN) gate. Moreover, we have evaluated the current drive capability dependence on the silicon surface orientation and found that the channel hole mobility on (110) surface at the channel-width direction of 13 5 degree from the (111) cut plane was 2.4 times hlgher than that of (100) surface. The CMOS transistor with the silicon nitride gate insulator formed by the microwave-excited plasma and TaN/Ta/TaN metal gate on (110) surface orientation silicon having a higher current drive capability and high integration density is the most practical candidate for lOOnm technology node and beyond.
{"title":"Advantage of silicon nitride gate insulator transistor by using microwave excited high-density plasma for applying 100nm technology node","authors":"S. Sugawa, I. Ohshima, H. Ishino, Y. Saito, M. Hirayama, T. Ohmi","doi":"10.1109/IEDM.2001.979639","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979639","url":null,"abstract":"We have succeeded to prepare a hgh quality silicon nitride gate insulator with lower gate leakage current in three orders of magnitude compared to that of conventional thermal oxide film, by using a Kr/NH3 mixed gas microwave-excited highdensity plasma with metal (TaN/Ta/TaN) gate. Moreover, we have evaluated the current drive capability dependence on the silicon surface orientation and found that the channel hole mobility on (110) surface at the channel-width direction of 13 5 degree from the (111) cut plane was 2.4 times hlgher than that of (100) surface. The CMOS transistor with the silicon nitride gate insulator formed by the microwave-excited plasma and TaN/Ta/TaN metal gate on (110) surface orientation silicon having a higher current drive capability and high integration density is the most practical candidate for lOOnm technology node and beyond.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"78 4 1","pages":"37.3_1-37.3_4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83494956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979661
N. Sato, K. Machida, H. Morimura, S. Shigematsu, K. Kudou, M. Yano, H. Kyuragi
We propose a MEMS (Micro Electro Mechanical Systems) fingerprint sensor whose pixels have novel cavity structures. Each cavity structure has a sensitive plane of a thin film on top, and a sensing circuit below it. Ridges on a finger surface bend the thin film mechanically, which is detected by the sensing circuit electronically. We fabricated the sensor using a CMOS compatible process with our sealing technique. The sensor can obtain fingerprint images of even dry or wet fingers. It also shows sufficient mechanical strength against finger pressure. These results confirm that the MEMS fingerprint sensor has the potential for wide practical application.
{"title":"MEMS fingerprint sensor with arrayed cavity structures","authors":"N. Sato, K. Machida, H. Morimura, S. Shigematsu, K. Kudou, M. Yano, H. Kyuragi","doi":"10.1109/IEDM.2001.979661","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979661","url":null,"abstract":"We propose a MEMS (Micro Electro Mechanical Systems) fingerprint sensor whose pixels have novel cavity structures. Each cavity structure has a sensitive plane of a thin film on top, and a sensing circuit below it. Ridges on a finger surface bend the thin film mechanically, which is detected by the sensing circuit electronically. We fabricated the sensor using a CMOS compatible process with our sealing technique. The sensor can obtain fingerprint images of even dry or wet fingers. It also shows sufficient mechanical strength against finger pressure. These results confirm that the MEMS fingerprint sensor has the potential for wide practical application.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"15 1","pages":"41.2.1-41.2.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81953158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979551
T. Ezaki, H. Nakasato, M. Hane
A new MOSFET device simulator has been developed based on a coupled Monte Carlo procedure for the carrier transport in both Si and SiO/sub 2/ regions. This simulator accounts for the image force effect that modulates potential barrier height for the electrons injected into the SiO/sub 2/. Gate currents are calculated combining both the hot carrier injection and the back-scattering from the SiO/sub 2/ region arising from the potential modulation. Flash memory cell simulations were performed by this method. The actual MOSFET gate currents and the programming characteristics of the flash memory cells could be reproduced quantitatively without using any adjustable parameters.
{"title":"Coupled Si and SiO/sub 2/ Monte Carlo device simulator for accurate gate current calculation","authors":"T. Ezaki, H. Nakasato, M. Hane","doi":"10.1109/IEDM.2001.979551","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979551","url":null,"abstract":"A new MOSFET device simulator has been developed based on a coupled Monte Carlo procedure for the carrier transport in both Si and SiO/sub 2/ regions. This simulator accounts for the image force effect that modulates potential barrier height for the electrons injected into the SiO/sub 2/. Gate currents are calculated combining both the hot carrier injection and the back-scattering from the SiO/sub 2/ region arising from the potential modulation. Flash memory cell simulations were performed by this method. The actual MOSFET gate currents and the programming characteristics of the flash memory cells could be reproduced quantitatively without using any adjustable parameters.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"1 1","pages":"21.3.1-21.3.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90881515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979488
Sungkwon Hong, Yaohui Zhang, Y. Luo, T. Suligoj, Seong-Dong Kim, J. Woo, R. Li, B. Min, B. Hradsky, A. Vandooren, B. Nguyen, K. Wang
A novel method for accurate gate length extraction has been developed using direct tunneling current (DTC) through thin gate oxide. Applied to decanano CMOS devices, the proposed method is verified to be free from a severe assumption of unified effective mobility that is one of limitations of conventional method to sub-0.1 /spl mu/m. The DTC method is also insensitive to doping concentration and gate oxide thinning effect at the corner regions. In addition, we have studied the channel length dependence on gate line-edge roughness by comparing the DTC method and the conventional channel current method.
{"title":"Novel direct-tunneling-current (DTC) method for channel length extraction beyond sub-50nm gate CMOS","authors":"Sungkwon Hong, Yaohui Zhang, Y. Luo, T. Suligoj, Seong-Dong Kim, J. Woo, R. Li, B. Min, B. Hradsky, A. Vandooren, B. Nguyen, K. Wang","doi":"10.1109/IEDM.2001.979488","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979488","url":null,"abstract":"A novel method for accurate gate length extraction has been developed using direct tunneling current (DTC) through thin gate oxide. Applied to decanano CMOS devices, the proposed method is verified to be free from a severe assumption of unified effective mobility that is one of limitations of conventional method to sub-0.1 /spl mu/m. The DTC method is also insensitive to doping concentration and gate oxide thinning effect at the corner regions. In addition, we have studied the channel length dependence on gate line-edge roughness by comparing the DTC method and the conventional channel current method.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"8 1","pages":"13.4.1-13.4.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89703150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979447
R. Degraeve, B. Kaczer, F. Schuler, M. Lorenzini, D. Wellekens, P. Hendrickx, J. van Houdt, L. Haspeslagh, G. Tempel, G. Groeseneken
We present a statistical, unified picture of Stress-Induced Leakage Current (SILC) generation, pre-breakdown current steps and breakdown in 2.4 nm oxide layers during a constant voltage stress. Pre-breakdown current steps were investigated through gate voltage ramp measurements and modeled by means of a percolation model with variable trap-trap distance. During oxide stress, first single-trap conduction paths are formed, followed by two-trap conduction paths which are identified as pre-breakdown current steps in small devices. Finally, a highly conducting path is formed which triggers breakdown.
{"title":"Statistical model for stress-induced leakage current and pre-breakdown current jumps in ultra-thin oxide layers","authors":"R. Degraeve, B. Kaczer, F. Schuler, M. Lorenzini, D. Wellekens, P. Hendrickx, J. van Houdt, L. Haspeslagh, G. Tempel, G. Groeseneken","doi":"10.1109/IEDM.2001.979447","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979447","url":null,"abstract":"We present a statistical, unified picture of Stress-Induced Leakage Current (SILC) generation, pre-breakdown current steps and breakdown in 2.4 nm oxide layers during a constant voltage stress. Pre-breakdown current steps were investigated through gate voltage ramp measurements and modeled by means of a percolation model with variable trap-trap distance. During oxide stress, first single-trap conduction paths are formed, followed by two-trap conduction paths which are identified as pre-breakdown current steps in small devices. Finally, a highly conducting path is formed which triggers breakdown.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"1 1","pages":"6.2.1-6.2.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89752963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979489
K. Nomoto, U. Fujiwara, H. Aozasa, T. Terano, T. Kobayashi
Investigated the relation between the density of Si-H/N-H bonds and the programming characteristics of scaled metal-oxide-nitride-oxide-semiconductor (MONOS) memory devices and developed an analytical model for programming characteristics of the MONOS devices having a variety of trap densities. The model was validated experimentally. We apply the model to a metal-oxide-nitride-semiconductor (MONS) memory device with trap-density modulation in the nitride layer. The result shows the MONS memory is programmed faster and at lower-voltage than the conventional MONOS memory device.
{"title":"Analytical model of the programming characteristics of scaled MONOS memories with a variety of trap densities and a proposal of a trap-density-modulated MONS memory","authors":"K. Nomoto, U. Fujiwara, H. Aozasa, T. Terano, T. Kobayashi","doi":"10.1109/IEDM.2001.979489","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979489","url":null,"abstract":"Investigated the relation between the density of Si-H/N-H bonds and the programming characteristics of scaled metal-oxide-nitride-oxide-semiconductor (MONOS) memory devices and developed an analytical model for programming characteristics of the MONOS devices having a variety of trap densities. The model was validated experimentally. We apply the model to a metal-oxide-nitride-semiconductor (MONS) memory device with trap-density modulation in the nitride layer. The result shows the MONS memory is programmed faster and at lower-voltage than the conventional MONOS memory device.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"9 28 1","pages":"13.5.1-13.5.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75098976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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