Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979451
A. Shanware, J. McPherson, M. Visokay, J. J. Chambers, A. Rotondaro, H. Bu, M. Bevan, R. Khamankar, L. Colombo
Alternate gate-dielectric films are required for future replacement of conventional SiO/sub 2/. Replacement is needed to reduce gate-leakage while still maintaining good reliability and a high-level of transistor performance. One such candidate is HfSiON dielectric film. In this paper we report for the first time, IV and CV characteristics, stability and reliability results for amorphous HfSiON dielectric films scaled below 13 /spl Aring/. Our results show that leakage current through this material is reduced by two orders of magnitude versus an equivalent SiO/sub 2/ film, while the interface and TDDB stability remains good. The positive leakage, stability and reliability results indicate that HfSiON may be a suitable candidate for gate-oxide replacement in CMOS applications where an effective hyper-thin gate-oxide is required for performance reasons and a reduced gate-leakage for low-power applications.
{"title":"Reliability evaluation of HfSiON gate dielectric film with 12.8 /spl Aring/ SiO/sub 2/ equivalent thickness","authors":"A. Shanware, J. McPherson, M. Visokay, J. J. Chambers, A. Rotondaro, H. Bu, M. Bevan, R. Khamankar, L. Colombo","doi":"10.1109/IEDM.2001.979451","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979451","url":null,"abstract":"Alternate gate-dielectric films are required for future replacement of conventional SiO/sub 2/. Replacement is needed to reduce gate-leakage while still maintaining good reliability and a high-level of transistor performance. One such candidate is HfSiON dielectric film. In this paper we report for the first time, IV and CV characteristics, stability and reliability results for amorphous HfSiON dielectric films scaled below 13 /spl Aring/. Our results show that leakage current through this material is reduced by two orders of magnitude versus an equivalent SiO/sub 2/ film, while the interface and TDDB stability remains good. The positive leakage, stability and reliability results indicate that HfSiON may be a suitable candidate for gate-oxide replacement in CMOS applications where an effective hyper-thin gate-oxide is required for performance reasons and a reduced gate-leakage for low-power applications.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"33 1","pages":"6.6.1-6.6.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87148815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979555
H. Ho, M. Steigerwalt, B. Walsh, T.L. Doney, D. Wildrick, P. McFarland, J. Benedict, K. Bard, D. Pendleton, J.D. Lee, S. Maurer, B. Corrow, D. Sadana
Reports the successful implementation of a 0.13 /spl mu/m high-performance, silicon-on-insulator (SOI) logic technology to produce a 0.13 /spl mu/m logic-based embedded DRAM (eDRAM) on substrates composed of both bulk Si and SOI or pattern SOI. eDRAM macros are constructed in bulk regions of the wafer and high-performance logic circuits lie on SOI. Pattern SOI wafers are produced by blocking out selected regions of p-type Si wafers from the separation by implantation of oxygen (SIMOX) implant using a thick (> 1 /spl mu/m) hard mask. Test results indicate that SOI eDRAM yield and retention characteristics are comparable to bulk eDRAM. Based on ring oscillator tests, the use of 0.13 /spl mu/m SOI logic devices improves switching speeds by >20% over 0.13 /spl mu/m bulk technology at 1.2 Vdd. These results pave the way for future generations of low power SOI system-on-a-chip (SOC) applications, starting at the 0.1 /spl mu/m node.
{"title":"A 0.13 /spl mu/m high-performance SOI logic technology with embedded DRAM for system-on-a-chip application","authors":"H. Ho, M. Steigerwalt, B. Walsh, T.L. Doney, D. Wildrick, P. McFarland, J. Benedict, K. Bard, D. Pendleton, J.D. Lee, S. Maurer, B. Corrow, D. Sadana","doi":"10.1109/IEDM.2001.979555","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979555","url":null,"abstract":"Reports the successful implementation of a 0.13 /spl mu/m high-performance, silicon-on-insulator (SOI) logic technology to produce a 0.13 /spl mu/m logic-based embedded DRAM (eDRAM) on substrates composed of both bulk Si and SOI or pattern SOI. eDRAM macros are constructed in bulk regions of the wafer and high-performance logic circuits lie on SOI. Pattern SOI wafers are produced by blocking out selected regions of p-type Si wafers from the separation by implantation of oxygen (SIMOX) implant using a thick (> 1 /spl mu/m) hard mask. Test results indicate that SOI eDRAM yield and retention characteristics are comparable to bulk eDRAM. Based on ring oscillator tests, the use of 0.13 /spl mu/m SOI logic devices improves switching speeds by >20% over 0.13 /spl mu/m bulk technology at 1.2 Vdd. These results pave the way for future generations of low power SOI system-on-a-chip (SOC) applications, starting at the 0.1 /spl mu/m node.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"27 1","pages":"22.3.1-22.3.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87252688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979646
L. S. Adam, M. Law, S. Hegde, O. Dokumaci
Nitrogen implantation allows the implementation of varying oxide thickness in the same process. At IEDM 2000, we have shown an integrated nitrogen diffusion-oxidation model to predict the gate oxide thickness. In this paper, we describe further experiments and modeling to explain the diffusion behavior of implanted nitrogen in silicon that lead to a substantial improvement in both the extent of data fit and understanding of the process physics. We show that the model is consistent with three new experimental studies. The improved model now predicts the formation of extended defects from nitrogen implants, correlates well with positron annihilation studies, and agrees with the diffusion results when the damage is changed by co-implants of silicon. The improved model is valid over a wider range of conditions.
{"title":"Comprehensive model for nitrogen diffusion in silicon","authors":"L. S. Adam, M. Law, S. Hegde, O. Dokumaci","doi":"10.1109/IEDM.2001.979646","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979646","url":null,"abstract":"Nitrogen implantation allows the implementation of varying oxide thickness in the same process. At IEDM 2000, we have shown an integrated nitrogen diffusion-oxidation model to predict the gate oxide thickness. In this paper, we describe further experiments and modeling to explain the diffusion behavior of implanted nitrogen in silicon that lead to a substantial improvement in both the extent of data fit and understanding of the process physics. We show that the model is consistent with three new experimental studies. The improved model now predicts the formation of extended defects from nitrogen implants, correlates well with positron annihilation studies, and agrees with the diffusion results when the damage is changed by co-implants of silicon. The improved model is valid over a wider range of conditions.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"7 1","pages":"38.5.1-38.5.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86008139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979622
A. Hara, Y. Mishima, T. Kakehi, F. Takeuchi, M. Takei, K. Yoshino, K. Suga, M. Chida, N. Sasaki
We have developed high performance poly-Si TFTs, which have comparable performance to that of [100] Si-MOSFETs, by using a stable scanning DPSS CW laser lateral crystallization without introduction of thermal damage to 300/spl times/300 mm/sup 2/ glass substrates with process temperature below 450/spl deg/C.
{"title":"High performance poly-Si TFTs on a glass by a stable scanning CW laser lateral crystallization","authors":"A. Hara, Y. Mishima, T. Kakehi, F. Takeuchi, M. Takei, K. Yoshino, K. Suga, M. Chida, N. Sasaki","doi":"10.1109/IEDM.2001.979622","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979622","url":null,"abstract":"We have developed high performance poly-Si TFTs, which have comparable performance to that of [100] Si-MOSFETs, by using a stable scanning DPSS CW laser lateral crystallization without introduction of thermal damage to 300/spl times/300 mm/sup 2/ glass substrates with process temperature below 450/spl deg/C.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"100 4 1","pages":"34.2.1-34.2.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77562461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979505
K. Oda, E. Ohue, I. Suzumura, R. Hayami, A. Kodama, H. Shimamoto, K. Washio
Si/sub 1-x-y/Ge/sub x/C/sub y/ selective epitaxial growth (SEG) was performed by cold-wall ultra-high-vacuum chemical vapor deposition (UHV/CVD), and a Si/sub 1-x-y/Ge/sub x/C/sub y/ layer with good crystallinity was produced by optimizing the growth conditions. As a result of applying Si/sub 1-x-y/Ge/sub x/C/sub y/ SEG to form the base of a self-aligned heterojunction bipolar transistor (HBT), device performance was significantly improved by suppression of B outdiffusion; namely, a maximum oscillation frequency of 174 GHz was obtained.
{"title":"Self-aligned selective-epitaxial-growth Si/sub 1-x-y/Ge/sub x/C/sub y/ HBT technology featuring 170-GHz f/sub max/","authors":"K. Oda, E. Ohue, I. Suzumura, R. Hayami, A. Kodama, H. Shimamoto, K. Washio","doi":"10.1109/IEDM.2001.979505","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979505","url":null,"abstract":"Si/sub 1-x-y/Ge/sub x/C/sub y/ selective epitaxial growth (SEG) was performed by cold-wall ultra-high-vacuum chemical vapor deposition (UHV/CVD), and a Si/sub 1-x-y/Ge/sub x/C/sub y/ layer with good crystallinity was produced by optimizing the growth conditions. As a result of applying Si/sub 1-x-y/Ge/sub x/C/sub y/ SEG to form the base of a self-aligned heterojunction bipolar transistor (HBT), device performance was significantly improved by suppression of B outdiffusion; namely, a maximum oscillation frequency of 174 GHz was obtained.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"1 1","pages":"15.2.1-15.2.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81162487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979416
K. Mosig, H. Cox, E. Klawuhn, T. Suwwan de Felipe, A. Shiota
The International Technology Roadmap for Semiconductors predicts the need for ultra low-k dielectric materials combined with very thin barriers on the order of 5 nm total thickness for the use in high performance logic integrated circuits in future technology generations. Some progress has been reported recently regarding the integration of copper with new, relatively weak, ultra low-k materials and the development of new ultra-thin CVD barriers. However there is still considerable concern about the interaction between porous low-k materials and CVD barriers, especially diffusion of CVD precursors into the pores of the low-k material and subsequent metal deposition inside the low-k material. This paper describes the integration of a new CVD barrier with a porous ultra low-k material. First results are discussed for integration into both single and dual damascene structures.
{"title":"Integration of porous ultra low-k dielectric with CVD barriers","authors":"K. Mosig, H. Cox, E. Klawuhn, T. Suwwan de Felipe, A. Shiota","doi":"10.1109/IEDM.2001.979416","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979416","url":null,"abstract":"The International Technology Roadmap for Semiconductors predicts the need for ultra low-k dielectric materials combined with very thin barriers on the order of 5 nm total thickness for the use in high performance logic integrated circuits in future technology generations. Some progress has been reported recently regarding the integration of copper with new, relatively weak, ultra low-k materials and the development of new ultra-thin CVD barriers. However there is still considerable concern about the interaction between porous low-k materials and CVD barriers, especially diffusion of CVD precursors into the pores of the low-k material and subsequent metal deposition inside the low-k material. This paper describes the integration of a new CVD barrier with a porous ultra low-k material. First results are discussed for integration into both single and dual damascene structures.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"62 1","pages":"4.5.1-4.5.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88979159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979617
Maddala Teja Kiran Kumar, Haitao Liu, J. Sin, J. Wan, K. Wang
In this paper, a novel 3-D BiCMOS technology is proposed and demonstrated for the first time. To implement the 3-D BiCMOS structure, NMOS transistors are fabricated on the bulk substrate (bottom layer), PMOS transistors are fabricated on the single crystal top layer which is obtained using selective epitaxial growth (SEG) and lateral solid phase epitaxy (LSPE), and BJTs are fabricated in the SEG regions. The mobility of the PMOS transistors fabricated on the top layer is only approximately 5% lower than those fabricated on SOI wafers, and the BJTs also have high performance with a peak f/sub T/ of 17 GHz and a peak f/sub max/ of 14 GHz. This 3-D BiCMOS technology is very promising for low power, high speed, and high frequency integrated circuits applications.
{"title":"A 3-D BiCMOS technology using selective epitaxial growth (SEG) and lateral solid phase epitaxy (LSPE)","authors":"Maddala Teja Kiran Kumar, Haitao Liu, J. Sin, J. Wan, K. Wang","doi":"10.1109/IEDM.2001.979617","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979617","url":null,"abstract":"In this paper, a novel 3-D BiCMOS technology is proposed and demonstrated for the first time. To implement the 3-D BiCMOS structure, NMOS transistors are fabricated on the bulk substrate (bottom layer), PMOS transistors are fabricated on the single crystal top layer which is obtained using selective epitaxial growth (SEG) and lateral solid phase epitaxy (LSPE), and BJTs are fabricated in the SEG regions. The mobility of the PMOS transistors fabricated on the top layer is only approximately 5% lower than those fabricated on SOI wafers, and the BJTs also have high performance with a peak f/sub T/ of 17 GHz and a peak f/sub max/ of 14 GHz. This 3-D BiCMOS technology is very promising for low power, high speed, and high frequency integrated circuits applications.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"28 1","pages":"33.2.1-33.2.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87555598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979642
V. Senez, T. Hoffmann, E. Robilliart, G. Bouché, H. Jaouen, M. Lunenborg, G. Carnevale
This paper presents a mechanical analysis of the entire process flow (i.e.: Front (FEOL) and Back (BEOL) End of Line) of a 0.12 CMOS technology using 2D numerical modeling. This study gives several quantitative modifications concerning the process conditions and device geometries in order to reduce the residual mechanical stress in the devices.
{"title":"Investigations of stress sensitivity of 0.12 CMOS technology using process modeling","authors":"V. Senez, T. Hoffmann, E. Robilliart, G. Bouché, H. Jaouen, M. Lunenborg, G. Carnevale","doi":"10.1109/IEDM.2001.979642","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979642","url":null,"abstract":"This paper presents a mechanical analysis of the entire process flow (i.e.: Front (FEOL) and Back (BEOL) End of Line) of a 0.12 CMOS technology using 2D numerical modeling. This study gives several quantitative modifications concerning the process conditions and device geometries in order to reduce the residual mechanical stress in the devices.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"25 1","pages":"38.1.1-38.1.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85036961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979597
Dae-gyu Park, Taeho Cha, K. Lim, Heung-Jae Cho, Tae-Kyun Kim, S. Jang, You-Seok Suh, V. Misra, I. Yeo, J. Roh, J. Park, H. Yoon
This report describes thermally stable dual metal gate electrodes for surface channel Si CMOS devices. We found that the ternary metal nitrides, i.e., Ti/sub 1-x/Al/sub x/N/sub y/ (TiAlN) and TaSi/sub x/N/sub y/ (TaSiN) films, are stable up to 1000/spl deg/C. Especially, the stoichiometric TiAlN (y/spl sim/1) exhibited highly robust p-type gate electrode (p-TiAlN) properties, demonstrating a work function (/spl Phi//sub m/) of /spl sim/5.1 eV and excellent gate oxide integrity against the thermal budget of conventional Si CMOS processing. The N-deficient TiAlN (y < 1) showed /spl Phi//sub m/ for n-type electrode (n-TiAlN) with limited thermal stability. The dual gate electrodes, p-TiAlN and TaSiN, exhibited negligible EOT (equivalent oxide thickness) variation on the high-k gate dielectrics (ZrO/sub 2/, HfO/sub 2/) up to 950/spl deg/C.
{"title":"Robust ternary metal gate electrodes for dual gate CMOS devices","authors":"Dae-gyu Park, Taeho Cha, K. Lim, Heung-Jae Cho, Tae-Kyun Kim, S. Jang, You-Seok Suh, V. Misra, I. Yeo, J. Roh, J. Park, H. Yoon","doi":"10.1109/IEDM.2001.979597","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979597","url":null,"abstract":"This report describes thermally stable dual metal gate electrodes for surface channel Si CMOS devices. We found that the ternary metal nitrides, i.e., Ti/sub 1-x/Al/sub x/N/sub y/ (TiAlN) and TaSi/sub x/N/sub y/ (TaSiN) films, are stable up to 1000/spl deg/C. Especially, the stoichiometric TiAlN (y/spl sim/1) exhibited highly robust p-type gate electrode (p-TiAlN) properties, demonstrating a work function (/spl Phi//sub m/) of /spl sim/5.1 eV and excellent gate oxide integrity against the thermal budget of conventional Si CMOS processing. The N-deficient TiAlN (y < 1) showed /spl Phi//sub m/ for n-type electrode (n-TiAlN) with limited thermal stability. The dual gate electrodes, p-TiAlN and TaSiN, exhibited negligible EOT (equivalent oxide thickness) variation on the high-k gate dielectrics (ZrO/sub 2/, HfO/sub 2/) up to 950/spl deg/C.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"8 1","pages":"30.6.1-30.6.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82383958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979615
H. Ishiwara
Current status and prospects of ferroelectric random access memories (FeRAMs) are reviewed. First, novel ferroelectric materials, which are suitable for both low temperature crystallization and low voltage operation are introduced. Then, various cell structures in FeRAMs are discussed, in which particular attention is paid to non-destructive-readout-type cells such as a 1T-type cell composed of a single ferroelectric-gate FET. Finally, a novel 1T2C-type non-destructive-readout cell with good data retention characteristic is introduced and its basic operation is presented.
{"title":"Current status and prospects of ferroelectric memories","authors":"H. Ishiwara","doi":"10.1109/IEDM.2001.979615","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979615","url":null,"abstract":"Current status and prospects of ferroelectric random access memories (FeRAMs) are reviewed. First, novel ferroelectric materials, which are suitable for both low temperature crystallization and low voltage operation are introduced. Then, various cell structures in FeRAMs are discussed, in which particular attention is paid to non-destructive-readout-type cells such as a 1T-type cell composed of a single ferroelectric-gate FET. Finally, a novel 1T2C-type non-destructive-readout cell with good data retention characteristic is introduced and its basic operation is presented.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"21 1","pages":"33.1.1-33.1.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84465919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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