Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979596
Y.H. Kim, C. Lee, T. Jeon, W. Bai, C. Choi, S.J. Lee, L. Xinjian, R. Clarks, D. Roberts, D. Kwong
In this paper, for the first time, we present a detailed evaluation of physical and electrical properties of CVD TaN as a potential gate electrode material for sub-100 nm MOS device applications. Our results show that CVD TaN films deposited using TBTDET (tertbutylimidoirisdiethylamido tantalum) exhibit excellent thermal stability with underlying ultra thin SiO/sub 2/ up to 1000/spl deg/C and extremely stable work function (5eV@800-1000/spl deg/C) suitable for p-MOS device applications. Compared to PVD TaN, MOS devices with CVD TaN gate electrode show desirable work function for p-MOS devices, excellent stability of gate oxide thickness, leakage current, and interface properties during high-temperature annealing, and superior gate dielectric TDDB reliability. These results suggest that CVD TaN can be used as the gate electrode on ultra thin gate oxide in self-aligned gate-first CMOS processing.
{"title":"High quality CVD TaN gate electrode for sub-100 nm MOS devices","authors":"Y.H. Kim, C. Lee, T. Jeon, W. Bai, C. Choi, S.J. Lee, L. Xinjian, R. Clarks, D. Roberts, D. Kwong","doi":"10.1109/IEDM.2001.979596","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979596","url":null,"abstract":"In this paper, for the first time, we present a detailed evaluation of physical and electrical properties of CVD TaN as a potential gate electrode material for sub-100 nm MOS device applications. Our results show that CVD TaN films deposited using TBTDET (tertbutylimidoirisdiethylamido tantalum) exhibit excellent thermal stability with underlying ultra thin SiO/sub 2/ up to 1000/spl deg/C and extremely stable work function (5eV@800-1000/spl deg/C) suitable for p-MOS device applications. Compared to PVD TaN, MOS devices with CVD TaN gate electrode show desirable work function for p-MOS devices, excellent stability of gate oxide thickness, leakage current, and interface properties during high-temperature annealing, and superior gate dielectric TDDB reliability. These results suggest that CVD TaN can be used as the gate electrode on ultra thin gate oxide in self-aligned gate-first CMOS processing.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"106 1","pages":"30.5.1-30.5.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85541167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979667
M. Inohara, T. Fujimaki, K. Yoshida, K. Miyamoto, T. Katata, J. Wada, A. Sakata, A. Kinoshita, F. Matsuoka
A copper filling contact process that does not cause any device characteristic degradation or reliability degradation is demonstrated. Optimization of the barrier layer realizes lower and small variation contact resistance with enough prevention of copper diffusion from the contact hole. Copper filling realizes a 65% reduction of contact resistance in 0.16 /spl mu/m diameter contacts and very small contact depth dependence. There is no degradation of junction leakage current and no difference in reliability characteristics compared to a conventional tungsten filling process. Gate oxide TDDB and hot carrier injection test results are shown. Another benefit of the copper filling process is lower production cost. Dual damascene structures for contact and metal-1 reduce process steps by 40%. Furthermore, investment for tungsten filling machines is saved because BEOL processes can be switched to copper filling for 0.13 /spl mu/m generations. Especially, in a 300 mm wafer fabrication line, the decrease in the varieties of machines will be significant.
{"title":"Copper filling contact process to realize low resistance and low cost production fully compatible to SOC devices","authors":"M. Inohara, T. Fujimaki, K. Yoshida, K. Miyamoto, T. Katata, J. Wada, A. Sakata, A. Kinoshita, F. Matsuoka","doi":"10.1109/IEDM.2001.979667","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979667","url":null,"abstract":"A copper filling contact process that does not cause any device characteristic degradation or reliability degradation is demonstrated. Optimization of the barrier layer realizes lower and small variation contact resistance with enough prevention of copper diffusion from the contact hole. Copper filling realizes a 65% reduction of contact resistance in 0.16 /spl mu/m diameter contacts and very small contact depth dependence. There is no degradation of junction leakage current and no difference in reliability characteristics compared to a conventional tungsten filling process. Gate oxide TDDB and hot carrier injection test results are shown. Another benefit of the copper filling process is lower production cost. Dual damascene structures for contact and metal-1 reduce process steps by 40%. Furthermore, investment for tungsten filling machines is saved because BEOL processes can be switched to copper filling for 0.13 /spl mu/m generations. Especially, in a 300 mm wafer fabrication line, the decrease in the varieties of machines will be significant.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"20 1","pages":"4.6.1-4.6.3"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78261376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979631
A. Sokolich, S. Thomas, C. Fields
We demonstrate an InP-based high-speed, low-power HBT technology with 180 GHz cutoff frequency. Current Mode Logic (CML) static dividers at 64 GHz maximum toggle rate at a power dissipation of 29 mW/flip-flop and 16 GHz maximum toggle rate at a power dissipation of 1.8 mW/flip-flop show that the technology is applicable to dense 40 Gbps logic circuits. Submicron InP HBT technology opens up the possibility of one thousand logic gates all operating at 10-40 GHz clock rates at a few watts of total power dissipation.
{"title":"High-speed and low-power InAlAs/InGaAs heterojunction bipolar transistors for dense ultra high speed digital applications","authors":"A. Sokolich, S. Thomas, C. Fields","doi":"10.1109/IEDM.2001.979631","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979631","url":null,"abstract":"We demonstrate an InP-based high-speed, low-power HBT technology with 180 GHz cutoff frequency. Current Mode Logic (CML) static dividers at 64 GHz maximum toggle rate at a power dissipation of 29 mW/flip-flop and 16 GHz maximum toggle rate at a power dissipation of 1.8 mW/flip-flop show that the technology is applicable to dense 40 Gbps logic circuits. Submicron InP HBT technology opens up the possibility of one thousand logic gates all operating at 10-40 GHz clock rates at a few watts of total power dissipation.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"49 1","pages":"35.5.1-35.5.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73571165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979558
K. Takeuchi, T. Mogami
A simple method for determining the optimal use of multiple transistor parameters (MP), i.e. multiple V/sub TH/, V/sub DD/, and T/sub OX/, for System-on-a-Chip's (SoC's) is proposed. Reasonable optimization results are automatically obtained for various SoC configurations, which is difficult to achieve intuitively. It was found that the MP design is particularly effective for SoC's consisting of circuit blocks with different speed requirements.
{"title":"A new multiple transistor parameter design methodology for high speed low power SoCs","authors":"K. Takeuchi, T. Mogami","doi":"10.1109/IEDM.2001.979558","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979558","url":null,"abstract":"A simple method for determining the optimal use of multiple transistor parameters (MP), i.e. multiple V/sub TH/, V/sub DD/, and T/sub OX/, for System-on-a-Chip's (SoC's) is proposed. Reasonable optimization results are automatically obtained for various SoC configurations, which is difficult to achieve intuitively. It was found that the MP design is particularly effective for SoC's consisting of circuit blocks with different speed requirements.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"89 1","pages":"22.6.1-22.6.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82380729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979480
Wan-Don Kim, J. Joo, Y. Jeong, Seok-jun Won, Soon-yeon Park, Sung-Choon Lee, C. Yoo, Sung-tae Kim, J. Moon
RIR(Ru/Crystalline-Ta/sub 2/O/sub 5/Ru) capacitor with concave structure was studied for the application into multigigabit-scale DRAM device. In this work, several novel technologies were successfully developed to solve current issues in the fabrication of RIR concave capacitor; such as 1) two-step deposition of Ta/sub 2/O/sub 5/ films 2) formation of Ta/sub 2/O/sub 5/ spacer 3) new separation process of Ru storage node using maskless etch-back method 4) H/sub 2/ pre-annealing and 5) Ar plasma pre-treatment on Ru bottom electrode. The RIR concave capacitor (design rule/spl sim/0.12 /spl mu/m, node height/spl sim/0.85 /spl mu/m) fabricated with these novel technologies showed excellent electrical properties (25fF/cell, 1fA/cell at /spl plusmn/ 1V), which indicates that RIR structure is the one of the most promising candidate for the next generation DRAM capacitor.
{"title":"Development of CVD-Ru/Ta/sub 2/O/sub 5//CVD-Ru capacitor with concave structure for multigigabit-scale DRAM generation","authors":"Wan-Don Kim, J. Joo, Y. Jeong, Seok-jun Won, Soon-yeon Park, Sung-Choon Lee, C. Yoo, Sung-tae Kim, J. Moon","doi":"10.1109/IEDM.2001.979480","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979480","url":null,"abstract":"RIR(Ru/Crystalline-Ta/sub 2/O/sub 5/Ru) capacitor with concave structure was studied for the application into multigigabit-scale DRAM device. In this work, several novel technologies were successfully developed to solve current issues in the fabrication of RIR concave capacitor; such as 1) two-step deposition of Ta/sub 2/O/sub 5/ films 2) formation of Ta/sub 2/O/sub 5/ spacer 3) new separation process of Ru storage node using maskless etch-back method 4) H/sub 2/ pre-annealing and 5) Ar plasma pre-treatment on Ru bottom electrode. The RIR concave capacitor (design rule/spl sim/0.12 /spl mu/m, node height/spl sim/0.85 /spl mu/m) fabricated with these novel technologies showed excellent electrical properties (25fF/cell, 1fA/cell at /spl plusmn/ 1V), which indicates that RIR structure is the one of the most promising candidate for the next generation DRAM capacitor.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"3 1","pages":"12.1.1-12.1.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82319350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979569
Ching-Chun Wang, C. Sodini
Excess minority carriers induced by hot carriers in source follower transistors in active pixel sensors are experimentally observed using sensor arrays fabricated with a standard 0.35-/spl mu/m CMOS process. The number of carriers absorbed by photodiodes depends on bias conditions of the transistors and consequently becomes optical-signal dependent. A cascoded 4-T active pixel sensor is more sensitive to this effect due to its small sensing capacitance. Temperature varying experiments are performed to confirm this mechanism. The spatial distribution of the excess carriers is quantified to be within /spl sim/30 /spl mu/m around the source follower transistors. Suggestions on pixel design are provided.
{"title":"The effect of hot carriers on the operation of CMOS active pixel sensors","authors":"Ching-Chun Wang, C. Sodini","doi":"10.1109/IEDM.2001.979569","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979569","url":null,"abstract":"Excess minority carriers induced by hot carriers in source follower transistors in active pixel sensors are experimentally observed using sensor arrays fabricated with a standard 0.35-/spl mu/m CMOS process. The number of carriers absorbed by photodiodes depends on bias conditions of the transistors and consequently becomes optical-signal dependent. A cascoded 4-T active pixel sensor is more sensitive to this effect due to its small sensing capacitance. Temperature varying experiments are performed to confirm this mechanism. The spatial distribution of the excess carriers is quantified to be within /spl sim/30 /spl mu/m around the source follower transistors. Suggestions on pixel design are provided.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"54 1","pages":"24.5.1-24.5.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75981778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979575
N. Zhang, B. Moran, S. Denbaars, U. Mishra, X. W. Wang, T. Ma
As a competitive candidate for power switching electronics, GaN has slightly wider bandgap, higher electric strength, and higher saturated velocity than SiC. An insulating-gate structure GaN HEMT with a breakdown voltage of 1.3 kV was fabricated with a specific on-resistance of 1.7 m/spl Omega/.cm/sup 2/. State-of-the-art power device figure of merit of V/sub BR//sup 2//R/sub on/= 9.94/spl times/10/sup 8/ [V/sup 2//spl middot//spl Omega//sup -1/ cm/sup -2/] was achieved on this device. Device analysis shows that the surface traps play a dominant role in breakdown voltage and switching speed. High switching speed was realized on the kilo-volts devices by adoption of double gate dielectrics.
{"title":"Effects of surface traps on breakdown voltage and switching speed of GaN power switching HEMTs","authors":"N. Zhang, B. Moran, S. Denbaars, U. Mishra, X. W. Wang, T. Ma","doi":"10.1109/IEDM.2001.979575","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979575","url":null,"abstract":"As a competitive candidate for power switching electronics, GaN has slightly wider bandgap, higher electric strength, and higher saturated velocity than SiC. An insulating-gate structure GaN HEMT with a breakdown voltage of 1.3 kV was fabricated with a specific on-resistance of 1.7 m/spl Omega/.cm/sup 2/. State-of-the-art power device figure of merit of V/sub BR//sup 2//R/sub on/= 9.94/spl times/10/sup 8/ [V/sup 2//spl middot//spl Omega//sup -1/ cm/sup -2/] was achieved on this device. Device analysis shows that the surface traps play a dominant role in breakdown voltage and switching speed. High switching speed was realized on the kilo-volts devices by adoption of double gate dielectrics.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"32 1","pages":"25.5.1-25.5.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87781901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979513
R. Fair, M. Pollack, R. Woo, V. Pamula, R. Hong, T. Zhang, J. Venkatraman
In this work new data, models, and applications are presented of an ultra-low power, microfluidic device for use in integrated bio-microelectrofluidic systems (Bio-MEFS). The metal-insulator-solution transport (MIST) device is based on the high-speed manipulation of discrete droplets of analytes and reagents under voltage control, and is the MOSFET equivalent for MEFS.
{"title":"A micro-watt metal-insulator-solution-transport (MIST) device for scalable digital bio-microfluidic systems","authors":"R. Fair, M. Pollack, R. Woo, V. Pamula, R. Hong, T. Zhang, J. Venkatraman","doi":"10.1109/IEDM.2001.979513","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979513","url":null,"abstract":"In this work new data, models, and applications are presented of an ultra-low power, microfluidic device for use in integrated bio-microelectrofluidic systems (Bio-MEFS). The metal-insulator-solution transport (MIST) device is based on the high-speed manipulation of discrete droplets of analytes and reagents under voltage control, and is the MOSFET equivalent for MEFS.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"69 1","pages":"16.4.1-16.4.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86899371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979595
T. Yamaguchi, H. Satake, N. Fukushima
Zr-silicate thin films with different Zr concentrations, fabricated by low impact pulsed laser ablation deposition, have identically thin interface layers and smooth Si interfaces. By using these Zr-silicate samples, the influence of Si interface properties and that of bulk charges in the Zr-silicate on current drivability were distinguished for the first time. It was found that bulk charges in the Zr-silicate dielectrics greatly affect the current drivability of MISFETs, even if the interface-state density is small.
{"title":"Degradation of current drivability by the increase of Zr concentrations in Zr-silicate MISFET","authors":"T. Yamaguchi, H. Satake, N. Fukushima","doi":"10.1109/IEDM.2001.979595","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979595","url":null,"abstract":"Zr-silicate thin films with different Zr concentrations, fabricated by low impact pulsed laser ablation deposition, have identically thin interface layers and smooth Si interfaces. By using these Zr-silicate samples, the influence of Si interface properties and that of bulk charges in the Zr-silicate on current drivability were distinguished for the first time. It was found that bulk charges in the Zr-silicate dielectrics greatly affect the current drivability of MISFETs, even if the interface-state density is small.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"122 1","pages":"30.4.1-30.4.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88069654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979599
TingYen Chiang, S. Souri, C. O. Chui, K. C. Saraswat
Presents detailed thermal analysis of high performance three dimensional (3D) ICs under various integration schemes. The model incorporates the effect of vias and power consumption due to both devices in active layers and interconnect joule heating. The results show excellent agreement with the 3D finite element simulations using ANSYS. It is shown that under certain scenarios, 3D ICs can actually lead to better thermal performance than planar (2D) ICs. With the effect of vias, as efficient heat dissipation paths, taken into account, our model provides more realistic temperature rise estimation for 3D ICs. Furthermore, tradeoffs among power, performance, chip real estate and thermal impact for 3D ICs is evaluated. Finally, the thermal influence from incorporating RF circuits and optical interconnect on 3D ICs has been discussed.
{"title":"Thermal analysis of heterogeneous 3D ICs with various integration scenarios","authors":"TingYen Chiang, S. Souri, C. O. Chui, K. C. Saraswat","doi":"10.1109/IEDM.2001.979599","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979599","url":null,"abstract":"Presents detailed thermal analysis of high performance three dimensional (3D) ICs under various integration schemes. The model incorporates the effect of vias and power consumption due to both devices in active layers and interconnect joule heating. The results show excellent agreement with the 3D finite element simulations using ANSYS. It is shown that under certain scenarios, 3D ICs can actually lead to better thermal performance than planar (2D) ICs. With the effect of vias, as efficient heat dissipation paths, taken into account, our model provides more realistic temperature rise estimation for 3D ICs. Furthermore, tradeoffs among power, performance, chip real estate and thermal impact for 3D ICs is evaluated. Finally, the thermal influence from incorporating RF circuits and optical interconnect on 3D ICs has been discussed.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"1 1","pages":"31.2.1-31.2.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88320860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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