Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979496
Kwang-Hoon Oh, C. Duvvury, K. Banerjee, R. Dutton
This paper presents a detailed investigation of the degradation of ESD strength with gate bias for various deep submicron ESD protection designs. It has been shown for the first time that gate bias induced heating is the primary cause of this degradation. It has also been established that substrate biasing can help eliminate the negative impact of the gate bias effect, which has significant implications for the design of ESD protection circuits in deep submicron technologies.
{"title":"Gate bias induced heating effect and implications for the design of deep submicron ESD protection","authors":"Kwang-Hoon Oh, C. Duvvury, K. Banerjee, R. Dutton","doi":"10.1109/IEDM.2001.979496","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979496","url":null,"abstract":"This paper presents a detailed investigation of the degradation of ESD strength with gate bias for various deep submicron ESD protection designs. It has been shown for the first time that gate bias induced heating is the primary cause of this degradation. It has also been established that substrate biasing can help eliminate the negative impact of the gate bias effect, which has significant implications for the design of ESD protection circuits in deep submicron technologies.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"10 1","pages":"14.2.1-14.2.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79790195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979506
Marco Racanelli, K. Schuegraf, Amol Kalburge, A. Kar-Roy, B. Shen, Chenming Hu, D. Chapek, D. Howard, D. Quon, F. Wang, G. U'ren, L. Lao, H. Tu, J. Zheng, Jinshu Zhang, K. Bell, K. Yin, P. Joshi, S. Akhtar, S. Vo, T. Lee, W. Shi, P. Kempf
A scalable SiGe NPN demonstrating Ft*BVceo product of 340 GHz-V with Ft of 170 GHz and BVceo of 2.0 V together with Fmax of 160 GHz is presented. Peak Ft is reached at a relatively low current density of 6 mA//spl mu/m/sup 2/. The device is integrated in a 0.18 /spl mu/m BiCMOS process with dual-gate MOS transistors, high voltage NPN transistors, MIM capacitors, metal resistors, and 6 layers of metal including two layers of thick Cu for improved interconnect and inductor performance.
{"title":"Ultra high speed SiGe NPN for advanced BiCMOS technology","authors":"Marco Racanelli, K. Schuegraf, Amol Kalburge, A. Kar-Roy, B. Shen, Chenming Hu, D. Chapek, D. Howard, D. Quon, F. Wang, G. U'ren, L. Lao, H. Tu, J. Zheng, Jinshu Zhang, K. Bell, K. Yin, P. Joshi, S. Akhtar, S. Vo, T. Lee, W. Shi, P. Kempf","doi":"10.1109/IEDM.2001.979506","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979506","url":null,"abstract":"A scalable SiGe NPN demonstrating Ft*BVceo product of 340 GHz-V with Ft of 170 GHz and BVceo of 2.0 V together with Fmax of 160 GHz is presented. Peak Ft is reached at a relatively low current density of 6 mA//spl mu/m/sup 2/. The device is integrated in a 0.18 /spl mu/m BiCMOS process with dual-gate MOS transistors, high voltage NPN transistors, MIM capacitors, metal resistors, and 6 layers of metal including two layers of thick Cu for improved interconnect and inductor performance.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"151 1","pages":"15.3.1-15.3.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76836623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979459
A. Chin, C. Liang, C. Lin, C.C. Wu, J. Liu
We have studied the electroluminescence of ITO/Al/sub 2/O/sub 3/ superlattice tunnel diode on Si. The light emission intensity and efficiency are >3 orders of magnitude larger than 20 /spl Aring/ SiO/sub 2/ tunnel diode and 0.18 /spl mu/m MOSFET. Besides the small 3 V operation and low power consumption, good reliability is another merit for this device.
{"title":"Strong and efficient light emission in ITO/Al/sub 2/O/sub 3/ superlattice tunnel diode","authors":"A. Chin, C. Liang, C. Lin, C.C. Wu, J. Liu","doi":"10.1109/IEDM.2001.979459","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979459","url":null,"abstract":"We have studied the electroluminescence of ITO/Al/sub 2/O/sub 3/ superlattice tunnel diode on Si. The light emission intensity and efficiency are >3 orders of magnitude larger than 20 /spl Aring/ SiO/sub 2/ tunnel diode and 0.18 /spl mu/m MOSFET. Besides the small 3 V operation and low power consumption, good reliability is another merit for this device.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"13 1","pages":"8.3.1-8.3.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74413836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979439
R. Lake
The Nanoelectronic Engineering Modeling software (NEMO) has been used to model the quantum electron and hole transport and charge in a wide variety of material systems and semiconductor devices. This paper provides an overview of NEMO's current status, its applications, and its theoretical extensions.
{"title":"Full quantum simulation, design, and analysis of Si tunnel diodes, MOS leakage and capacitance, HEMTs, and RTDs","authors":"R. Lake","doi":"10.1109/IEDM.2001.979439","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979439","url":null,"abstract":"The Nanoelectronic Engineering Modeling software (NEMO) has been used to model the quantum electron and hole transport and charge in a wide variety of material systems and semiconductor devices. This paper provides an overview of NEMO's current status, its applications, and its theoretical extensions.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"33 1","pages":"5.5.1-5.5.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75764844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979662
E. Hynes, P. Elebert, D. McAuliffe, D. Doyle, M. O’Neill, W. Lane, H. Berney, M. Hill, A. Mathewson
A new MEMS sensor architecture is presented that converts mechanical displacement of a conductive diaphragm directly to a current. The electrical bias on the mechanical element is capacitively coupled to an electrically floating MOS gate that controls the sensor output current. The sensor is manufactured using a process module that slots directly in to a CMOS process. Both the sensor architecture and process module will scale with shrinking CMOS generations. Injection of charge onto the floating gate can be used to program the sensor threshold voltage. The sensor architecture has been demonstrated as a pressure sensor on a CMOS process.
{"title":"The CAP-FET, a scaleable MEMS sensor technology on CMOS with programmable floating gate","authors":"E. Hynes, P. Elebert, D. McAuliffe, D. Doyle, M. O’Neill, W. Lane, H. Berney, M. Hill, A. Mathewson","doi":"10.1109/IEDM.2001.979662","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979662","url":null,"abstract":"A new MEMS sensor architecture is presented that converts mechanical displacement of a conductive diaphragm directly to a current. The electrical bias on the mechanical element is capacitively coupled to an electrically floating MOS gate that controls the sensor output current. The sensor is manufactured using a process module that slots directly in to a CMOS process. Both the sensor architecture and process module will scale with shrinking CMOS generations. Injection of charge onto the floating gate can be used to program the sensor threshold voltage. The sensor architecture has been demonstrated as a pressure sensor on a CMOS process.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"45 1","pages":"41.3.1-41.3.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79002612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979611
Y.M. Park, J. Lee, M. Kim, M.K. Choi, K. Kim, J.I. Han, D. Kwon, W. Lee, Y. Song, K. Suh
The mechanical stress of silicon nitride and silicon oxynitride, used as gate transistor sidewall or passivation layers in NOR flash memory cells, on data retention characteristics is investigated. The stress is studied by simulation based on experimental data. As the mechanical stress on the floating gate increases, the Vth shift of the programmed cell after bake increases. It is explained by the trap assisted tunneling model. Such stress has a severe impact on data retention when using silicon nitride as the gate sidewall layer and increasing the thickness of it. It is certified that the effect of the passivation layer on data retention is due to the hydrogen concentration in the layer rather than mechanical stress.
{"title":"The mechanical stress effects on data retention reliability of NOR flash memory","authors":"Y.M. Park, J. Lee, M. Kim, M.K. Choi, K. Kim, J.I. Han, D. Kwon, W. Lee, Y. Song, K. Suh","doi":"10.1109/IEDM.2001.979611","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979611","url":null,"abstract":"The mechanical stress of silicon nitride and silicon oxynitride, used as gate transistor sidewall or passivation layers in NOR flash memory cells, on data retention characteristics is investigated. The stress is studied by simulation based on experimental data. As the mechanical stress on the floating gate increases, the Vth shift of the programmed cell after bake increases. It is explained by the trap assisted tunneling model. Such stress has a severe impact on data retention when using silicon nitride as the gate sidewall layer and increasing the thickness of it. It is certified that the effect of the passivation layer on data retention is due to the hydrogen concentration in the layer rather than mechanical stress.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"38 1","pages":"32.4.1-32.4.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79055556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979641
B. Tavel, T. Skotnicki, G. Pares, N. Carriere, M. Rivoire, F. Leverd, C. Julien, J. Torres, R. Pantel
In this paper we present for the first time mid-gap CoSi/sub 2/ metal gates obtained by total gate silicidation meaning that the silicidation process decay itself once the reaction front arrives down to the gate oxide and no more polysilicon is left. Metal gate are required for FDSOI but they may also be useful for low gate-resistance bulk RF devices. For simplicity, we have investigated totally silicided gates within a 0.1 /spl mu/m CMOS bulk technology. In the next step, CoSi/sub 2/ metal gates were processed after the poly CMP step (first CMP in damascene process) in order to protect source and drain from deep silicidation. Low gate resistivity transistors were obtained, exhibiting good performances without degradation in gate leakage, subthreshold slope nor in drive and off currents compared with reference poly-silicon gate transistors.
{"title":"Totally silicided (CoSi/sub 2/) polysilicon: a novel approach to very low-resistive gate (/spl sim/2/spl Omega///spl square/) without metal CMP nor etching","authors":"B. Tavel, T. Skotnicki, G. Pares, N. Carriere, M. Rivoire, F. Leverd, C. Julien, J. Torres, R. Pantel","doi":"10.1109/IEDM.2001.979641","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979641","url":null,"abstract":"In this paper we present for the first time mid-gap CoSi/sub 2/ metal gates obtained by total gate silicidation meaning that the silicidation process decay itself once the reaction front arrives down to the gate oxide and no more polysilicon is left. Metal gate are required for FDSOI but they may also be useful for low gate-resistance bulk RF devices. For simplicity, we have investigated totally silicided gates within a 0.1 /spl mu/m CMOS bulk technology. In the next step, CoSi/sub 2/ metal gates were processed after the poly CMP step (first CMP in damascene process) in order to protect source and drain from deep silicidation. Low gate resistivity transistors were obtained, exhibiting good performances without degradation in gate leakage, subthreshold slope nor in drive and off currents compared with reference poly-silicon gate transistors.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"119 1","pages":"37.5.1-37.5.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80321245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979435
Z. Ren, R. Venugopal, S. Datta, M. Lundstrom
The double gate (DG) MOSFET and similar structures provide the electrostatic integrity needed to scale devices to their limits. In this paper, we use a non-equilibrium Green's function (NEGF) approach to examine 10 nm-scale device design and manufacturing issues realistically. NEGF simulations are used to examine: (i) choice of body thickness, (ii) effect of body thickness variations, (iii) the required junction abruptness, (iv) sensitivity of the device to gate-S/D (source/drain) over/underlap, and (v) the impact of metal-semiconductor contact resistance. The results of this study identify key device challenges for 10 nm-scale MOSFETs.
{"title":"Examination of design and manufacturing issues in a 10 nm double gate MOSFET using nonequilibrium Green's function simulation","authors":"Z. Ren, R. Venugopal, S. Datta, M. Lundstrom","doi":"10.1109/IEDM.2001.979435","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979435","url":null,"abstract":"The double gate (DG) MOSFET and similar structures provide the electrostatic integrity needed to scale devices to their limits. In this paper, we use a non-equilibrium Green's function (NEGF) approach to examine 10 nm-scale device design and manufacturing issues realistically. NEGF simulations are used to examine: (i) choice of body thickness, (ii) effect of body thickness variations, (iii) the required junction abruptness, (iv) sensitivity of the device to gate-S/D (source/drain) over/underlap, and (v) the impact of metal-semiconductor contact resistance. The results of this study identify key device challenges for 10 nm-scale MOSFETs.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"30 9 1","pages":"5.4.1-5.4.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73729462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979652
B. Min, O. Zia, M. Celik, R. Widenhofer, L. Kang, S. Song, S. Gonzales, A. Mendicino
We have investigated hot carrier stress degradation for short channel (100 nm and 80 nm) nMOSFETs with ultra-thin gate oxides (2.5 nm). Under high drain bias, gate current was measured well above that is expected from direct tunneling itself We have found that this hot carrier enhanced gate current mechanism plays a significant role in the degradation of nMOSFETs. The degradation under very accelerated stress bias, where hot carrier enhanced gate current is dominant, was relatively insensitive to stress bias and time, compared to the degradation under low voltage hot carrier stress. Unless properly considered, the additional mechanism can cause the extrapolated lifetime to be overestimated.
{"title":"Hot carrier enhanced gate current and its impact on short channel nMOSFET reliability with ultra-thin gate oxides","authors":"B. Min, O. Zia, M. Celik, R. Widenhofer, L. Kang, S. Song, S. Gonzales, A. Mendicino","doi":"10.1109/IEDM.2001.979652","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979652","url":null,"abstract":"We have investigated hot carrier stress degradation for short channel (100 nm and 80 nm) nMOSFETs with ultra-thin gate oxides (2.5 nm). Under high drain bias, gate current was measured well above that is expected from direct tunneling itself We have found that this hot carrier enhanced gate current mechanism plays a significant role in the degradation of nMOSFETs. The degradation under very accelerated stress bias, where hot carrier enhanced gate current is dominant, was relatively insensitive to stress bias and time, compared to the degradation under low voltage hot carrier stress. Unless properly considered, the additional mechanism can cause the extrapolated lifetime to be overestimated.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"106 1","pages":"39.5.1-39.5.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76228519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979450
A. Nakajima, Q. Khosru, T. Yoshirnoto, T. Kidera, S. Yokoyama
An extremely-thin (0.3-0.4 nm) silicon nitride layer has been deposited on thermally grown SiO/sub 2/ by an atomic-layer-deposition (ALD) technique. The boron penetration through the stack gate dielectrics has been dramatically suppressed and the reliability has been significantly improved. An exciting feature of no soft breakdown (SBD) events is observed in ramped voltage stressing and time-dependent dielectric breakdown (TDDB) characteristics. A model has been proposed, which consistently explains the no-SBD phenomena in ALD-silicon-nitride/SiO/sub 2/ stack gate dielectrics as well as the SBD events in conventional SiO/sub 2/ dielectrics.
{"title":"Soft breakdown free atomic-layer-deposited silicon-nitride/SiO/sub 2/ stack gate dielectrics","authors":"A. Nakajima, Q. Khosru, T. Yoshirnoto, T. Kidera, S. Yokoyama","doi":"10.1109/IEDM.2001.979450","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979450","url":null,"abstract":"An extremely-thin (0.3-0.4 nm) silicon nitride layer has been deposited on thermally grown SiO/sub 2/ by an atomic-layer-deposition (ALD) technique. The boron penetration through the stack gate dielectrics has been dramatically suppressed and the reliability has been significantly improved. An exciting feature of no soft breakdown (SBD) events is observed in ramped voltage stressing and time-dependent dielectric breakdown (TDDB) characteristics. A model has been proposed, which consistently explains the no-SBD phenomena in ALD-silicon-nitride/SiO/sub 2/ stack gate dielectrics as well as the SBD events in conventional SiO/sub 2/ dielectrics.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"5 1","pages":"6.5.1-6.5.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75960658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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