Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979632
J. Yi, W.S. Kim, S. Song, Y. Khang, H. Kim, J.H. Choi, H. Lim, N. Lee, K. Fujihara, H. Kang, J. Moon, M.Y. Lee
A novel memory device called Scalable Two-Transistor Memory (STTM) has been developed. STTM is a floating gate device with the writing mechanism of direct tunneling through the multiple tunnel junction (MTJ). STTM has potential advantages of scalability, high density, high speed, long data retention, low voltage operation, low power consumption, and good endurability. We have fabricated and successfully demonstrated the memory cell operation of the STTM for the first time. The STTM unit cell fabricated using 0.16 /spl mu/m silicon processing showed the writing speed of /spl sim/100 ns and the data retention time of /spl sim/200 sec. with the operation voltages of -5/spl sim/5 V. Also, we developed a novel architecture for the high-density STTM cell array with an unit cell size of 4F/sup 2/ and a process scheme to fabricate it.
{"title":"Scalable Two-Transistor Memory (STTM)","authors":"J. Yi, W.S. Kim, S. Song, Y. Khang, H. Kim, J.H. Choi, H. Lim, N. Lee, K. Fujihara, H. Kang, J. Moon, M.Y. Lee","doi":"10.1109/IEDM.2001.979632","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979632","url":null,"abstract":"A novel memory device called Scalable Two-Transistor Memory (STTM) has been developed. STTM is a floating gate device with the writing mechanism of direct tunneling through the multiple tunnel junction (MTJ). STTM has potential advantages of scalability, high density, high speed, long data retention, low voltage operation, low power consumption, and good endurability. We have fabricated and successfully demonstrated the memory cell operation of the STTM for the first time. The STTM unit cell fabricated using 0.16 /spl mu/m silicon processing showed the writing speed of /spl sim/100 ns and the data retention time of /spl sim/200 sec. with the operation voltages of -5/spl sim/5 V. Also, we developed a novel architecture for the high-density STTM cell array with an unit cell size of 4F/sup 2/ and a process scheme to fabricate it.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"16 1","pages":"36.1.1-36.1.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75468993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979484
J. Koo, S. Hong, S. Yeom, J. Roh, Jiyoung Kim
We propose a novel CrTiN/TiN double barrier layer technology for high-density COB structure applications. After furnace annealing at 800/spl deg/C for 30min, a 0.35/spl mu/m poly-Si contact test structure with the Pt/CrTiN/TiN layer was found to maintain ohmic behaviors and provide a resistance of about 1k/spl Omega/. In addition, these contact structures successfully exhibited long time thermal stability at 750/spl deg/C. The findings of this study suggest that the CrTiN/TiN double barrier layer method is suitable for the COB structure in order to realize high-density ferroelectric memory applications.
{"title":"High thermal stability of poly-Si nodes with novel CrTiN/TiN double barrier layers for high-density ferroelectric memory applications","authors":"J. Koo, S. Hong, S. Yeom, J. Roh, Jiyoung Kim","doi":"10.1109/IEDM.2001.979484","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979484","url":null,"abstract":"We propose a novel CrTiN/TiN double barrier layer technology for high-density COB structure applications. After furnace annealing at 800/spl deg/C for 30min, a 0.35/spl mu/m poly-Si contact test structure with the Pt/CrTiN/TiN layer was found to maintain ohmic behaviors and provide a resistance of about 1k/spl Omega/. In addition, these contact structures successfully exhibited long time thermal stability at 750/spl deg/C. The findings of this study suggest that the CrTiN/TiN double barrier layer method is suitable for the COB structure in order to realize high-density ferroelectric memory applications.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"10 3 1","pages":"12.5.1-12.5.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75513241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979525
R. Weis, K. Hummler, H. Akatsu, S. Kudelka, T. Dyer, M. Seitz, A. Scholz, B. Kim, M. Wise, R. Malik, J. Strane, T. Goebel, K. McStay, J. Beintner, N. Arnold, R. Gerber, B. Liegl, A. Knorr, L. Economikos, A. Simpson, W. Yan, D. Dobuzinsky, J. Mandelman, L. Nesbit, C. Radens, R. Divakaruni, W. Bergner, G. Bronner, W. Mueller
This paper describes a highly cost efficient 8F/sup 2/ trench capacitor DRAM cell with a lithography-friendly layout. It consists of only 4 critical masks, i.e. a highly regular trench pattern and three line masks. The cell is shrinkable below 100 nm. It is fabricated with an overlay robust process with a double gate vertical pass transistor in the upper part of the trench capacitor and a double buried strap node contact. The cell features four bitline contacts per cell (two shared with the neighboring cells). Lines of deep oxide isolation trenches provide efficient decoupling of adjacent cells. Feasibility has been demonstrated at a 175 nm design rule with a 128 Mb product chip and a 1 Mb test array at 120 nm.
{"title":"A highly cost efficient 8F/sup 2/ DRAM cell with a double gate vertical transistor device for 100 nm and beyond","authors":"R. Weis, K. Hummler, H. Akatsu, S. Kudelka, T. Dyer, M. Seitz, A. Scholz, B. Kim, M. Wise, R. Malik, J. Strane, T. Goebel, K. McStay, J. Beintner, N. Arnold, R. Gerber, B. Liegl, A. Knorr, L. Economikos, A. Simpson, W. Yan, D. Dobuzinsky, J. Mandelman, L. Nesbit, C. Radens, R. Divakaruni, W. Bergner, G. Bronner, W. Mueller","doi":"10.1109/IEDM.2001.979525","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979525","url":null,"abstract":"This paper describes a highly cost efficient 8F/sup 2/ trench capacitor DRAM cell with a lithography-friendly layout. It consists of only 4 critical masks, i.e. a highly regular trench pattern and three line masks. The cell is shrinkable below 100 nm. It is fabricated with an overlay robust process with a double gate vertical pass transistor in the upper part of the trench capacitor and a double buried strap node contact. The cell features four bitline contacts per cell (two shared with the neighboring cells). Lines of deep oxide isolation trenches provide efficient decoupling of adjacent cells. Feasibility has been demonstrated at a 175 nm design rule with a 128 Mb product chip and a 1 Mb test array at 120 nm.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"1 1","pages":"18.7.1-18.7.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78512925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979655
C. Kim, Joung-Woo Park, Hyun-Kyu Yu
New trenched sinker LDMOSFET structure is proposed for the application of high power RF amplifier. By adopting low temperature deep trench technology, the sinker area can be shrunk down more than 70% compared with the conventional diffusion type. The RF performance of proposed device with channel width of 5 mm showed a small signal gain of 19.3 dB at 2 GHz and 14.8 dB at 3 GHz, and maximum peak power of 30 dBm at V/sub DD/ of 26 V. Furthermore, the trench sinker (or guard), that is applied to suppress the coupling between inductors, also showed a excellent blocking performance at frequency range from 0.5 GHz to 20 GHz.
{"title":"Trenched sinker LDMOSFET (TS-LDMOS) structure for high power amplifier application above 2 GHz","authors":"C. Kim, Joung-Woo Park, Hyun-Kyu Yu","doi":"10.1109/IEDM.2001.979655","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979655","url":null,"abstract":"New trenched sinker LDMOSFET structure is proposed for the application of high power RF amplifier. By adopting low temperature deep trench technology, the sinker area can be shrunk down more than 70% compared with the conventional diffusion type. The RF performance of proposed device with channel width of 5 mm showed a small signal gain of 19.3 dB at 2 GHz and 14.8 dB at 3 GHz, and maximum peak power of 30 dBm at V/sub DD/ of 26 V. Furthermore, the trench sinker (or guard), that is applied to suppress the coupling between inductors, also showed a excellent blocking performance at frequency range from 0.5 GHz to 20 GHz.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"25 1","pages":"40.2.1-40.2.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74760021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979578
C. Chen, T. Lin, J. Jung, N. Yabuoshi, Y. Sasaki, K. Komori, H. Shih, Chao Min Liao, M. Funabashi, N. Suzuki, Y. Ishii, T. Uchino, K. Nemoto, H. Yamamoto, S. Nishihara, S. Sasabe, A. Koike, S. Ikeda, J. Tsao
In this paper, we discuss a new technology implemented with all single wafer process for 300 mm fab. Very aggressive cycle time reduction with high yield has been demonstrated (one-third cycle time of that of conventional fab) in single polysilicon triple metal 8M/4M low power SRAM. High performance devices with excellent reliability are also achieved.
{"title":"Innovation of 300 mm fab manufacturing with single wafer technology","authors":"C. Chen, T. Lin, J. Jung, N. Yabuoshi, Y. Sasaki, K. Komori, H. Shih, Chao Min Liao, M. Funabashi, N. Suzuki, Y. Ishii, T. Uchino, K. Nemoto, H. Yamamoto, S. Nishihara, S. Sasabe, A. Koike, S. Ikeda, J. Tsao","doi":"10.1109/IEDM.2001.979578","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979578","url":null,"abstract":"In this paper, we discuss a new technology implemented with all single wafer process for 300 mm fab. Very aggressive cycle time reduction with high yield has been demonstrated (one-third cycle time of that of conventional fab) in single polysilicon triple metal 8M/4M low power SRAM. High performance devices with excellent reliability are also achieved.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"52 1","pages":"28.3.1-28.3.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73816689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979511
K. Misiakos, S. Kakabakos, A. Douvas, P. Argitis
This work presents results on protein detection through a monolithically integrated silicon optoelectronic transducer. Also, we demonstrate the enabling technologies for developing high probe density optical biochips that can be read out without the need of external optical components. Experimental results are presented that demonstrate sensitive protein detection using biotin and protein coated chips as well as probe patterning using biocompatible photoresist.
{"title":"Monolithic silicon optoelectronic biochips","authors":"K. Misiakos, S. Kakabakos, A. Douvas, P. Argitis","doi":"10.1109/IEDM.2001.979511","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979511","url":null,"abstract":"This work presents results on protein detection through a monolithically integrated silicon optoelectronic transducer. Also, we demonstrate the enabling technologies for developing high probe density optical biochips that can be read out without the need of external optical components. Experimental results are presented that demonstrate sensitive protein detection using biotin and protein coated chips as well as probe patterning using biocompatible photoresist.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"25 1","pages":"16.2.1-16.2.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84757579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979618
H. Majima, Y. Saito, T. Hiramoto
The impact of quantum mechanical effects and device design guidelines in nano-scale narrow channel n-type and p-type MOSFETs is presented. Ultra-narrow channel MOSFETs with n- and p-type source/drain have been successfully fabricated and threshold voltage increase due to quantum confinement has been clearly observed in both n- and p-type devices. By analytical calculations, device design for threshold voltage adjustment in n- and p-type MOSFETs using quantum mechanical effects is discussed. The calculations also demonstrate that an ultra-narrow channel along the <100> direction has a large advantage in device design over the <110> direction due to higher mobility.
{"title":"Impact of quantum mechanical effects on design of nano-scale narrow channel n- and p-type MOSFETs","authors":"H. Majima, Y. Saito, T. Hiramoto","doi":"10.1109/IEDM.2001.979618","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979618","url":null,"abstract":"The impact of quantum mechanical effects and device design guidelines in nano-scale narrow channel n-type and p-type MOSFETs is presented. Ultra-narrow channel MOSFETs with n- and p-type source/drain have been successfully fabricated and threshold voltage increase due to quantum confinement has been clearly observed in both n- and p-type devices. By analytical calculations, device design for threshold voltage adjustment in n- and p-type MOSFETs using quantum mechanical effects is discussed. The calculations also demonstrate that an ultra-narrow channel along the <100> direction has a large advantage in device design over the <110> direction due to higher mobility.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"43 1","pages":"33.3.1-33.3.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85527961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979552
J.B. Johnson, A. Stricker, A. Joseph, J. Slinkman
A methodology for simultaneous calibration of SiGe HBT process and device simulation is presented and applied to SiGe BiCMOS HBTs with peak cut-off frequencies ranging from 100 GHz to 200 GHz. Predictive simulation capability is demonstrated for critical HBT AC device characteristics through comparison with experimental devices.
{"title":"A technology simulation methodology for AC-performance optimization of SiGe HBTs","authors":"J.B. Johnson, A. Stricker, A. Joseph, J. Slinkman","doi":"10.1109/IEDM.2001.979552","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979552","url":null,"abstract":"A methodology for simultaneous calibration of SiGe HBT process and device simulation is presented and applied to SiGe BiCMOS HBTs with peak cut-off frequencies ranging from 100 GHz to 200 GHz. Predictive simulation capability is demonstrated for critical HBT AC device characteristics through comparison with experimental devices.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"261 1","pages":"21.4.1-21.4.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79657013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979482
J. Goo, Eunkee Hong, Hong-Gun Kim, Hyun Joo Kim, Eun Kyung Baek, Sun-hoo Park, Jubum Lee, Hyeon-deok Lee, Ho-Kyu Kang, J. Moon
New PMD (Pre-Metal Dielectric) process by employing polysilazane based inorganic SOG (spin-on-glass) is suggested for future VLSI devices. Compared with conventional SOG materials, the film made from new SOG has higher wet etch resistance, which is critical in achieving deformation-free contact profile. Additional advantages of using this new SOG process are excellent gap-fill capability upto an aspect ratio (A/R) of 20 and lower thermal budget than BPSG reflow process. Neither detrimental effect of new SOG PMD process on electrical characteristics nor device performance such as refresh characteristic, compared to HDPCVD SiO/sub 2/ was observed, indicating this is a PMD process of choice for the future devices.
{"title":"A highly manufacturable, low-thermal budget, void and seam free pre-metal-dielectric process using new SOG for beyond 60nm DRAM and other devices","authors":"J. Goo, Eunkee Hong, Hong-Gun Kim, Hyun Joo Kim, Eun Kyung Baek, Sun-hoo Park, Jubum Lee, Hyeon-deok Lee, Ho-Kyu Kang, J. Moon","doi":"10.1109/IEDM.2001.979482","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979482","url":null,"abstract":"New PMD (Pre-Metal Dielectric) process by employing polysilazane based inorganic SOG (spin-on-glass) is suggested for future VLSI devices. Compared with conventional SOG materials, the film made from new SOG has higher wet etch resistance, which is critical in achieving deformation-free contact profile. Additional advantages of using this new SOG process are excellent gap-fill capability upto an aspect ratio (A/R) of 20 and lower thermal budget than BPSG reflow process. Neither detrimental effect of new SOG PMD process on electrical characteristics nor device performance such as refresh characteristic, compared to HDPCVD SiO/sub 2/ was observed, indicating this is a PMD process of choice for the future devices.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"204 1","pages":"12.3.1-12.3.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80324856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-12-02DOI: 10.1109/IEDM.2001.979638
M. Togo, K. Watanabe, M. Terai, T. Fukai, M. Narihiro, K. Arai, S. Koyama, N. Ikezawa, T. Tatsumi, T. Mogami
We have demonstrated that oxynitridation using radical-O and -N improves reverse narrow channel effects (RNCE) and reliability in a sub-1.5 nm-thick gate-SiO/sub 2/ FETs with narrow channel and shallow-trench isolation (STI), which is suitable for high-density SRAM and logic devices. The STI structure needs a uniform gate-dielectric on the Si surface with various orientations. Oxidation using radical-O forms the uniform SiO/sub 2/ on the Si<100> and Si<111> surfaces and suppresses RNCE in a sub-1.5 nm-thick gate-SiO/sub 2/ FET with STI. Nitrifying the SiO/sub 2/ using radical-N increases the physical thickness while maintaining the oxide equivalent thickness on the Si<111> surface as well as the Si<100> one and, thus, producing a low-leakage and highly reliable sub-1.5 nm-thick gate-SiON.
{"title":"Impact of radical oxynitridation on characteristics and reliability of sub-1.5 nm-thick gate-dielectric FETs with narrow channel and shallow-trench isolation","authors":"M. Togo, K. Watanabe, M. Terai, T. Fukai, M. Narihiro, K. Arai, S. Koyama, N. Ikezawa, T. Tatsumi, T. Mogami","doi":"10.1109/IEDM.2001.979638","DOIUrl":"https://doi.org/10.1109/IEDM.2001.979638","url":null,"abstract":"We have demonstrated that oxynitridation using radical-O and -N improves reverse narrow channel effects (RNCE) and reliability in a sub-1.5 nm-thick gate-SiO/sub 2/ FETs with narrow channel and shallow-trench isolation (STI), which is suitable for high-density SRAM and logic devices. The STI structure needs a uniform gate-dielectric on the Si surface with various orientations. Oxidation using radical-O forms the uniform SiO/sub 2/ on the Si<100> and Si<111> surfaces and suppresses RNCE in a sub-1.5 nm-thick gate-SiO/sub 2/ FET with STI. Nitrifying the SiO/sub 2/ using radical-N increases the physical thickness while maintaining the oxide equivalent thickness on the Si<111> surface as well as the Si<100> one and, thus, producing a low-leakage and highly reliable sub-1.5 nm-thick gate-SiON.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"30 1","pages":"37.2.1-37.2.4"},"PeriodicalIF":0.0,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83411267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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