International Journal of Circuit Theory and Applications最新文献

This paper presents the analysis and design methodology of a second-order ΔΣ modulator analogous bang-bang digital phase-locked loop (DSBPLL). When the bang-bang-based digital PLL (BB-DPLL) cannot fully track the DCO jitter, the jitter slewing effect exacerbates the in-band noise. The proposed DSBPLL can increase the PLL filter order without using a high-order loop filter, thereby mitigating the in-band noise caused by input tracking jitter. Theoretical noise analysis confirmed that the proposed DSBPLL can reduce 54.3% of the integrated jitter from 100 kHz to 100 MHz, consistent with the measurement results.

The classical direct torque control (DTC) of five-phase induction motors is a simple control technique and exhibits fast dynamics; however, it suffers from significant drawbacks like high flux ripple, torque ripple, current harmonic distortion, and variable switching frequencies. Several modified DTC control strategies have been proposed to address these issues by employing multiple lookup tables or multilevel hysteresis torque controllers, which increase the complexity of the system. In this paper, a novel approach is proposed that replaces the classical hysteresis torque and flux controllers with a triangular-carrier-based three-level constant switching torque (CST) controller and a two-level constant switching flux (CSF) controller. This approach, known as constant switching torque-flux controllers-based DTC (CSTF-DTC), significantly enhances the steady-state performance of the five-phase induction motor by mitigating flux ripple, torque ripple, and current harmonic distortion without compromising dynamic behavior and without altering the generality of the classical DTC method for simplicity. The proposed CSTF-DTC scheme also effectively eliminates harmonic plane components using virtual voltage vectors. Experimental results on a two-level inverter-fed five-phase induction motor validate the superior performance of the proposed method over existing DTC techniques for a wide range of operating conditions and dynamics.

This paper presents the design of a high-precision, low-voltage inverter-based comparator. The comparator employs current-limiting and current calibration circuits to reduce power consumption and improve precision by correcting the errors associated with the inaccurate reset operation of the comparator. An analytical model was developed to determine the optimum operating point for the voltage gain and the effects of reset operation on the characteristics of the comparator. The model was verified through simulations using the TSMC 0.18-$�\mu$ m N-well CMOS process and was used to develop current-mode calibration and power-reduction techniques to improve the gain of the comparator. The simulations showed an improvement in the gain by a factor of $�3�\times$ with minimal added power consumption. Monte Carlo and process corner simulations were performed to verify the effectiveness of the proposed calibration technique. A 5-bit flash and 12-bit SAR analog-to-digital converters (ADCs) were designed using the new comparator and calibration technique as a proof of concept to demonstrate the superiority of the calibration technique, which significantly improved the resolution of the ADC. Thus, it was concluded that the proposed current-limited current-calibrated (CLCC) inverter-based comparator can be used in high-precision, low-voltage data converters in applications where resolution and supply voltage are critical design considerations.

Traditional DC-DC converter topologies often encounter challenges such as low voltage gain, discontinuous input current, and the absence of a common ground (CG) between source and load terminals. Moreover, many of these topologies struggle to efficiently integrate power from multiple low-voltage sources, such as photovoltaic (PV), fuel cells, and battery storage, to supply high-voltage DC at a common DC bus terminal. To overcome these challenges, this paper introduces three different dual-input single-output (DISO) DC-DC converters, derived from the traditional Buck, Boost, and SEPIC topologies. After a comparative analysis, the Boost-based DISO converter is identified as the most favorable for practical applications. The proposed DISO step-up DC-DC converter, based on the conventional boost topology, is designed and analyzed for grid-tied applications, aiming to achieve high voltage gain from low-voltage PV sources. A key advantage of this converter is the establishment of a CG between the input and output ports, while maintaining a continuous input current characteristic at both input ports. The paper explores the different operating modes and performs a steady-state analysis under various input conditions. The output voltage expression of the DISO converter, incorporating both input sources, is derived through equivalent circuit analysis. Additionally, the paper discusses the voltage and peak current stresses on different devices and provides design equations for the passive components. A comprehensive performance comparison highlights the primary benefits of the proposed topology over existing DISO topologies. Simulation results, using the PSIM simulator, validate the converter's operational characteristics, and experimental results from a $�350$ W prototype converter affirm the accuracy of the analysis and demonstrate its practical performance.

The low-power magnetic coupling resonant wireless power transfer (MCRWPT) system, which is widely used in household appliances, experiences significant performance degradation over long transmission distances. To address this problem, a reconfigurable relay coil with a variable inductor is introduced to optimize the MCRWPT system, and a maximum power point tracking (MPPT) control strategy is used to enhance its real-time anti-offset performance. By adding a relay coil but not introducing the control strategy, the system's maximum transfer efficiency is enhanced from 14.95% to 58.04%, and the output power is increased from 0.3 to 8.57 W when a transmission distance is 300 mm (three times of the coil's radius) and the relay coil is located 155 mm away from the transmitting coil. When adding the reconfigurable relay coil and introducing the control strategy, the system's maximum transfer efficiency is enhanced to 61.65%, and the output power is increased to 11.34 W. The research results indicate that the proposed MCRWPT system and control strategy can effectively improve the system's transfer efficiency, output power, and anti-offset ability under different working situations. The designed MCRWPT system can promote industrial upgrading and transformation related to wireless power transmission technology.

In this paper, a low-complexity digital predistortion (DPD) technique is proposed to compensate for the joint nonlinear distortions, such as the nonlinearity of power amplifier (PA), I/Q imbalance, and the filter group delay in broadband satellite communication system links. The proposed DPD technique is based on a band-limited IQ-separated memory polynomial (BL-IQMP) model and a parallel lookup table (LUT) architecture. The proposed model separates the real and imaginary parts of the polynomial kernel to counteract the effect of I/Q imbalance. For band-limited systems, the modeling bandwidth is controlled by introducing a band-limit function. In addition, a smooth twins support vector regression (STSVR) method is used instead of the traditional least squares (LS) method in the parameter-solving process to increase the accuracy of the modeling. The proposed architecture utilizes parallel signal processing techniques to circumvent the hardware clock frequency limitation, concurrently employing the LUT method to minimize hardware resource consumption substantially. Subsequently, the DPD experiments are conducted with 625-MHz 16 and 32APSK signals on the traveling-wave tube amplifier (TWTA) in the Ka-band, respectively. The experimental findings demonstrate that the proposed predistortion scheme has the capacity to substantially reduce the EVM of the signals and circumvent the loss of lock of phase-locked loop (PLL). This provides an effective solution for the predistortion technique employed in the radio frequency (RF) front-end of satellite communication systems.

Common-ground switched-capacitor (CGSC) inverters show unique advantages in voltage boosting and eliminating leakage current due to the combination of switched-capacitor and common-ground structure. However, the existing CGSC inverters have a drawback in that the unbalanced AC output voltage waveform will lead to DC bias. To address this problem, a CGSC five-level inverter with low–DC bias characteristics is proposed in this article. The topology consists of a single–DC input voltage, 11 switches, two diodes, and three capacitors. The inherent circuit feature enables the hybrid modulation strategy to repeatedly charge the capacitors using the DC source, optimizing the voltage ripples. By further designing the capacitance to compensate for the asymmetry of the voltage ripple, the output DC bias can be effectively suppressed. This article details how the topology works and the hybrid modulation strategies, as well as capacitance analysis. In addition, a performance comparison analysis with other similar topologies highlights the advantages of the proposed topology to suppress DC bias and improve capacitor utilization. The simulation results show the suppression effect with the hybrid modulation strategy and ripple compensation. Finally, a 500-W experimental prototype was built to verify the feasibility of the proposed topology.

In on-road e-bike charging technology, traditional wireless charging systems often struggle to maintain controllable power output due to fluctuations in coupling coefficients and differences in battery types and electric bicycles (e-bikes) structures. To address these challenges, this article introduces a versatile wireless charging circuit incorporating variable inductor and capacitor arrays, complemented by a novel impedance-modulation control method. This wireless charger is designed to accommodate varying coupling coefficients and power requirements, enabling efficient battery charging for on-road e-bikes. First, the circuit parameters are customized by the impedance modulation requirements of the load, including the variation range of variable inductance and capacitance. Second, the complex interactions between variable inductor, capacitor arrays, coupling coefficients and output power are explored and mathematically modeled through analysis. Finally, a prototype with an output power of 50 W and maximum system efficiency of 86.78% is built to validate the proposed method. The experimental validation shows that the output power is almost constant when $�k$ is varied from 0.15 to 0.25.

Multiport DC-DC converters have the capability to provide the output power at different voltage levels simultaneously. In this paper, a novel boost-side interleaved switched boost (BSISB) multiport DC-DC converter is proposed. The boost-side interleaving (BSI) reduces the input current ripple and improves fault-tolerant capability at the load end, even after an open-circuit transistor failure. The switched-boost action topology uses time-multiplexing control of boost and buck switches for independently regulated voltage of both the output ports using reduced semiconductor device count. The state-space averaged (SSA) and small signal model (SSM) of the proposed converter is developed with circuit parasitic. The SSA and SSM are used for steady-state gain analysis and the controller design for the converter, respectively. A prototype is developed in the lab to test the proposed converter under constant-current constant-voltage (CC-CV) mode of charging of the battery and verify the derived analytical results.