Aiming at the rich bifurcation and chaotic characteristics in the inverter with proportion integral derivative (PID) controller, the discrete iterative model of such an inverter was derived based on the stroboscopic mapping theory; the nonlinear evolution and the cause of instability in this inverter are analyzed. It was observed that the low‐frequency oscillation following instability was due to the Hopf bifurcation, which will decrease the power supplied quality by the inverter. To address the potential issue of the system instability caused by nonlinear behaviors, an improved exponential time‐delay feedback control scheme was proposed. The controlled object's output current first subtracted its own delay a period of time to form a difference term, which was subsequently fed into an exponential link to make difference with the constant 1. The resulting value was then fed into a proportional link to obtain the control term, which was applied to the PID controlled inverter in a feedback manner. Moreover, the range of the feedback proportional coefficient was solved via the Jury criterion. Finally, the effectiveness of this scheme was verified through the comparative simulations, demonstrating that this scheme can not only increase the stability domain for each parameter by more than 50% in the PID controlled inverter but also stabilize the quasi‐periodic behavior due to the low scale oscillation caused by the Hopf bifurcation at the switching frequency.
{"title":"Bifurcation analysis and control in a DC–AC inverter with PID controller","authors":"Ronghua Wu, Xiaohong Zhang, Wei Jiang","doi":"10.1002/cta.4209","DOIUrl":"https://doi.org/10.1002/cta.4209","url":null,"abstract":"Aiming at the rich bifurcation and chaotic characteristics in the inverter with proportion integral derivative (PID) controller, the discrete iterative model of such an inverter was derived based on the stroboscopic mapping theory; the nonlinear evolution and the cause of instability in this inverter are analyzed. It was observed that the low‐frequency oscillation following instability was due to the Hopf bifurcation, which will decrease the power supplied quality by the inverter. To address the potential issue of the system instability caused by nonlinear behaviors, an improved exponential time‐delay feedback control scheme was proposed. The controlled object's output current first subtracted its own delay a period of time to form a difference term, which was subsequently fed into an exponential link to make difference with the constant 1. The resulting value was then fed into a proportional link to obtain the control term, which was applied to the PID controlled inverter in a feedback manner. Moreover, the range of the feedback proportional coefficient was solved via the Jury criterion. Finally, the effectiveness of this scheme was verified through the comparative simulations, demonstrating that this scheme can not only increase the stability domain for each parameter by more than 50<jats:italic>%</jats:italic> in the PID controlled inverter but also stabilize the quasi‐periodic behavior due to the low scale oscillation caused by the Hopf bifurcation at the switching frequency.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"10 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142223884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article comprehensively reviews and studies CMOS transformer tank voltage‐controlled oscillators (VCOs) designed to improve the frequency tuning range (FTR) and minimize phase noise (PN) across a broad frequency range, particularly for mm‐wave and fifth‐generation applications. The study focuses on enhancing the performance of the oscillators to meet the demanding requirements of these advanced applications. This study thoroughly investigates and compares various strategies to increase the FTR, minimize PN, and reduce power dissipation in transformer tank VCOs. The aim is to establish fundamental guidelines for implementing transformer‐based tank VCOs. The study comprehensively reviews and analyzes the overall architecture of transformer‐based tank VCOs, presenting a detailed examination of the methods employed to enhance VCO performance. Additionally, the study illustrates the impact of the coupling factor on the VCO's performance parameters, detailing and demonstrating the overall tank circuit quality factor (Q) and resonator coupling factor (κ). A thorough understanding of PN methodology and the limitations of FTR has led to the development of innovative architectures. These include transformer‐based capacitive feedback (FB) oscillators with resistively adjusted variable inductors, as well as class‐F and inverse class‐F VCOs. These novel architectures contribute significantly to the improvement of oscillator performance.
{"title":"Comprehensive review and study for the CMOS transformer tank voltage‐controlled oscillator","authors":"Marwa Mansour, Islam Mansour","doi":"10.1002/cta.4214","DOIUrl":"https://doi.org/10.1002/cta.4214","url":null,"abstract":"This article comprehensively reviews and studies CMOS transformer tank voltage‐controlled oscillators (VCOs) designed to improve the frequency tuning range (FTR) and minimize phase noise (PN) across a broad frequency range, particularly for mm‐wave and fifth‐generation applications. The study focuses on enhancing the performance of the oscillators to meet the demanding requirements of these advanced applications. This study thoroughly investigates and compares various strategies to increase the FTR, minimize PN, and reduce power dissipation in transformer tank VCOs. The aim is to establish fundamental guidelines for implementing transformer‐based tank VCOs. The study comprehensively reviews and analyzes the overall architecture of transformer‐based tank VCOs, presenting a detailed examination of the methods employed to enhance VCO performance. Additionally, the study illustrates the impact of the coupling factor on the VCO's performance parameters, detailing and demonstrating the overall tank circuit quality factor (<jats:italic>Q</jats:italic>) and resonator coupling factor (<jats:italic>κ</jats:italic>). A thorough understanding of PN methodology and the limitations of FTR has led to the development of innovative architectures. These include transformer‐based capacitive feedback (FB) oscillators with resistively adjusted variable inductors, as well as class‐F and inverse class‐F VCOs. These novel architectures contribute significantly to the improvement of oscillator performance.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"59 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141941817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The three‐level Vienna rectifier is widely used in industrial applications, such as electric vehicle charging systems and telecommunication power systems. Discontinuous pulse width modulation (DPWM) is widely used in three‐level AC/DC converters due to its features of switching loss minimization. However, the problems of neutral‐point voltage ripple, current zero‐crossing distortion, and switching losses are mutually coupled for the Vienna rectifier. To address these issues, a hybrid carrier‐based discontinuous pulse width modulation (HCB‐DPWM) with reduced neutral‐point (NP) voltage ripple and current distortion is proposed. First, the /6 clamping period of the conventional DPWM is divided into three‐type clamping intervals, which reduce NP voltage ripple with shortened clamping period. Then, the elimination of current distortion around the current zero‐crossing point and the switching loss reduction are investigated. The implementation of the proposed HCB‐DPWM is given in detail. Finally, the simulation and experimental results of the Vienna rectifier are presented to validate the performance that the proposed HCB‐DPWM can eliminate current zero‐crossing distortion and reduce neutral‐point voltage ripple with different modulation indices.
{"title":"A hybrid carrier‐based discontinuous PWM with neutral‐point voltage ripple and current distortion reduction for Vienna rectifier","authors":"Yushuo Pei, Yu Tang","doi":"10.1002/cta.4223","DOIUrl":"https://doi.org/10.1002/cta.4223","url":null,"abstract":"The three‐level Vienna rectifier is widely used in industrial applications, such as electric vehicle charging systems and telecommunication power systems. Discontinuous pulse width modulation (DPWM) is widely used in three‐level AC/DC converters due to its features of switching loss minimization. However, the problems of neutral‐point voltage ripple, current zero‐crossing distortion, and switching losses are mutually coupled for the Vienna rectifier. To address these issues, a hybrid carrier‐based discontinuous pulse width modulation (HCB‐DPWM) with reduced neutral‐point (NP) voltage ripple and current distortion is proposed. First, the /6 clamping period of the conventional DPWM is divided into three‐type clamping intervals, which reduce NP voltage ripple with shortened clamping period. Then, the elimination of current distortion around the current zero‐crossing point and the switching loss reduction are investigated. The implementation of the proposed HCB‐DPWM is given in detail. Finally, the simulation and experimental results of the Vienna rectifier are presented to validate the performance that the proposed HCB‐DPWM can eliminate current zero‐crossing distortion and reduce neutral‐point voltage ripple with different modulation indices.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"100 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141941816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SummaryDigital MemComputing machines (DMMs), which employ nonlinear dynamical systems with memory (time non‐locality), have proven to be a robust and scalable unconventional computing approach for solving a wide variety of combinatorial optimization problems. However, most of the research so far has focused on the numerical simulations of the equations of motion of DMMs. This inevitably subjects time to discretization, which brings its own (numerical) issues that would be otherwise absent in actual physical systems operating in continuous time. Although hardware realizations of DMMs have been previously suggested, their implementation would require materials and devices that are not so easy to integrate with traditional electronics. Addressing this, our study introduces a novel hardware design for DMMs, utilizing readily available electronic components. This approach not only significantly boosts computational speed compared to current models but also exhibits remarkable robustness against additive noise. Crucially, it circumvents the limitations imposed by numerical noise, ensuring enhanced stability and reliability during extended operations. This paves a new path for tackling increasingly complex problems, leveraging the inherent advantages of DMMs in a more practical and accessible framework.
{"title":"Implementation of digital MemComputing using standard electronic components","authors":"Yuan‐Hang Zhang, Massimiliano Di Ventra","doi":"10.1002/cta.4220","DOIUrl":"https://doi.org/10.1002/cta.4220","url":null,"abstract":"SummaryDigital MemComputing machines (DMMs), which employ nonlinear dynamical systems with memory (time non‐locality), have proven to be a robust and scalable unconventional computing approach for solving a wide variety of combinatorial optimization problems. However, most of the research so far has focused on the numerical simulations of the equations of motion of DMMs. This inevitably subjects time to discretization, which brings its own (numerical) issues that would be otherwise absent in actual physical systems operating in continuous time. Although hardware realizations of DMMs have been previously suggested, their implementation would require materials and devices that are not so easy to integrate with traditional electronics. Addressing this, our study introduces a novel hardware design for DMMs, utilizing readily available electronic components. This approach not only significantly boosts computational speed compared to current models but also exhibits remarkable robustness against additive noise. Crucially, it circumvents the limitations imposed by numerical noise, ensuring enhanced stability and reliability during extended operations. This paves a new path for tackling increasingly complex problems, leveraging the inherent advantages of DMMs in a more practical and accessible framework.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"79 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141941923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Faridul Hassan, Alok Kumar Dubey, Amritesh Kumar, Avadh Pati
SummaryGenerating a quadrature signal in a single‐phase system using a second‐order generalized integrator (SOGI) requires accurate frequency information. The standard SOGI phase‐locked loop (PLL) includes frequency feedback to the SOGI. However, during grid abnormalities such as voltage sag/swell and phase angle jumps, the SOGI‐PLL faces frequency disturbances that propagate to the phase detector (PD) and affects the quadrature signal generator (QSG). Furthermore, the SOGI‐PLL having two loops dependent on each other creates loop coupling phenomena; either a change in phase or frequency affects each other. SOGI‐PLL is tuning sensitive, as the SOGI block has a gain that needs to be adjusted, increases the complexity, and affects the performance of the system. There is a trade‐off between SOGI gain and PLL parameters that needs to be considered for adequate parameter design to provide accurate grid synchronization while maintaining the stability of the system. To attain better performance, researchers have proposed derivative‐based PLL (DPLL). The conventional DPLL faces challenges to noise and harmonics amplification. This paper presents an improved DPLL for single‐phase grid synchronization under adverse grid conditions. The improved derivative‐based PLL (IDPLL) comprises two improved derivative‐based quadrature signal generator (IDQSG) blocks to extract the phase‐error information for accurately estimating phase and frequency. The detailed mathematical modeling and bode plot for the IDQSG and IDPLL are presented. The proposed IDQSG eliminates the requirement of gain tuning, hence reducing complexity. Moreover, there is no interdependent loop in the IDPLL, which significantly improves the dynamic performance. A hardware setup is developed to evaluate the performance of the system in real‐time. The experimental results are obtained using an field programmable gate array (FPGA)‐based controller.
{"title":"An improved derivative‐based phase‐locked loop for single‐phase grid synchronization under abnormal grid conditions","authors":"Faridul Hassan, Alok Kumar Dubey, Amritesh Kumar, Avadh Pati","doi":"10.1002/cta.4211","DOIUrl":"https://doi.org/10.1002/cta.4211","url":null,"abstract":"SummaryGenerating a quadrature signal in a single‐phase system using a second‐order generalized integrator (SOGI) requires accurate frequency information. The standard SOGI phase‐locked loop (PLL) includes frequency feedback to the SOGI. However, during grid abnormalities such as voltage sag/swell and phase angle jumps, the SOGI‐PLL faces frequency disturbances that propagate to the phase detector (PD) and affects the quadrature signal generator (QSG). Furthermore, the SOGI‐PLL having two loops dependent on each other creates loop coupling phenomena; either a change in phase or frequency affects each other. SOGI‐PLL is tuning sensitive, as the SOGI block has a gain that needs to be adjusted, increases the complexity, and affects the performance of the system. There is a trade‐off between SOGI gain and PLL parameters that needs to be considered for adequate parameter design to provide accurate grid synchronization while maintaining the stability of the system. To attain better performance, researchers have proposed derivative‐based PLL (DPLL). The conventional DPLL faces challenges to noise and harmonics amplification. This paper presents an improved DPLL for single‐phase grid synchronization under adverse grid conditions. The improved derivative‐based PLL (IDPLL) comprises two improved derivative‐based quadrature signal generator (IDQSG) blocks to extract the phase‐error information for accurately estimating phase and frequency. The detailed mathematical modeling and bode plot for the IDQSG and IDPLL are presented. The proposed IDQSG eliminates the requirement of gain tuning, hence reducing complexity. Moreover, there is no interdependent loop in the IDPLL, which significantly improves the dynamic performance. A hardware setup is developed to evaluate the performance of the system in real‐time. The experimental results are obtained using an field programmable gate array (FPGA)‐based controller.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"12 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141941924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Guangfu Ning, Litao Du, Ben Dai, Mei Su, Wenjing Xiong, Jingtao Xu, Guo Xu
SummaryIn this paper, an asymmetric pulse frequency modulation (APFM) is applied to the full‐bridge series resonant converter with a secondary LC resonant tank. Different from the traditional PFM, the upper and lower switches have complementary gate drivers and the lower switches have constant on time of half‐resonant period in this paper. Thanks to the resonant tank moved to the secondary side with the adopted APFM, the maximum magnetic flux density Bm of a high‐frequency transformer (HFT) is only concerned with the fixed resonant frequency rather than the variable switching frequency. Hence, the switching frequency can be widely regulated, as well as the voltage gain. Furthermore, the circulating current flowing back to the input voltage source in the traditional LC series resonant converter can be eliminated by the APFM, leading to a low resonant current peak value. The operation principles and characteristics of the adopted method are analyzed in detail. Finally, a 500 W/70–120 V to 300 V/21–180 kHz prototype is built, and the experimental results verified the theoretical analysis well.
{"title":"Noncirculating current series resonant converter with pulse frequency modulation","authors":"Guangfu Ning, Litao Du, Ben Dai, Mei Su, Wenjing Xiong, Jingtao Xu, Guo Xu","doi":"10.1002/cta.4206","DOIUrl":"https://doi.org/10.1002/cta.4206","url":null,"abstract":"SummaryIn this paper, an asymmetric pulse frequency modulation (APFM) is applied to the full‐bridge series resonant converter with a secondary LC resonant tank. Different from the traditional PFM, the upper and lower switches have complementary gate drivers and the lower switches have constant on time of half‐resonant period in this paper. Thanks to the resonant tank moved to the secondary side with the adopted APFM, the maximum magnetic flux density <jats:italic>B</jats:italic><jats:sub><jats:italic>m</jats:italic></jats:sub> of a high‐frequency transformer (HFT) is only concerned with the fixed resonant frequency rather than the variable switching frequency. Hence, the switching frequency can be widely regulated, as well as the voltage gain. Furthermore, the circulating current flowing back to the input voltage source in the traditional LC series resonant converter can be eliminated by the APFM, leading to a low resonant current peak value. The operation principles and characteristics of the adopted method are analyzed in detail. Finally, a 500 W/70–120 V to 300 V/21–180 kHz prototype is built, and the experimental results verified the theoretical analysis well.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"15 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141941929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new multiport DC–AC converter is proposed for standalone and off‐grid tied applications. The configuration converts power from DC to AC form in a single stage with suitable voltage gain. To increase the certainty of supporting power, the converter is designed to operate in four modes, including battery‐alone mode. The other advantage of the presented work is supplying the output power during unbalanced voltage conditions of the input ports. The advanced features of the converter for being used in standalone applications are related to the suitable placement and structure of the bidirectional port. In addition, the configuration is designed in a way to contain appropriate structural properties such as the existence of a common ground between the DC section and inverter, continuity of input currents, configured by an acceptable number of components, and low‐voltage stress on the DC–DC section's switches. Furthermore, it has an impedance network to protect the inverter's switches in a shoot‐through state. To confirm the converter advantages from the mentioned points of view, it has been compared with similar configurations. A prototype rated at 110 V is prepared to demonstrate the advantages of the converter performance per different conditions. The results of the steady‐state and transient experiments validate the suitability of the presented converter.
针对独立和离网并网应用，提出了一种新型多端口直流-交流转换器。该配置通过单级适当的电压增益将直流电转换为交流电。为了提高支持功率的确定性，该转换器设计为四种工作模式，包括电池独立模式。这项工作的另一个优势是在输入端口电压不平衡的情况下提供输出功率。该转换器可用于独立应用的先进功能与双向端口的适当位置和结构有关。此外，该配置的设计还包含适当的结构特性，如直流部分和逆变器之间的公共接地、输入电流的连续性、可接受的元件配置数量以及直流-直流部分开关的低压应力。此外，它还有一个阻抗网络，可在击穿状态下保护逆变器开关。为了从上述角度证实变流器的优势，我们将其与类似的配置进行了比较。我们制作了一个额定电压为 110 V 的原型，以展示变流器在不同条件下的性能优势。稳态和瞬态实验结果验证了该转换器的适用性。
{"title":"Single‐stage single‐phase multiport DC–AC inverter suitable for standalone applications due to its notable performance in different operation modes","authors":"Sina Ahmadian, Vahid Abbasi, Siroos Hemmati","doi":"10.1002/cta.4201","DOIUrl":"https://doi.org/10.1002/cta.4201","url":null,"abstract":"A new multiport DC–AC converter is proposed for standalone and off‐grid tied applications. The configuration converts power from DC to AC form in a single stage with suitable voltage gain. To increase the certainty of supporting power, the converter is designed to operate in four modes, including battery‐alone mode. The other advantage of the presented work is supplying the output power during unbalanced voltage conditions of the input ports. The advanced features of the converter for being used in standalone applications are related to the suitable placement and structure of the bidirectional port. In addition, the configuration is designed in a way to contain appropriate structural properties such as the existence of a common ground between the DC section and inverter, continuity of input currents, configured by an acceptable number of components, and low‐voltage stress on the DC–DC section's switches. Furthermore, it has an impedance network to protect the inverter's switches in a shoot‐through state. To confirm the converter advantages from the mentioned points of view, it has been compared with similar configurations. A prototype rated at 110 V is prepared to demonstrate the advantages of the converter performance per different conditions. The results of the steady‐state and transient experiments validate the suitability of the presented converter.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"141 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141969196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a novel compact and shadow resistance-to-frequency converter and resistance-to-time converter. The design incorporates three current feedback operational amplifiers (CFOA) and can be implemented in CMOS technology. The design's functionality has been proven through simulation and experimental verification. The simulation and experimental findings show that the proposed design works well with small deviation between simulation and experimental results.
{"title":"A novel compact and shadow resistance-to-frequency and resistance-to-time converter","authors":"Muneer A. Al-Absi, Abdulaziz Alkhulaifi","doi":"10.1002/cta.4225","DOIUrl":"10.1002/cta.4225","url":null,"abstract":"<p>This paper presents a novel compact and shadow resistance-to-frequency converter and resistance-to-time converter. The design incorporates three current feedback operational amplifiers (CFOA) and can be implemented in CMOS technology. The design's functionality has been proven through simulation and experimental verification. The simulation and experimental findings show that the proposed design works well with small deviation between simulation and experimental results.</p>","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"53 2","pages":"1151-1158"},"PeriodicalIF":1.8,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141941927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the paper, a high‐selectivity wideband four‐way filtering power divider with input absorptive feature is presented. It consists of two parallel‐coupled lines (CLs), two three‐coupled lines (TCLs), two open‐ended stepped branches, one absorptive branch, and two isolation resistors. The wideband filtering response is achieved by cascading the TCLs and CLs. While high selectivity is obtained by loading the open‐ended stepped branch, where two extra transmission zeros are generated. In addition, wide absorptive bandwidth with good isolations between adjacent output ports are realized by combining the absorptive branch with the isolation resistors. Equations are derived by using the two‐parity mode analysis, and main parameters are investigated in detail. For validation, a prototype was designed and fabricated. Test results show that the 3‐dB FBW can reach 87% with a 10‐dB input absorptive FBW of 200%. Besides, for the output ports with 10‐dB return loss and 10‐dB isolation, the FBWs are 94% and 91.5%, respectively. It also features high frequency selectivity and low insertion loss.
{"title":"High‐selectivity wideband four‐way filtering power divider with input absorptive feature","authors":"Siran Zhang, Hongmei Liu, Zhongbao Wang, Shaojun Fang","doi":"10.1002/cta.4227","DOIUrl":"https://doi.org/10.1002/cta.4227","url":null,"abstract":"In the paper, a high‐selectivity wideband four‐way filtering power divider with input absorptive feature is presented. It consists of two parallel‐coupled lines (CLs), two three‐coupled lines (TCLs), two open‐ended stepped branches, one absorptive branch, and two isolation resistors. The wideband filtering response is achieved by cascading the TCLs and CLs. While high selectivity is obtained by loading the open‐ended stepped branch, where two extra transmission zeros are generated. In addition, wide absorptive bandwidth with good isolations between adjacent output ports are realized by combining the absorptive branch with the isolation resistors. Equations are derived by using the two‐parity mode analysis, and main parameters are investigated in detail. For validation, a prototype was designed and fabricated. Test results show that the 3‐dB FBW can reach 87% with a 10‐dB input absorptive FBW of 200%. Besides, for the output ports with 10‐dB return loss and 10‐dB isolation, the FBWs are 94% and 91.5%, respectively. It also features high frequency selectivity and low insertion loss.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"129 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141941925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In building a smarter and more flexible low‐carbon smart grid system, alternating current (AC) microgrids using virtual synchronous generator (VSG) technology are viewed as a key link in integrating distributed renewable energy access into the main grid. Given that renewable energy sources (such as solar, hydroenergy, and wind) do not have sufficient capacity for reactive power when not available, AC microgrids face challenges in maintaining stable operation. In order to overcome this difficulty, it is hoped that digging deeper and applying more system information can significantly improve the overall performance of the microgrid. This paper proposes a novel method based on macroscopic state dynamic modeling. This method expands the understanding of the inherent rational control mechanism within the microgrid, enabling the overall control objective of the microgrid to be expressed in a more abstract and direct manner. Additionally, by implementing additional convergence constraint conditions on the macroscopic state dynamics, such as based on some optimality criteria, a set of macroscopic state controllers can be obtained to meet specific performance indicators. Theoretical analysis combined with simulation validation demonstrate the effectiveness of this macroscopic state based control strategy. It proves that when meeting the predefined design requirements, the designed controller can enhance the transient response of microgrids in practical applications, thus supporting higher rate of renewable energy access and promoting the development of the smart grid.
{"title":"Macroscopic state‐based reactive voltage control of virtual synchronous generator in AC microgrid","authors":"Fangyuan Li, Yan Liu, Yanhong Liu","doi":"10.1002/cta.4197","DOIUrl":"https://doi.org/10.1002/cta.4197","url":null,"abstract":"In building a smarter and more flexible low‐carbon smart grid system, alternating current (AC) microgrids using virtual synchronous generator (VSG) technology are viewed as a key link in integrating distributed renewable energy access into the main grid. Given that renewable energy sources (such as solar, hydroenergy, and wind) do not have sufficient capacity for reactive power when not available, AC microgrids face challenges in maintaining stable operation. In order to overcome this difficulty, it is hoped that digging deeper and applying more system information can significantly improve the overall performance of the microgrid. This paper proposes a novel method based on macroscopic state dynamic modeling. This method expands the understanding of the inherent rational control mechanism within the microgrid, enabling the overall control objective of the microgrid to be expressed in a more abstract and direct manner. Additionally, by implementing additional convergence constraint conditions on the macroscopic state dynamics, such as based on some optimality criteria, a set of macroscopic state controllers can be obtained to meet specific performance indicators. Theoretical analysis combined with simulation validation demonstrate the effectiveness of this macroscopic state based control strategy. It proves that when meeting the predefined design requirements, the designed controller can enhance the transient response of microgrids in practical applications, thus supporting higher rate of renewable energy access and promoting the development of the smart grid.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":"33 1","pages":""},"PeriodicalIF":2.3,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141969067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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