Dingfeng Dong, Wenxin Huang, Shanfeng Zhu, Feifei Bu
Active disturbance rejection controller (ADRC) has been widely promoted in permanent magnet synchronous motor (PMSM) drives for its simple design and remarkable anti‐disturbance characteristics. To further improve the control performance, a variety of advanced ADRC schemes have been proposed in recent years. However, the majority of them focused on constructing more complicated extended state observers (ESOs) while ignoring the utilization of state feedback. Motivated by the above issue, this article proposes an enhanced virtual friction ADR speed controller (VFADRC). It is distinguished by the simpler structure compared with other ADRC schemes. Besides, the introduced zero in disturbance rejection function of VFADRC contributes to the preferable anti‐disturbance response. Moreover, the enhanced configuration of VFADRC proposed in the article further improves the speed dynamics and robustness to inertia variations. Both the theoretical analysis and experimental results validate the excellent performance of the proposed ADR controller.
{"title":"Enhanced active disturbance rejection speed controller for permanent magnet synchronous motors using virtual friction feedback technique","authors":"Dingfeng Dong, Wenxin Huang, Shanfeng Zhu, Feifei Bu","doi":"10.1002/cta.4249","DOIUrl":"https://doi.org/10.1002/cta.4249","url":null,"abstract":"Active disturbance rejection controller (ADRC) has been widely promoted in permanent magnet synchronous motor (PMSM) drives for its simple design and remarkable anti‐disturbance characteristics. To further improve the control performance, a variety of advanced ADRC schemes have been proposed in recent years. However, the majority of them focused on constructing more complicated extended state observers (ESOs) while ignoring the utilization of state feedback. Motivated by the above issue, this article proposes an enhanced virtual friction ADR speed controller (VFADRC). It is distinguished by the simpler structure compared with other ADRC schemes. Besides, the introduced zero in disturbance rejection function of VFADRC contributes to the preferable anti‐disturbance response. Moreover, the enhanced configuration of VFADRC proposed in the article further improves the speed dynamics and robustness to inertia variations. Both the theoretical analysis and experimental results validate the excellent performance of the proposed ADR controller.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142227583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tongqing Xu, Tan Yao, Ning Li, JunMing Li, Xinlong Min, Hao Xiao
Lossless image compression techniques shrink the image size to improve the transmission efficiency and reduce the occupied storage space while ensuring the quality of the image is lossless. Among them, the LOCO‐I/JPEG‐LS algorithm benefits high lossless compression ratio and low computational complexity and thus is widely used for various real‐time applications. However, due to the problems of the context dependency in the LOCO‐I, the parallelism in the algorithm is greatly constrained, which significantly limits the throughput and the real‐time performance of hardware implementations. Existing designs achieve more parallelism by using a lot of hardware costs or straightforward chunking with losing compression ratio. In order to trade off the parallelism and the compression ratio, this paper proposes a chunk‐oriented error modeling scheme for LOCO‐I, which enables parallelism in both compression and decompression and achieves a better compression ratio in chunks. Based on the optimized algorithm, a high‐throughput flexible lossless compression and decompression architecture (HFCD) is proposed, which achieves higher pixel per clock (PPC) with less hardware cost. Additionally, HFCD introduces a parameter sharing mechanism to enable random access of image chunks to improve the flexibility for decompression. Experimental results show that, compared with state‐of‐the‐art works, HFCD achieves 3.02–13.50 times improvement for the PPC of compression. For decompression, benefiting from our optimizations, HFCD achieves 22.4 times speedup compared to the software solution.
{"title":"A high‐throughput flexible lossless compression and decompression architecture for color images","authors":"Tongqing Xu, Tan Yao, Ning Li, JunMing Li, Xinlong Min, Hao Xiao","doi":"10.1002/cta.4230","DOIUrl":"https://doi.org/10.1002/cta.4230","url":null,"abstract":"Lossless image compression techniques shrink the image size to improve the transmission efficiency and reduce the occupied storage space while ensuring the quality of the image is lossless. Among them, the LOCO‐I/JPEG‐LS algorithm benefits high lossless compression ratio and low computational complexity and thus is widely used for various real‐time applications. However, due to the problems of the context dependency in the LOCO‐I, the parallelism in the algorithm is greatly constrained, which significantly limits the throughput and the real‐time performance of hardware implementations. Existing designs achieve more parallelism by using a lot of hardware costs or straightforward chunking with losing compression ratio. In order to trade off the parallelism and the compression ratio, this paper proposes a chunk‐oriented error modeling scheme for LOCO‐I, which enables parallelism in both compression and decompression and achieves a better compression ratio in chunks. Based on the optimized algorithm, a high‐throughput flexible lossless compression and decompression architecture (HFCD) is proposed, which achieves higher pixel per clock (PPC) with less hardware cost. Additionally, HFCD introduces a parameter sharing mechanism to enable random access of image chunks to improve the flexibility for decompression. Experimental results show that, compared with state‐of‐the‐art works, HFCD achieves 3.02–13.50 times improvement for the PPC of compression. For decompression, benefiting from our optimizations, HFCD achieves 22.4 times speedup compared to the software solution.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper introduces a coupled inductor (CI)‐based high step‐up DC‐DC converter. Cascaded or quadratic DC–DC converters are the most practical solution to achieve a wide conversion ratio and reduced current ripple. The proposed structure (P1) is achieved by a combination of a base structure of two‐stage boost converter with one active switch, a CI, and a voltage multiplier cell (VMC). The secondary side of the CI is placed at the output side, where it is combined with a VMC. In the proposed topology, a passive clamp consisting of a diode and a capacitor is added to minimize the voltage stress on the active switch. In addition, the passive clamp recycles the leakage energy of the CI and causes to increase the efficiency. The input source current ripple is low, and the input current is continuous, which are very suitable for renewable energy applications. Additionally, the voltage stresses on switches are less than some quadratic DC‐DC boost converters that have been presented. Also, an extended topology of P1 is proposed as the second proposed converter (P2), to enhance the operation of P1. Moreover, to show the feasibility and performance of the presented converter, a laboratory prototype circuit is examined. The results accredit the theoretical analysis and experimental outcomes of the presented converter.
本文介绍了一种基于耦合电感器 (CI) 的高升压直流-直流转换器。级联或二次直流-直流转换器是实现宽转换率和降低电流纹波的最实用解决方案。所提出的结构（P1）是由带有一个有源开关、一个 CI 和一个电压倍增单元（VMC）的两级升压转换器的基本结构组合而成。CI 的二次侧位于输出侧，与 VMC 相结合。在所提出的拓扑结构中，增加了一个由二极管和电容器组成的无源钳位，以最大限度地减少有源开关上的电压应力。此外，无源箝位还能回收 CI 的泄漏能量，从而提高效率。输入源电流纹波小，输入电流连续，非常适合可再生能源应用。此外，开关上的电压应力也小于一些二次直流-直流升压转换器。此外，还提出了 P1 的扩展拓扑结构，作为第二个拟议转换器（P2），以增强 P1 的运行。此外，为了证明所提出的转换器的可行性和性能，还对实验室原型电路进行了检查。结果证实了所提出的转换器的理论分析和实验结果。
{"title":"A high step‐up single switch DC‐DC quadratic boost converter based on coupled inductor with reduced voltage stress of power components","authors":"Seyyed Alireza Modaberi, Tohid Ghanizadeh Bolandi, Mahyar Hassanifar, Yousef Neyshabouri","doi":"10.1002/cta.4233","DOIUrl":"https://doi.org/10.1002/cta.4233","url":null,"abstract":"This paper introduces a coupled inductor (CI)‐based high step‐up DC‐DC converter. Cascaded or quadratic DC–DC converters are the most practical solution to achieve a wide conversion ratio and reduced current ripple. The proposed structure (P1) is achieved by a combination of a base structure of two‐stage boost converter with one active switch, a CI, and a voltage multiplier cell (VMC). The secondary side of the CI is placed at the output side, where it is combined with a VMC. In the proposed topology, a passive clamp consisting of a diode and a capacitor is added to minimize the voltage stress on the active switch. In addition, the passive clamp recycles the leakage energy of the CI and causes to increase the efficiency. The input source current ripple is low, and the input current is continuous, which are very suitable for renewable energy applications. Additionally, the voltage stresses on switches are less than some quadratic DC‐DC boost converters that have been presented. Also, an extended topology of P1 is proposed as the second proposed converter (P2), to enhance the operation of P1. Moreover, to show the feasibility and performance of the presented converter, a laboratory prototype circuit is examined. The results accredit the theoretical analysis and experimental outcomes of the presented converter.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a high‐performance and area‐efficient hardware structure of the ChaCha20 stream cipher is presented. The most complex operation in the ChaCha20 stream cipher is addition modulo 232. The addition is used in the round function computations and the addition of the last round result and initial state. We use the proposed sparse parallel prefix adder for the implementation of addition modulo 232, which has a low critical path delay. In the proposed structure, to reduce area consumption, we use resource sharing with minimum hardware. To increase throughput and speed, the four registers are used with two main tasks including the storing intermediate results of the round function and the break critical path delay for the pipeline of the structure. Also, based on the used registers in the structure, the computations of the last clock cycle of the previous round function and the first clock cycle from the next round function are computed concurrently. Implementation results such as delay, computation time, area, and throughput of the proposed structure in 180 nm CMOS technology and FPGA implementation on the device Xilinx Virtex‐7 XC7VX485T are achieved. The achieved results show that the design has better hardware and timing properties compared with other works.
{"title":"High‐Performance Hardware Structure of ChaCha20 Stream Cipher Based on Sparse Parallel Prefix Adder","authors":"Bahram Rashidi","doi":"10.1002/cta.4264","DOIUrl":"https://doi.org/10.1002/cta.4264","url":null,"abstract":"In this paper, a high‐performance and area‐efficient hardware structure of the ChaCha20 stream cipher is presented. The most complex operation in the ChaCha20 stream cipher is addition modulo 2<jats:sup>32</jats:sup>. The addition is used in the round function computations and the addition of the last round result and initial state. We use the proposed sparse parallel prefix adder for the implementation of addition modulo 2<jats:sup>32</jats:sup>, which has a low critical path delay. In the proposed structure, to reduce area consumption, we use resource sharing with minimum hardware. To increase throughput and speed, the four registers are used with two main tasks including the storing intermediate results of the round function and the break critical path delay for the pipeline of the structure. Also, based on the used registers in the structure, the computations of the last clock cycle of the previous round function and the first clock cycle from the next round function are computed concurrently. Implementation results such as delay, computation time, area, and throughput of the proposed structure in 180 nm CMOS technology and FPGA implementation on the device Xilinx Virtex‐7 XC7VX485T are achieved. The achieved results show that the design has better hardware and timing properties compared with other works.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a novel control method to achieve the true unity power factor for a single‐phase boost rectifier. Firstly, the phase difference between the voltage and current on the AC side is calculated by the heterodyne method. Secondly, this phase difference is fed into an integral regulator to get a phase shift angle. Finally, by using the heterodyne method once again, the AC side current is phase‐shifted and used as the modulation signal for the single‐phase full bridge rectifier circuit and ultimately yields a unity power factor. The experimental results verify the effectiveness and feasibility of this strategy.
{"title":"Unity Power Factor Control of Single‐Phase Boost Rectifier Based on Dual Heterodyne Method","authors":"Liping Zhong, Song Hu","doi":"10.1002/cta.4271","DOIUrl":"https://doi.org/10.1002/cta.4271","url":null,"abstract":"This paper proposes a novel control method to achieve the true unity power factor for a single‐phase boost rectifier. Firstly, the phase difference between the voltage and current on the AC side is calculated by the heterodyne method. Secondly, this phase difference is fed into an integral regulator to get a phase shift angle. Finally, by using the heterodyne method once again, the AC side current is phase‐shifted and used as the modulation signal for the single‐phase full bridge rectifier circuit and ultimately yields a unity power factor. The experimental results verify the effectiveness and feasibility of this strategy.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The key circuits of servo channel loading card with high‐precision data acquisition and output functions for wing fatigue testing are studied and improved in this paper. To solve the problem of large offset voltage in some op‐amps, non‐inverting combined amplifier circuit (NCAC) and inverting combination amplifier circuit (ICAC) are proposed by utilizing precision op‐amps combined with wide voltage and high‐power output op‐amps. In the force signal acquisition section, a non‐inverting combined zeroing filter circuit (NCZFC) is proposed to improve the precision of signal acquisition. In the excitation source output section, a non‐inverting combined excitation output circuit (NCEOC) is proposed to improve the precision of the positive excitation output; an inverting combined excitation output circuit (ICEOC) is also proposed, which improves the precision of the negative excitation output and also realizes the inversion of the input and output signals. In the servo drive output section, a non‐inverting combined voltage and current conversion circuit is proposed to improve the precision of voltage and current outputs, which has two modes of non‐inverting combined voltage output (NCVO) and non‐inverting combined current output (NCIO) modes. Simulation experiments in Multisim and actual tests have been carried out on the above improved circuits to verify the stability and precision.
{"title":"Research on key circuits of high‐precision servo channel loading card for wing fatigue testing","authors":"Baoshui Zhao, Yancai Xiao, Haikuo Shen, Shaodan Zhi","doi":"10.1002/cta.4258","DOIUrl":"https://doi.org/10.1002/cta.4258","url":null,"abstract":"The key circuits of servo channel loading card with high‐precision data acquisition and output functions for wing fatigue testing are studied and improved in this paper. To solve the problem of large offset voltage in some op‐amps, non‐inverting combined amplifier circuit (NCAC) and inverting combination amplifier circuit (ICAC) are proposed by utilizing precision op‐amps combined with wide voltage and high‐power output op‐amps. In the force signal acquisition section, a non‐inverting combined zeroing filter circuit (NCZFC) is proposed to improve the precision of signal acquisition. In the excitation source output section, a non‐inverting combined excitation output circuit (NCEOC) is proposed to improve the precision of the positive excitation output; an inverting combined excitation output circuit (ICEOC) is also proposed, which improves the precision of the negative excitation output and also realizes the inversion of the input and output signals. In the servo drive output section, a non‐inverting combined voltage and current conversion circuit is proposed to improve the precision of voltage and current outputs, which has two modes of non‐inverting combined voltage output (NCVO) and non‐inverting combined current output (NCIO) modes. Simulation experiments in Multisim and actual tests have been carried out on the above improved circuits to verify the stability and precision.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gideon Igor Carvalho Lobato, Menaouar Berrehil El Kattel, Fernando Luiz Marcelo Antunes, Sidelmo Magalhães Silva, Braz de Jesus Cardoso Filho
This paper introduces a novel topology for a non‐isolated bidirectional multiphase single inductor (BMPSIC) DC–DC converter. The proposed BMPSIC requires only a single inductor, irrespective of the number of arms, and features reduced volume and weight compared to the total magnetics needed for a conventional converter with similar ratings. The proposed BMPSIC advantages include a high DC voltage gain without operating on a large duty cycle, voltage stress on the power switches equal to that at the high‐voltage port, easy implementation, and a lower cost for application at high‐power densities. Furthermore, this topology requires only one current and voltage control loop. This paper thoroughly details the steady‐state operating principles of the inductor current continuous mode. It provides theoretical and mathematical analysis, including a comparative analysis of the proposed BMPSIC against earlier DC–DC converters, highlighting the superior performance and efficiency of the BMPSIC. An 8‐kW laboratory prototype, designed as a proof of concept, has been meticulously developed and tested, showcasing the performance of the converter across a broad range of load variations. The efficiency measured for the rated load exceeded 98.2% at the low‐voltage port of 250 V and the high‐voltage port of 400 V. Additionally, the article features Video S1, which illustrates the functioning of the converter.
{"title":"A novel topology of a non‐isolated bidirectional multiphase single inductor DC–DC converter","authors":"Gideon Igor Carvalho Lobato, Menaouar Berrehil El Kattel, Fernando Luiz Marcelo Antunes, Sidelmo Magalhães Silva, Braz de Jesus Cardoso Filho","doi":"10.1002/cta.4257","DOIUrl":"https://doi.org/10.1002/cta.4257","url":null,"abstract":"This paper introduces a novel topology for a non‐isolated bidirectional multiphase single inductor (BMPSIC) DC–DC converter. The proposed BMPSIC requires only a single inductor, irrespective of the number of arms, and features reduced volume and weight compared to the total magnetics needed for a conventional converter with similar ratings. The proposed BMPSIC advantages include a high DC voltage gain without operating on a large duty cycle, voltage stress on the power switches equal to that at the high‐voltage port, easy implementation, and a lower cost for application at high‐power densities. Furthermore, this topology requires only one current and voltage control loop. This paper thoroughly details the steady‐state operating principles of the inductor current continuous mode. It provides theoretical and mathematical analysis, including a comparative analysis of the proposed BMPSIC against earlier DC–DC converters, highlighting the superior performance and efficiency of the BMPSIC. An 8‐kW laboratory prototype, designed as a proof of concept, has been meticulously developed and tested, showcasing the performance of the converter across a broad range of load variations. The efficiency measured for the rated load exceeded 98.2% at the low‐voltage port of 250 V and the high‐voltage port of 400 V. Additionally, the article features Video S1, which illustrates the functioning of the converter.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142223857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SummaryOscillator‐based Ising machines (OIMs) particularly those realized in complementary metal oxide semiconductor (CMOS) have gained popularity for solving combinatorial optimization problems (COPs) in recent years due to its scalability, low‐power consumption, and room temperature operation. The implemented OIMs have thus far focused on solving optimization problems with a single global minima. However, real‐life optimization problems often have multiple solutions. In this paper, we propose a generalized approach to solve COPs with single (without contention), as well as multiple (with contention) solutions using frequency tunable CMOS ring oscillator (ROSC)‐based Ising machine. A capacitive frequency tunable CMOS ring‐oscillator coupled with an internal subharmonic injection locking (SHIL) generator realized using 14‐nm FinFET models works as Ising spin in the proposed approach. We demonstrate how frequency tuning can help in attaining good quality results and also determine all possible solutions of COP with contention. We also propose a generalized algorithm for monitoring the states of the oscillator network to indicate tuning necessity and extract solutions from the oscillator's output irrespective of the type of COP.
{"title":"Frequency tunable CMOS ring oscillator‐based Ising machine","authors":"Mizanur Rahaman Nayan, Orchi Hassan","doi":"10.1002/cta.4256","DOIUrl":"https://doi.org/10.1002/cta.4256","url":null,"abstract":"SummaryOscillator‐based Ising machines (OIMs) particularly those realized in complementary metal oxide semiconductor (CMOS) have gained popularity for solving combinatorial optimization problems (COPs) in recent years due to its scalability, low‐power consumption, and room temperature operation. The implemented OIMs have thus far focused on solving optimization problems with a single global minima. However, real‐life optimization problems often have multiple solutions. In this paper, we propose a generalized approach to solve COPs with single (without contention), as well as multiple (with contention) solutions using frequency tunable CMOS ring oscillator (ROSC)‐based Ising machine. A capacitive frequency tunable CMOS ring‐oscillator coupled with an internal subharmonic injection locking (SHIL) generator realized using 14‐nm FinFET models works as Ising spin in the proposed approach. We demonstrate how frequency tuning can help in attaining good quality results and also determine all possible solutions of COP with contention. We also propose a generalized algorithm for monitoring the states of the oscillator network to indicate tuning necessity and extract solutions from the oscillator's output irrespective of the type of COP.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wireless power transfer (WPT) is an emerging technology that enables the wireless transfer of electrical energy from power supplies to electrical equipment. It has been widely used in electric vehicles, mobile phones, household appliances, medical devices, and other fields. However, the frequency splitting and bifurcation phenomena existing in WPT systems are the fundamental obstacles and challenges that affect the effective operation of WPT systems. In this paper, a method based on the fractional‐order circuit is proposed to simultaneously suppress the frequency splitting and bifurcation phenomena by changing the order of fractional‐order capacitor. By replacing the compensation capacitor in the transmitter of the traditional WPT system with a fractional‐order capacitor, a fractional‐order WPT system is formed. Then, using fractional calculus and circuit theory, the mathematical model of the proposed WPT system containing a fractional‐order capacitor is established, and the frequency splitting and bifurcation phenomena are analyzed. The theoretical results show that the frequency splitting and bifurcation phenomena are suppressed only by adjusting the order of fractional‐order capacitor, and the output power of the original resonant frequency is improved. Finally, the experimental prototype is implemented to validate the theoretical results.
{"title":"A Fractional‐Order Method of Frequency Splitting and Bifurcation Suppression for Wireless Power Transfer Systems","authors":"Xujian Shu, Xueqi Zhang, Yanwei Jiang, Bo Zhang","doi":"10.1002/cta.4262","DOIUrl":"https://doi.org/10.1002/cta.4262","url":null,"abstract":"Wireless power transfer (WPT) is an emerging technology that enables the wireless transfer of electrical energy from power supplies to electrical equipment. It has been widely used in electric vehicles, mobile phones, household appliances, medical devices, and other fields. However, the frequency splitting and bifurcation phenomena existing in WPT systems are the fundamental obstacles and challenges that affect the effective operation of WPT systems. In this paper, a method based on the fractional‐order circuit is proposed to simultaneously suppress the frequency splitting and bifurcation phenomena by changing the order of fractional‐order capacitor. By replacing the compensation capacitor in the transmitter of the traditional WPT system with a fractional‐order capacitor, a fractional‐order WPT system is formed. Then, using fractional calculus and circuit theory, the mathematical model of the proposed WPT system containing a fractional‐order capacitor is established, and the frequency splitting and bifurcation phenomena are analyzed. The theoretical results show that the frequency splitting and bifurcation phenomena are suppressed only by adjusting the order of fractional‐order capacitor, and the output power of the original resonant frequency is improved. Finally, the experimental prototype is implemented to validate the theoretical results.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To enhance the stabilizing function and boost the output power of the inductive coupling power transfer (ICPT) system, a power stabilization control method based on LCL‐P resonance compensation for a wireless energy transmission system is proposed. “L” represents inductance, “C” represents capacitance, “LCL” refers to the primary‐side compensation structure, and “P” indicates that the secondary side is compensated in parallel . Firstly, this paper synthesizes the modeling principle of the gyrator equivalent model of the resonant circuit and coupled inductor, graphically analyzes the resonant compensation structure, and derives the circuit characteristics of the LCL‐P compensation structure. Then, this paper proposes an improved control strategy for the Maximum Power Point Tracking (MPPT) algorithm to dynamically track the output power and thus obtain the optimal operating point through frequency conversion. Lastly, using MATLAB/Simulink software to build the simulation model of the wireless charging system through parameter design, the impact of the conventional DC/DC power control method is contrasted with the algorithmic control suggested in this paper. The results demonstrate that: the device can realize power transfer of 2.7 KW level, the energy transfer efficiency reaches more than 90%, the inverter realizes soft‐switching operation, and the improved MPPT algorithmic control strategy proposed in this paper is utilized to achieve better closed‐loop control of the system. The excellent characteristics of the LCL‐P compensation structure in high‐power transmission applications, as well as the correctness and feasibility of the control algorithm proposed in this paper, are demonstrated through simulation and practical experiments. This is a significant step towards improving the wide‐range adaptation of the wireless charging system, which is based on the LCL‐P resonance compensation to the changes in the load and coupling.
{"title":"Power stabilization control of wireless charging system based on LCL‐P compensation structure","authors":"Yonghui Yue, Zhenao Sun, Mingyu Lu","doi":"10.1002/cta.4250","DOIUrl":"https://doi.org/10.1002/cta.4250","url":null,"abstract":"To enhance the stabilizing function and boost the output power of the inductive coupling power transfer (ICPT) system, a power stabilization control method based on LCL‐P resonance compensation for a wireless energy transmission system is proposed. “L” represents inductance, “C” represents capacitance, “LCL” refers to the primary‐side compensation structure, and “P” indicates that the secondary side is compensated in parallel . Firstly, this paper synthesizes the modeling principle of the gyrator equivalent model of the resonant circuit and coupled inductor, graphically analyzes the resonant compensation structure, and derives the circuit characteristics of the LCL‐P compensation structure. Then, this paper proposes an improved control strategy for the Maximum Power Point Tracking (MPPT) algorithm to dynamically track the output power and thus obtain the optimal operating point through frequency conversion. Lastly, using MATLAB/Simulink software to build the simulation model of the wireless charging system through parameter design, the impact of the conventional DC/DC power control method is contrasted with the algorithmic control suggested in this paper. The results demonstrate that: the device can realize power transfer of 2.7 KW level, the energy transfer efficiency reaches more than 90%, the inverter realizes soft‐switching operation, and the improved MPPT algorithmic control strategy proposed in this paper is utilized to achieve better closed‐loop control of the system. The excellent characteristics of the LCL‐P compensation structure in high‐power transmission applications, as well as the correctness and feasibility of the control algorithm proposed in this paper, are demonstrated through simulation and practical experiments. This is a significant step towards improving the wide‐range adaptation of the wireless charging system, which is based on the LCL‐P resonance compensation to the changes in the load and coupling.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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