This paper proposes a novel configuration for a multiport boost converter (MPBC) with a single inductor (SI), accounting for equivalent series resistances (ESRs) and minimizing input switching stress. The MPBC performance is evaluated and compared with other established topologies. The proposed MPBC interfaces two unidirectional input DC power ports and a rechargeable port for an energy storage element (ESE) with two output ports. The design integrates two renewable sources with the ESE as a third source. One output is for higher voltage, linked to a single‐phase inverter for AC loads. The other output is for lower DC voltage, used for DC loads. The configuration can be adjusted based on requirements. This converter has numerous applications in renewable energy systems, electric vehicles, and agriculture. The steady‐state and small signal modeling of MPBC has been done to derive the mathematical expressions for analyzing stability, stresses (both voltage and current), and performance considering ESRs. A 240 W, MPBC is fabricated along with improved switching strategies using DSP TMS320F28379D. Experimental and simulation results are compared to show the effectiveness of proposed scheme on stability, stresses, and efficient power transfer. Output power is regulated effectively by sharing the input power thereby reducing voltage stress on switches.
{"title":"Mathematical modeling and stress‐aware stability analysis of a nonideal multiport Single Inductor DC–DC converter for renewable energy","authors":"Ashutosh Gupta, Dheeraj Joshi","doi":"10.1002/cta.4234","DOIUrl":"https://doi.org/10.1002/cta.4234","url":null,"abstract":"This paper proposes a novel configuration for a multiport boost converter (MPBC) with a single inductor (SI), accounting for equivalent series resistances (ESRs) and minimizing input switching stress. The MPBC performance is evaluated and compared with other established topologies. The proposed MPBC interfaces two unidirectional input DC power ports and a rechargeable port for an energy storage element (ESE) with two output ports. The design integrates two renewable sources with the ESE as a third source. One output is for higher voltage, linked to a single‐phase inverter for AC loads. The other output is for lower DC voltage, used for DC loads. The configuration can be adjusted based on requirements. This converter has numerous applications in renewable energy systems, electric vehicles, and agriculture. The steady‐state and small signal modeling of MPBC has been done to derive the mathematical expressions for analyzing stability, stresses (both voltage and current), and performance considering ESRs. A 240 W, MPBC is fabricated along with improved switching strategies using DSP TMS320F28379D. Experimental and simulation results are compared to show the effectiveness of proposed scheme on stability, stresses, and efficient power transfer. Output power is regulated effectively by sharing the input power thereby reducing voltage stress on switches.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A DC‐DC converter with high boost and low switching voltage stress is proposed by combining switched capacitor (SC) and coupled inductor (CL) techniques based on a conventional boost circuit. The design methodology of this converter includes substituting SC for a single switch in the boost converter, combining CL, and integrating a resonant boost circuit for absorbing leakage inductance. The improved power switch topology in this design has lower voltage stress, lower diode current stress, fewer total components, and common ground than other conventional DC‐DC converters. The operating modes and steady state analysis of the converter are provided in terms of leakage inductance utilization, with component stress derivation and theoretical efficiency analysis. In addition, comparisons with other dc‐dc converters are made. Subsequently, experiments were conducted on a 200 W DC‐DC converter prototype to verify the reliability of the converter.
通过在传统升压电路的基础上结合开关电容（SC）和耦合电感（CL）技术，提出了一种具有高升压和低开关电压应力的直流-直流转换器。该转换器的设计方法包括用 SC 代替升压转换器中的单个开关、结合 CL 以及集成用于吸收漏感的谐振升压电路。与其他传统直流-直流转换器相比，该设计中改进的功率开关拓扑具有更低的电压应力、更低的二极管电流应力、更少的总元件和共地。从漏电感利用率、元件应力推导和理论效率分析的角度，提供了转换器的工作模式和稳态分析。此外，还与其他直流-直流转换器进行了比较。随后，在 200 W 直流-直流转换器原型上进行了实验，以验证转换器的可靠性。
{"title":"A novel high step‐up, low switching voltage stress DC‐DC converter using leakage inductance for resonant boosting","authors":"Yin Chen, Haibin Li, Huaming Chen, Tao Jin","doi":"10.1002/cta.4236","DOIUrl":"https://doi.org/10.1002/cta.4236","url":null,"abstract":"A DC‐DC converter with high boost and low switching voltage stress is proposed by combining switched capacitor (SC) and coupled inductor (CL) techniques based on a conventional boost circuit. The design methodology of this converter includes substituting SC for a single switch in the boost converter, combining CL, and integrating a resonant boost circuit for absorbing leakage inductance. The improved power switch topology in this design has lower voltage stress, lower diode current stress, fewer total components, and common ground than other conventional DC‐DC converters. The operating modes and steady state analysis of the converter are provided in terms of leakage inductance utilization, with component stress derivation and theoretical efficiency analysis. In addition, comparisons with other dc‐dc converters are made. Subsequently, experiments were conducted on a 200 W DC‐DC converter prototype to verify the reliability of the converter.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SummaryIn this paper, computational analysis of a Caputo fractional variable‐order system with inductor‐capacitor (LC) and resistor‐capacitor (RC) electrical circuit models is presented. The existence and uniqueness of solutions to the given problem are determined using Schaefer's fixed point theorem and the Banach contraction principle, respectively. The proposed problem's computational consequences are addressed and analyzed using modified Euler and Runge–Kutta fourth‐order techniques. Furthermore, the suggested model compares several orders, including integer, fractional, and variable orders. To demonstrate the utility of the proposed approach, computational simulations are carried out on LC and RC circuit models of various orders. Furthermore, a comparative analysis with previous investigations has been carried. For the given problem, the numerical solution results in high‐precision approximations.
{"title":"Variable‐order Caputo derivative of LC and RC circuits system with numerical analysis","authors":"S Naveen, V Parthiban","doi":"10.1002/cta.4240","DOIUrl":"https://doi.org/10.1002/cta.4240","url":null,"abstract":"SummaryIn this paper, computational analysis of a Caputo fractional variable‐order system with inductor‐capacitor (LC) and resistor‐capacitor (RC) electrical circuit models is presented. The existence and uniqueness of solutions to the given problem are determined using Schaefer's fixed point theorem and the Banach contraction principle, respectively. The proposed problem's computational consequences are addressed and analyzed using modified Euler and Runge–Kutta fourth‐order techniques. Furthermore, the suggested model compares several orders, including integer, fractional, and variable orders. To demonstrate the utility of the proposed approach, computational simulations are carried out on LC and RC circuit models of various orders. Furthermore, a comparative analysis with previous investigations has been carried. For the given problem, the numerical solution results in high‐precision approximations.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cheng Liu, Jiaqing Zhao, Yang Zhang, Zhennan Xi, Jiawei Deng, Xiangdong Luo
Aiming to address the timing skew mismatch in the time‐interleaved analog‐to‐digital converter (TIADC) system, this paper presents a timing skew mismatch calibration method based on a back propagation (BP) neural network optimized by an adaptive genetic algorithm (AGA). In this paper, a trained BP neural network is used to detect the timing skew mismatch in the TIADC system, and the variable delay line is used to calibrate it. In this paper, AGA is used to optimize the BP neural network, accelerating its training speed and improving the detection accuracy of timing skew mismatch in the system. The proposed approach boasts superior detection speed and accuracy compared to other methods. In this paper, an 18‐bit 1GS/S 4‐channel TIADC system is simulated and the timing skew mismatch in the system is corrected. Simulation results show that the proposed calibration method has fast detection speed, high detection accuracy, and calibration accuracy. After completing the timing skew mismatch correction, the performance of the TIADC system is dramatically improved. The effective number of bits (ENOB) of the system increases by 9.5 bits, and the spurious‐free dynamic range (SFDR) increases by 59.9 dB.
为了解决时间交错模数转换器（TIADC）系统中的时序偏移失配问题，本文提出了一种基于反向传播（BP）神经网络的时序偏移失配校准方法，该方法通过自适应遗传算法（AGA）进行了优化。本文使用训练有素的 BP 神经网络来检测 TIADC 系统中的时序偏斜失配，并使用可变延迟线对其进行校准。本文使用 AGA 对 BP 神经网络进行优化，加快了其训练速度，提高了系统中时序偏移失配的检测精度。与其他方法相比，本文提出的方法具有更高的检测速度和精度。本文仿真了一个 18 位 1GS/S 4 通道 TIADC 系统，并修正了系统中的时序偏移失配问题。仿真结果表明，所提出的校准方法具有检测速度快、检测精度高、校准准确的特点。完成时序偏移失配校正后，TIADC 系统的性能显著提高。系统的有效位数（ENOB）增加了 9.5 位，无杂散动态范围（SFDR）增加了 59.9 dB。
{"title":"Calibration on timing skew mismatch of time‐interleaved ADC based on optimized adaptive genetic algorithm back‐propagation neural network","authors":"Cheng Liu, Jiaqing Zhao, Yang Zhang, Zhennan Xi, Jiawei Deng, Xiangdong Luo","doi":"10.1002/cta.4252","DOIUrl":"https://doi.org/10.1002/cta.4252","url":null,"abstract":"Aiming to address the timing skew mismatch in the time‐interleaved analog‐to‐digital converter (TIADC) system, this paper presents a timing skew mismatch calibration method based on a back propagation (BP) neural network optimized by an adaptive genetic algorithm (AGA). In this paper, a trained BP neural network is used to detect the timing skew mismatch in the TIADC system, and the variable delay line is used to calibrate it. In this paper, AGA is used to optimize the BP neural network, accelerating its training speed and improving the detection accuracy of timing skew mismatch in the system. The proposed approach boasts superior detection speed and accuracy compared to other methods. In this paper, an 18‐bit 1GS/S 4‐channel TIADC system is simulated and the timing skew mismatch in the system is corrected. Simulation results show that the proposed calibration method has fast detection speed, high detection accuracy, and calibration accuracy. After completing the timing skew mismatch correction, the performance of the TIADC system is dramatically improved. The effective number of bits (ENOB) of the system increases by 9.5 bits, and the spurious‐free dynamic range (SFDR) increases by 59.9 dB.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The quadratic buck converter is renowned for its steep step‐down capability. It encounters increased losses due to its high component count. In scenarios with light loads, switching losses become the dominant factor. Additionally, the presence of two right‐half plane zeros impairs transient response, even at high‐frequency switching operations. Incorporating this converter into the digital domain introduces an undesired phenomenon known as subharmonic oscillation, rendering the system unstable, albeit potentially mitigated over time—a drawback particularly undesirable for converters tasked with rapid load dynamics. This paper introduces an adaptive pulse skipping modulation scheme to control metal–oxide–semiconductor field‐effect transistor (MOSFET) switching actions, enhancing overall efficiency in discontinuous conduction mode. Furthermore, the effects of right half‐plane (RHP) zeros on stability are analyzed within these switching schemes. The proposed scheme is integrated with voltage‐mode control. Simulation and theoretical analyses are conducted to validate this converter. A flat efficiency of 89% to 86% for the load range of 25 to 700 mA is obtained, outperforming other existing schemes. The results demonstrate that the adaptive pulse modulation scheme effectively improves efficiency and stability in discontinuous conduction mode converters. This research provides valuable insights for optimizing power electronics systems with varying load dynamics.
二次降压转换器以其陡峭的降压能力而闻名。由于元件数量较多，它的损耗也随之增加。在轻负载情况下，开关损耗成为主要因素。此外，即使在高频开关操作时，两个右半平面零点的存在也会影响瞬态响应。将这种转换器纳入数字域，会引入一种不希望出现的现象，即次谐振，从而使系统变得不稳定，尽管随着时间的推移有可能得到缓解--这种缺点对于承担快速负载动态任务的转换器来说尤其不可取。本文介绍了一种自适应脉冲跳变调制方案，用于控制金属氧化物半导体场效应晶体管（MOSFET）的开关动作，从而提高非连续传导模式下的整体效率。此外，还分析了这些开关方案中右半平面（RHP）零点对稳定性的影响。所提出的方案与电压模式控制相结合。通过仿真和理论分析，对该转换器进行了验证。在 25 至 700 mA 的负载范围内，获得了 89% 至 86% 的平效率，优于其他现有方案。结果表明，自适应脉冲调制方案能有效提高不连续传导模式转换器的效率和稳定性。这项研究为优化负载动态变化的电力电子系统提供了宝贵的见解。
{"title":"High‐frequency digitally adaptive pulse skipping modulated voltage‐mode controlled quadratic buck converter","authors":"Vijay Kumar Gupta, Bipin Chandra Mandi","doi":"10.1002/cta.4247","DOIUrl":"https://doi.org/10.1002/cta.4247","url":null,"abstract":"The quadratic buck converter is renowned for its steep step‐down capability. It encounters increased losses due to its high component count. In scenarios with light loads, switching losses become the dominant factor. Additionally, the presence of two right‐half plane zeros impairs transient response, even at high‐frequency switching operations. Incorporating this converter into the digital domain introduces an undesired phenomenon known as subharmonic oscillation, rendering the system unstable, albeit potentially mitigated over time—a drawback particularly undesirable for converters tasked with rapid load dynamics. This paper introduces an adaptive pulse skipping modulation scheme to control metal–oxide–semiconductor field‐effect transistor (MOSFET) switching actions, enhancing overall efficiency in discontinuous conduction mode. Furthermore, the effects of right half‐plane (RHP) zeros on stability are analyzed within these switching schemes. The proposed scheme is integrated with voltage‐mode control. Simulation and theoretical analyses are conducted to validate this converter. A flat efficiency of 89<jats:italic>%</jats:italic> to 86<jats:italic>%</jats:italic> for the load range of 25 to 700 mA is obtained, outperforming other existing schemes. The results demonstrate that the adaptive pulse modulation scheme effectively improves efficiency and stability in discontinuous conduction mode converters. This research provides valuable insights for optimizing power electronics systems with varying load dynamics.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a systematic approach to enhance the performance of a 21‐level asymmetrical multilevel inverter (MLI) with less power electronics switches and DC voltage sources. In the first step (Configuration 1), the voltage level is improved at the cost of DC‐link voltage utilization. In the second step (Configuration 2), the ratio of the DC‐link voltages is modified to improve the utilization of DC‐link voltage, with an insignificant reduction of voltage levels as compared to Configuration 1. Finally, another modification of the MLI configuration is proposed (Configuration 3), by incorporating an H‐bridge in place of a T‐type module for further improvement of DC source utilization and increasing the number of voltage levels. Thus, Configuration 3 improves the inverter's total standing voltage (TSV) and efficiency. To reduce the number of DC sources, the output voltage levels are obtained in Configuration 3 by adding and subtracting the input DC sources. Moreover, conducting switches are reduced to minimize conduction loss and maximize efficiency. The DS1103‐based digital controller is used to verify the performance of the proposed configurations, which are compared with the literature‐based MLI models.
{"title":"Systematic approach to improve performance of asymmetrical 21‐level inverter with fewer components","authors":"Madan Kumar Das, Priyatosh Mahish, Parusharamulu Buduma, Sukumar Mishra","doi":"10.1002/cta.4229","DOIUrl":"https://doi.org/10.1002/cta.4229","url":null,"abstract":"This paper proposes a systematic approach to enhance the performance of a 21‐level asymmetrical multilevel inverter (MLI) with less power electronics switches and DC voltage sources. In the first step (Configuration 1), the voltage level is improved at the cost of DC‐link voltage utilization. In the second step (Configuration 2), the ratio of the DC‐link voltages is modified to improve the utilization of DC‐link voltage, with an insignificant reduction of voltage levels as compared to Configuration 1. Finally, another modification of the MLI configuration is proposed (Configuration 3), by incorporating an H‐bridge in place of a T‐type module for further improvement of DC source utilization and increasing the number of voltage levels. Thus, Configuration 3 improves the inverter's total standing voltage (TSV) and efficiency. To reduce the number of DC sources, the output voltage levels are obtained in Configuration 3 by adding and subtracting the input DC sources. Moreover, conducting switches are reduced to minimize conduction loss and maximize efficiency. The DS1103‐based digital controller is used to verify the performance of the proposed configurations, which are compared with the literature‐based MLI models.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142223881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, a systematic theory and design approach are presented to achieve bandwidth expansion of the Doherty power amplifier (DPA) by using extended continuous Class‐GF (ECCGF) power amplifiers (PAs) as carrier PAs. The results of the theoretical analysis indicate that compared to conventional DPA, introducing ECCGF PA as carrier PA into the DPA design can establish two larger target impedance spaces with overlapping regions for saturation and output back‐off (OBO) power levels, which can reduce the design complexity of impedance inverter networks (IINs) while achieving DPA bandwidth expansion. Based on this, the proposed design theory is validated in the design and fabrication of a prototype DPA employing the CGH40010F GaN HEMT provided by MACOM. The measured results show that under continuous wave excitation, the designed DPA delivers a saturated output power of 43.1–44.2 dBm in the range of 1.3–2.7 GHz with a relative bandwidth of 70%. The drain efficiencies of 61.2%–73.2% and 42.5%–52.7% are achieved over the entire band at the saturation and 6‐dB OBO power levels, respectively. The measured results also confirmed the theoretical findings.
{"title":"Design of a Doherty power amplifier based on extended continuous class‐GF mode for broadband applications","authors":"Xuefei Xuan, Zhiqun Cheng, Brendan Hayes, Zhiwei Zhang, Ziming Zhao, Tingwei Gong, Chao Le","doi":"10.1002/cta.4215","DOIUrl":"https://doi.org/10.1002/cta.4215","url":null,"abstract":"In this article, a systematic theory and design approach are presented to achieve bandwidth expansion of the Doherty power amplifier (DPA) by using extended continuous Class‐GF (ECCGF) power amplifiers (PAs) as carrier PAs. The results of the theoretical analysis indicate that compared to conventional DPA, introducing ECCGF PA as carrier PA into the DPA design can establish two larger target impedance spaces with overlapping regions for saturation and output back‐off (OBO) power levels, which can reduce the design complexity of impedance inverter networks (IINs) while achieving DPA bandwidth expansion. Based on this, the proposed design theory is validated in the design and fabrication of a prototype DPA employing the CGH40010F GaN HEMT provided by MACOM. The measured results show that under continuous wave excitation, the designed DPA delivers a saturated output power of 43.1–44.2 dBm in the range of 1.3–2.7 GHz with a relative bandwidth of 70%. The drain efficiencies of 61.2%–73.2% and 42.5%–52.7% are achieved over the entire band at the saturation and 6‐dB OBO power levels, respectively. The measured results also confirmed the theoretical findings.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Marcus V. M. Rodrigues, Rafael Santos, Luis De Oro Arenas, Fernando P. Marafão, Flávio A. S. Gonçalves
The widespread of renewable energy sources often requires DC‐DC power converters with higher operational flexibility and voltage gain capability. The Y‐source converter offers significant features to fill this demand, but its performance can be negatively affected by coupled‐inductor leakage inductances. This paper presents simplified models for the Y‐source DC‐DC converter (YSDC) that, although not directly including the presence of leakage inductances, offer a satisfactory description of how the converter operates in terms of its steady‐state behavior, small‐signal dynamics, and estimation of power losses. These models allow for a comprehensive analysis of how non‐ideal components in the converter affect the determination of the YSDC voltage gain and efficiency and allow one to identify the most interesting design alternatives to satisfy the current and voltage stress constraints placed on the converter power switches, thus excluding undesired converter design alternatives. Experimental results with a 280 W real converter, using coupled‐inductor with leakage inductances, present results similar to those of switched circuit simulations and the derived models, thus confirming that the simplified models present satisfactory adherence to the real converter performance over the majority extent of the maximum duty cycle.
可再生能源的广泛应用往往要求直流-直流电源转换器具有更高的操作灵活性和电压增益能力。Y 源转换器具有满足这一需求的显著特点，但其性能可能会受到耦合电感漏感的负面影响。本文介绍了 Y 型源 DC-DC 转换器 (YSDC) 的简化模型，虽然没有直接包括漏感的存在，但从稳态行为、小信号动态和功率损耗估算的角度，对转换器的运行方式进行了令人满意的描述。通过这些模型，可以全面分析转换器中的非理想元件如何影响 YSDC 电压增益和效率的确定，并确定最有意义的设计方案，以满足对转换器功率开关施加的电流和电压应力约束，从而排除不受欢迎的转换器设计方案。使用带漏感的耦合电感的 280 W 实际转换器的实验结果与开关电路仿真和推导模型的结果相似，从而证实简化模型在最大占空比的大部分范围内与实际转换器性能的一致性令人满意。
{"title":"Modeling, design, and performance analysis of a Y‐source DC‐DC converter under limitations of hardware and leakage inductances","authors":"Marcus V. M. Rodrigues, Rafael Santos, Luis De Oro Arenas, Fernando P. Marafão, Flávio A. S. Gonçalves","doi":"10.1002/cta.4243","DOIUrl":"https://doi.org/10.1002/cta.4243","url":null,"abstract":"The widespread of renewable energy sources often requires DC‐DC power converters with higher operational flexibility and voltage gain capability. The Y‐source converter offers significant features to fill this demand, but its performance can be negatively affected by coupled‐inductor leakage inductances. This paper presents simplified models for the Y‐source DC‐DC converter (YSDC) that, although not directly including the presence of leakage inductances, offer a satisfactory description of how the converter operates in terms of its steady‐state behavior, small‐signal dynamics, and estimation of power losses. These models allow for a comprehensive analysis of how non‐ideal components in the converter affect the determination of the YSDC voltage gain and efficiency and allow one to identify the most interesting design alternatives to satisfy the current and voltage stress constraints placed on the converter power switches, thus excluding undesired converter design alternatives. Experimental results with a 280 W real converter, using coupled‐inductor with leakage inductances, present results similar to those of switched circuit simulations and the derived models, thus confirming that the simplified models present satisfactory adherence to the real converter performance over the majority extent of the maximum duty cycle.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper studies the influence of the gate voltage of the power amplifier (PA) on the drain current and efficiency. This study proposes a theory of controlling input non‐linearity to improve the efficiency of PAs. The theoretical efficiency of the inverse Class F PA that controls the input nonlinearity is within the range of 77% to 97%. A new design method for the inverse Class F PA reconstructs the design of the load admittance space into a region instead of a point. To verify the validity of the proposed theory, an inverse Class F PA is designed and fabricated using a commercial 10 W GaN high electron mobility transistor (HEMT). Results of the measurement show a high drain efficiency (DE) of 78.5%, an output power of 41.6 dBm, and a large signal gain of 12.1 dB at 1.5 GHz. The overall PA's size is controlled at 80*50 .
本文研究了功率放大器（PA）的栅极电压对漏极电流和效率的影响。该研究提出了一种控制输入非线性以提高功率放大器效率的理论。控制输入非线性的反向 F 类功率放大器的理论效率在 77% 至 97% 之间。反向 F 类功率放大器的新设计方法将负载导纳空间的设计重构为一个区域而不是一个点。为了验证所提理论的正确性，我们使用商用 10 W 氮化镓高电子迁移率晶体管 (HEMT) 设计并制造了反 F 类功率放大器。测量结果表明，该功率放大器的漏极效率（DE）高达 78.5%，输出功率为 41.6 dBm，在 1.5 GHz 频率下的信号增益高达 12.1 dB。功率放大器的整体尺寸控制在 80*50 厘米。
{"title":"Input–output waveform engineered inverse Class F power amplifiers with high efficiency","authors":"Zheming Zhu, Zhiqun Cheng, Minshi Jia, Kun Wang, Bingxin Li, Zhenghao Yang, Baoquan Zhong","doi":"10.1002/cta.4254","DOIUrl":"https://doi.org/10.1002/cta.4254","url":null,"abstract":"This paper studies the influence of the gate voltage of the power amplifier (PA) on the drain current and efficiency. This study proposes a theory of controlling input non‐linearity to improve the efficiency of PAs. The theoretical efficiency of the inverse Class F PA that controls the input nonlinearity is within the range of 77% to 97%. A new design method for the inverse Class F PA reconstructs the design of the load admittance space into a region instead of a point. To verify the validity of the proposed theory, an inverse Class F PA is designed and fabricated using a commercial 10 W GaN high electron mobility transistor (HEMT). Results of the measurement show a high drain efficiency (DE) of 78.5%, an output power of 41.6 dBm, and a large signal gain of 12.1 dB at 1.5 GHz. The overall PA's size is controlled at 80*50 .","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In an SRAM, threshold voltages of transistors decrease as the CMOS process technology scales down into the nanometer scale, which causes the leakage currents on the bit‐lines. The bit‐line leakage current slows reading operations or even causes reading errors. In this paper, we proposed a new scheme called RTB, which is combined with a four‐input low‐offset sense amplifier with threshold voltage consideration to solve the problem caused by bit‐line leakage current. This scheme adopts 8T cells and two pairs of bit‐lines connected to a four‐input sense amplifier to balance the bit‐line leakage current in real‐time. In this way, the maximum tolerable bit‐line leakage current can be effectively increased and the reading operation can be accelerated. Simulations in the 55 nm CMOS process design kits under different process corners, temperatures, and voltages show that the proposed scheme can increase the maximum tolerable leakage to more than 300 μA.
{"title":"Real‐time bit‐line leakage balance circuit with four‐input low‐offset SA considering threshold voltage for SRAM stability design","authors":"Chunyu Peng, Wei Hu, Hao Zheng, Wenjuan Lu, Chenghu Dai, Xiulong Wu, Zhiting Lin, Junning Chen","doi":"10.1002/cta.4248","DOIUrl":"https://doi.org/10.1002/cta.4248","url":null,"abstract":"In an SRAM, threshold voltages of transistors decrease as the CMOS process technology scales down into the nanometer scale, which causes the leakage currents on the bit‐lines. The bit‐line leakage current slows reading operations or even causes reading errors. In this paper, we proposed a new scheme called RTB, which is combined with a four‐input low‐offset sense amplifier with threshold voltage consideration to solve the problem caused by bit‐line leakage current. This scheme adopts 8T cells and two pairs of bit‐lines connected to a four‐input sense amplifier to balance the bit‐line leakage current in real‐time. In this way, the maximum tolerable bit‐line leakage current can be effectively increased and the reading operation can be accelerated. Simulations in the 55 nm CMOS process design kits under different process corners, temperatures, and voltages show that the proposed scheme can increase the maximum tolerable leakage to more than 300 μA.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：