The key characteristics of a DC‐DC converter for a fuel cell (FC) application include higher voltage gain for DC‐link voltage, the continuous and ripple‐free source current that is beneficial for FC. This paper proposes a high‐gain DC‐DC converter with continuous and ripple‐free input current. The proposed converter is suitable for integrating fuel cell and photovoltaic (PV) power into an isolated DC microgrid. Modified boost converter with an intermediate capacitor integrated with the cuk converter to achieve high voltage gain and low voltage stress across switches, which also reduces the reverse recovery problem of diodes. A prototype of a 1 kW converter is designed, developed, and analyzed to verify its working principle. The simulation and experimental results for high gain 40/400 V and 1 kW load power, with a DC microgrid of 400 V connected to the proposed converter, are in good harmony and are conforming to the theoretical analysis. The maximum obtained converter efficiency is 96.13%.
{"title":"High gain bipolar converter with reduced input current ripple for fuel cell integrated DC microgrid","authors":"Ashish Prajapati, Kalpana Chaudhary","doi":"10.1002/cta.4174","DOIUrl":"https://doi.org/10.1002/cta.4174","url":null,"abstract":"The key characteristics of a DC‐DC converter for a fuel cell (FC) application include higher voltage gain for DC‐link voltage, the continuous and ripple‐free source current that is beneficial for FC. This paper proposes a high‐gain DC‐DC converter with continuous and ripple‐free input current. The proposed converter is suitable for integrating fuel cell and photovoltaic (PV) power into an isolated DC microgrid. Modified boost converter with an intermediate capacitor integrated with the cuk converter to achieve high voltage gain and low voltage stress across switches, which also reduces the reverse recovery problem of diodes. A prototype of a 1 kW converter is designed, developed, and analyzed to verify its working principle. The simulation and experimental results for high gain 40/400 V and 1 kW load power, with a DC microgrid of 400 V connected to the proposed converter, are in good harmony and are conforming to the theoretical analysis. The maximum obtained converter efficiency is 96.13%.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141737416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper introduces a modified continuous mode class‐GF power amplifier (PA) incorporating a phase shift parameter to modify the drain voltage waveform. This modification significantly boosts the overlap area between the fundamental impedance and the second harmonic impedance, thereby providing increased flexibility in designing a broadband matching network. Additionally, a straightforward modified coupler network is proposed to effectively accommodate the expanded impedance design space. Experimental validation was conducted with a PA operating within the frequency range of 0.5–3.5 GHz. The results affirm the efficacy of the proposed approach, with the saturated output power ranging from 40.0 to 42.5 dBm, accompanied by a gain exceeding 10 dB. Furthermore, a remarkable drain efficiency ranging from 59% to 76.2% is achieved within the targeted frequency band.
{"title":"Design of a multi‐octave high‐efficiency power amplifier employing a modified continuous class‐GF mode","authors":"Haipeng Zhu, Zhiwei Zhang, Xuefei Xuan, Chenlu Wang, Luyu Zhang, Chao Gu","doi":"10.1002/cta.4194","DOIUrl":"https://doi.org/10.1002/cta.4194","url":null,"abstract":"This paper introduces a modified continuous mode class‐GF power amplifier (PA) incorporating a phase shift parameter to modify the drain voltage waveform. This modification significantly boosts the overlap area between the fundamental impedance and the second harmonic impedance, thereby providing increased flexibility in designing a broadband matching network. Additionally, a straightforward modified coupler network is proposed to effectively accommodate the expanded impedance design space. Experimental validation was conducted with a PA operating within the frequency range of 0.5–3.5 GHz. The results affirm the efficacy of the proposed approach, with the saturated output power ranging from 40.0 to 42.5 dBm, accompanied by a gain exceeding 10 dB. Furthermore, a remarkable drain efficiency ranging from 59% to 76.2% is achieved within the targeted frequency band.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141737420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The conventional automatic battery equalizer is characterized by its low cost in batter management system. However, its effectiveness is limited by the absence of signal feedback, leading to inadequate self‐regulation and protection of the topology. In this paper, an equalizer with constant magnetizing current is proposed. By adjusting the duty cycle of the MOSFETs, the magnetizing current can be flexibly controlled, which greatly improves the equalization rate and safety. The topology has multiple modes such as cell to cell (C2C), cell to string (C2S), and string to string (S2S). A creative signal sampling method is designed to obtain the cell voltage and magnetizing current with few sensors. And a novel balancing strategy is proposed, which can achieve wonderful accuracy of equalization at any initial voltage distribution.
{"title":"A novel multimode constant magnetizing current battery equalizer with few sensors in electric vehicles","authors":"Runmin Zou, Wenqi Zhou, Ji Wang","doi":"10.1002/cta.4165","DOIUrl":"https://doi.org/10.1002/cta.4165","url":null,"abstract":"The conventional automatic battery equalizer is characterized by its low cost in batter management system. However, its effectiveness is limited by the absence of signal feedback, leading to inadequate self‐regulation and protection of the topology. In this paper, an equalizer with constant magnetizing current is proposed. By adjusting the duty cycle of the MOSFETs, the magnetizing current can be flexibly controlled, which greatly improves the equalization rate and safety. The topology has multiple modes such as cell to cell (C2C), cell to string (C2S), and string to string (S2S). A creative signal sampling method is designed to obtain the cell voltage and magnetizing current with few sensors. And a novel balancing strategy is proposed, which can achieve wonderful accuracy of equalization at any initial voltage distribution.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141737418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article proposes two different structures of fractional‐order modified synchronous reference frame phase‐locked loop (MSRF PLL) and discusses their performance under different grid abnormalities. Phase‐locked loop (PLL) is a type of closed‐loop feedback control system that ensures phase and frequency coherence between its input and output signals. The basic synchronous reference frame phase‐locked loop (SRF‐PLL) is a conventional synchronization technique that is frequently employed in grid‐connected systems for power electronic converters. The SRF‐PLL offers rapid and precise phase/frequency detection under ideal grid environments. However, its performance is severely hampered under unbalanced and distorted grid environments. This paper discusses two new configurations of fractional‐order (FO) modified SRF (MSRF), one with fractional order only in additional low‐pass filter of first order (FO‐LP) and another fractional order in both first‐order low‐pass filter and PI (FO‐LPFO‐PI) of MSRF. These controllers are assembled using FOs “a” and “b” with limits as 0 < a < 2 and 0 < b < 2. The performance analysis of proposed FO MSRFs is done under grid abnormalities like voltage sag and swell, polluted grid supply, frequency change, phase change, and variables for dc offset. The outcomes of simulation are acquired using FO modeling and control (FOMCON) toolbox for MATLAB/SIMULINK, and the experimental results are validated with simulation results. A fair comparison among the MSRF‐PLL, FO‐LP MSRF‐PLL, and FO‐LPFO‐PI MSRF‐PLL is also depicted during grid abnormalities.
{"title":"Performance analysis of fractional‐order modified SRF PLL under grid abnormalities","authors":"Oinam Lotika Devi, Alka Singh","doi":"10.1002/cta.4161","DOIUrl":"https://doi.org/10.1002/cta.4161","url":null,"abstract":"This article proposes two different structures of fractional‐order modified synchronous reference frame phase‐locked loop (MSRF PLL) and discusses their performance under different grid abnormalities. Phase‐locked loop (PLL) is a type of closed‐loop feedback control system that ensures phase and frequency coherence between its input and output signals. The basic synchronous reference frame phase‐locked loop (SRF‐PLL) is a conventional synchronization technique that is frequently employed in grid‐connected systems for power electronic converters. The SRF‐PLL offers rapid and precise phase/frequency detection under ideal grid environments. However, its performance is severely hampered under unbalanced and distorted grid environments. This paper discusses two new configurations of fractional‐order (FO) modified SRF (MSRF), one with fractional order only in additional low‐pass filter of first order (FO‐LP) and another fractional order in both first‐order low‐pass filter and PI (FO‐LPFO‐PI) of MSRF. These controllers are assembled using FOs “<jats:italic>a</jats:italic>” and “<jats:italic>b</jats:italic>” with limits as 0 < <jats:italic>a</jats:italic> < 2 and 0 < <jats:italic>b</jats:italic> < 2. The performance analysis of proposed FO MSRFs is done under grid abnormalities like voltage sag and swell, polluted grid supply, frequency change, phase change, and variables for dc offset. The outcomes of simulation are acquired using FO modeling and control (FOMCON) toolbox for MATLAB/SIMULINK, and the experimental results are validated with simulation results. A fair comparison among the MSRF‐PLL, FO‐LP MSRF‐PLL, and FO‐LPFO‐PI MSRF‐PLL is also depicted during grid abnormalities.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141737417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The CLLLC resonant converter is a promising technology for electric vehicles and microgrids due to its ability to operate bidirectionally. This article presents a design of a bidirectional CLLLC resonant converter that is applied in the vehicle‐to‐grid (V2G). The battery side of the converter uses a two‐channel parallel structure to enhance its efficiency and reliability. In contrast, the DC‐bus side uses a transformer series structure to obtain the benefits of passive current sharing on the secondary side and reduce the transformer turns ratio. By utilizing the proposed design method, the converter can achieve a wide input and output voltage range, high efficiency, and high power density. The article analyzes the working principle of the converter and explains the design process, which includes the transformer turns ratio, magnetizing inductance, and resonance parameters. Finally, an experimental prototype is produced to verify the theory's validity and the design's feasibility. The prototype has a DC‐bus side voltage of 660–860 V, a battery side voltage of 250–500 V, and a maximum power output of 30 kW. The peak efficiency of the prototype is 98.2%, and its power density can reach up to 8 kW/L.
{"title":"Design and optimization of 30 kW CLLLC resonant converter for vehicle‐to‐grid applications","authors":"Donghao Tian, Yu Tang, Zhe Shi","doi":"10.1002/cta.4181","DOIUrl":"https://doi.org/10.1002/cta.4181","url":null,"abstract":"The CLLLC resonant converter is a promising technology for electric vehicles and microgrids due to its ability to operate bidirectionally. This article presents a design of a bidirectional CLLLC resonant converter that is applied in the vehicle‐to‐grid (V2G). The battery side of the converter uses a two‐channel parallel structure to enhance its efficiency and reliability. In contrast, the DC‐bus side uses a transformer series structure to obtain the benefits of passive current sharing on the secondary side and reduce the transformer turns ratio. By utilizing the proposed design method, the converter can achieve a wide input and output voltage range, high efficiency, and high power density. The article analyzes the working principle of the converter and explains the design process, which includes the transformer turns ratio, magnetizing inductance, and resonance parameters. Finally, an experimental prototype is produced to verify the theory's validity and the design's feasibility. The prototype has a DC‐bus side voltage of 660–860 V, a battery side voltage of 250–500 V, and a maximum power output of 30 kW. The peak efficiency of the prototype is 98.2<jats:italic>%</jats:italic>, and its power density can reach up to 8 kW/L.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141737419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Injection‐locked dividers feature ultrahigh operating frequency, low power consumption, and low phase noise, making them suitable for Q‐band phase‐locked loop. This paper presents a transformer‐based divide‐by‐4 injection locking frequency divider with a high third harmonic rejection buffer based on 40‐nm CMOS technology. Employing a fourth‐order transformer resonator enhances the third‐order harmonic amplitude, increasing the injection efficiency and expanding the locking range. The proposed high third harmonic rejection buffer using a source degeneration inductor can effectively suppress the output of the third harmonic caused by the resonator, ultimately yielding a clean fundamental frequency signal. Simulation results demonstrate that the proposed divide‐by‐4 injection‐locked frequency divider (ILFD) achieves a locking range of 10.2 GHz (from 40.3 to 50.5 GHz) with 0 dBm input signal. The core divide‐by‐4 ILFD circuit consumes 4.6 mW power with a 0.9 V supply and occupies an area of 0.026 mm2.
{"title":"A 40.3–50.5 GHz locking range transformer‐based injection‐locked frequency divider utilizing a high third harmonic rejection buffer","authors":"Xinsheng Wang, Yanhong Song, Xiyue Wang","doi":"10.1002/cta.4189","DOIUrl":"https://doi.org/10.1002/cta.4189","url":null,"abstract":"Injection‐locked dividers feature ultrahigh operating frequency, low power consumption, and low phase noise, making them suitable for Q‐band phase‐locked loop. This paper presents a transformer‐based divide‐by‐4 injection locking frequency divider with a high third harmonic rejection buffer based on 40‐nm CMOS technology. Employing a fourth‐order transformer resonator enhances the third‐order harmonic amplitude, increasing the injection efficiency and expanding the locking range. The proposed high third harmonic rejection buffer using a source degeneration inductor can effectively suppress the output of the third harmonic caused by the resonator, ultimately yielding a clean fundamental frequency signal. Simulation results demonstrate that the proposed divide‐by‐4 injection‐locked frequency divider (ILFD) achieves a locking range of 10.2 GHz (from 40.3 to 50.5 GHz) with 0 dBm input signal. The core divide‐by‐4 ILFD circuit consumes 4.6 mW power with a 0.9 V supply and occupies an area of 0.026 mm2.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":1.8,"publicationDate":"2024-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141646104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper carries out the research on a novel two‐level voltage source inverter to further improve the output power quality of the inverter under the premise of efficient operation. Main switches can realize zero‐voltage switching in a wide load range to ensure the efficient operation of the designed inverter. Total harmonic distortion (THD) of the output current at low output frequencies can be improved by the modification of resonant tanks in the designed inverter. In the dead time, the modified resonant tanks can result in a shorter duration of nonlinear changes in the output phase voltage at lower load current, which is beneficial for reducing the output voltage error caused by dead time. The improved power quality at low output frequencies is conductive to the use of the designed inverter in the drive system of the low‐speed AC motor. The paper expounds every operating status during a switching period. The experiment manifests that switches realize soft switching. The efficiency of the designed inverter reaches 98.6% at rated operation state, which is 0.3% and 0.5% more than that of two comparison objects, respectively. Moreover, when the output frequency reduces to 5 Hz, the THD of the output current is only 2%, which is also less than that of comparison objects. Hence, the designed inverter has advantages in the efficiency and the output power quality.
{"title":"An efficient three‐phase two‐level voltage source inverter with the suppression of the dead time effect","authors":"Qiang Wang, Xiang Gong, Youzheng Wang","doi":"10.1002/cta.4180","DOIUrl":"https://doi.org/10.1002/cta.4180","url":null,"abstract":"The paper carries out the research on a novel two‐level voltage source inverter to further improve the output power quality of the inverter under the premise of efficient operation. Main switches can realize zero‐voltage switching in a wide load range to ensure the efficient operation of the designed inverter. Total harmonic distortion (THD) of the output current at low output frequencies can be improved by the modification of resonant tanks in the designed inverter. In the dead time, the modified resonant tanks can result in a shorter duration of nonlinear changes in the output phase voltage at lower load current, which is beneficial for reducing the output voltage error caused by dead time. The improved power quality at low output frequencies is conductive to the use of the designed inverter in the drive system of the low‐speed AC motor. The paper expounds every operating status during a switching period. The experiment manifests that switches realize soft switching. The efficiency of the designed inverter reaches 98.6% at rated operation state, which is 0.3% and 0.5% more than that of two comparison objects, respectively. Moreover, when the output frequency reduces to 5 Hz, the THD of the output current is only 2%, which is also less than that of comparison objects. Hence, the designed inverter has advantages in the efficiency and the output power quality.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141610813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mahdi Alijani, Mohammadmahdi Javanmardi, Adib Abrishamifar
A differential ring voltage‐controlled oscillator (DRVCO) is proposed in this paper as one of the critical blocks in communication systems. It consists of four stages of delay cells connected in a chain, creating a ring structure with auxiliary path interconnections. The oscillation frequency of the DRVCO can be controlled by adjusting the tuning voltage that controls the charging current. To achieve the desired performance for wireless applications, the Wu active inductor, which is a low‐noise and high‐quality factor active inductor, is employed in each delay cell for the first time. Using an active inductor provides a wide tuning range and also allows for proper phase noise and low power consumption. The proposed circuit is designed and simulated using standard 180‐nm CMOS technology with a 1.8‐V voltage source (VDD). The circuit is designed to achieve a tuning range of 2.15 GHz with a center frequency oscillation of 2.745 GHz, over the control voltage variation of 1.4 V (0 to 1.4 V). To achieve the desired performance, the circuit consumes an average power of 1.99 mW. It achieves a phase noise of − 91.2 dBc/Hz at 1 MHz offset frequency, indicating effective noise suppression. The figure of merit (FoM) for the circuit is − 156.9 dBc/Hz, representing its overall performance. The final layout of the circuit estimates an area of 0.00072 mm2. Various analyses, including Monte–Carlo simulations, PVT (process, voltage, temperature) variation analysis, and other relevant analyses, have been performed to ensure the reliable performance of the proposed circuit.
{"title":"A wide tuning range CMOS differential ring VCO using an active inductor for wireless applications","authors":"Mahdi Alijani, Mohammadmahdi Javanmardi, Adib Abrishamifar","doi":"10.1002/cta.4155","DOIUrl":"https://doi.org/10.1002/cta.4155","url":null,"abstract":"A differential ring voltage‐controlled oscillator (DRVCO) is proposed in this paper as one of the critical blocks in communication systems. It consists of four stages of delay cells connected in a chain, creating a ring structure with auxiliary path interconnections. The oscillation frequency of the DRVCO can be controlled by adjusting the tuning voltage that controls the charging current. To achieve the desired performance for wireless applications, the Wu active inductor, which is a low‐noise and high‐quality factor active inductor, is employed in each delay cell for the first time. Using an active inductor provides a wide tuning range and also allows for proper phase noise and low power consumption. The proposed circuit is designed and simulated using standard 180‐nm CMOS technology with a 1.8‐V voltage source (<jats:italic>V</jats:italic><jats:sub>DD</jats:sub>). The circuit is designed to achieve a tuning range of 2.15 GHz with a center frequency oscillation of 2.745 GHz, over the control voltage variation of 1.4 V (0 to 1.4 V). To achieve the desired performance, the circuit consumes an average power of 1.99 mW. It achieves a phase noise of − 91.2 dBc/Hz at 1 MHz offset frequency, indicating effective noise suppression. The figure of merit (FoM) for the circuit is − 156.9 dBc/Hz, representing its overall performance. The final layout of the circuit estimates an area of 0.00072 mm<jats:sup>2</jats:sup>. Various analyses, including Monte–Carlo simulations, PVT (process, voltage, temperature) variation analysis, and other relevant analyses, have been performed to ensure the reliable performance of the proposed circuit.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141610812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hanbing Dan, Yuqian Chao, Zixi Liu, Xueqing Liu, Qi Zhu, Mei Su
This paper proposes a dual‐frequency three‐dimensional wireless power transfer system, which can achieve dual channel independent maximum power transfer of two movable receivers. Based on the dual‐frequency compensation network, a dual‐frequency magnetic field orientation strategy and a current control strategy are developed. Accordingly, the mathematical model of the proposed system is established, providing the theoretical support for mutual non‐interference of the power transfer between the two power transfer channels with different frequencies. On this basis, an iterative optimization control system is designed for independent maximum power transfer for two power transfer channels without any interference. A 200‐W experimental prototype with an efficiency of around 80% is built to verify the correctness of the proposed system. In the case of load position change, the response time of the proposed system is around 200 ms.
{"title":"Dual‐frequency three‐dimensional wireless power transfer system to achieve two‐channel independent maximum power transfer","authors":"Hanbing Dan, Yuqian Chao, Zixi Liu, Xueqing Liu, Qi Zhu, Mei Su","doi":"10.1002/cta.4172","DOIUrl":"https://doi.org/10.1002/cta.4172","url":null,"abstract":"This paper proposes a dual‐frequency three‐dimensional wireless power transfer system, which can achieve dual channel independent maximum power transfer of two movable receivers. Based on the dual‐frequency compensation network, a dual‐frequency magnetic field orientation strategy and a current control strategy are developed. Accordingly, the mathematical model of the proposed system is established, providing the theoretical support for mutual non‐interference of the power transfer between the two power transfer channels with different frequencies. On this basis, an iterative optimization control system is designed for independent maximum power transfer for two power transfer channels without any interference. A 200‐W experimental prototype with an efficiency of around 80% is built to verify the correctness of the proposed system. In the case of load position change, the response time of the proposed system is around 200 ms.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141610818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Experimental advanced superconducting tokamak (EAST) fast control power supply (FCPS) is an essential device to realize balance control of plasma vertical displacement during controllable nuclear fusion process. The primary control purpose of EAST FCPS is to quickly output current to track reference current. Change of load inductance parameters due to plasma motion poses higher robustness requirements for fast tracking control of output current. Therefore, an improved gray prediction parameter identification sliding mode control method is proposed to achieve fast tracking and robust control of output current under changes in load inductance parameters. Parameter identification sliding mode control method applied to identify load inductance parameters in real‐time, accurate EAST FCPS output current tracking sliding mode control model is established. High‐order terms are added to discrete exponential convergence reaching law, and a new smooth saturation function is designed to replace traditional sign function to achieve chattering suppression and accelerate system convergence speed. Gray prediction used in current sampling to achieve output current trajectory advanced prediction to further accelerate output current response speed. Four times equal interval time sampling within a fixed switching period and new information priority period by period prediction is proposed to improving gray prediction, achieving digital control delay compensation, and improving prediction accuracy of output current trajectory at abrupt edge. Simulation and experimental verification show that the proposed improved gray prediction parameter identification sliding mode control method has good output current tracking control performance under changes in load parameters. Compared with PI control method currently used in engineering, the proposed control method performs better in output current fast response and overshoot suppression.
先进超导托卡马克实验装置（EAST）快速控制电源（FCPS）是在可控核聚变过程中实现等离子体垂直位移平衡控制的重要装置。EAST FCPS 的主要控制目的是快速输出电流以跟踪参考电流。等离子体运动导致的负载电感参数变化对输出电流的快速跟踪控制提出了更高的鲁棒性要求。因此，提出了一种改进的灰色预测参数识别滑模控制方法，以实现负载电感参数变化时输出电流的快速跟踪和鲁棒控制。应用参数识别滑模控制方法实时识别负载电感参数，建立精确的 EAST FCPS 输出电流跟踪滑模控制模型。在离散指数收敛达成律中加入了高阶项，并设计了新的平滑饱和函数来取代传统的符号函数，以实现颤振抑制并加快系统收敛速度。电流采样采用灰色预测，实现输出电流轨迹高级预测，进一步加快输出电流响应速度。提出在固定开关周期内进行四次等间隔时间采样，并逐期预测新的信息优先级，以改进灰色预测，实现数字控制延迟补偿，提高突变边缘输出电流轨迹的预测精度。仿真和实验验证表明，改进的灰色预测参数识别滑模控制方法在负载参数变化时具有良好的输出电流跟踪控制性能。与目前工程中使用的 PI 控制方法相比，所提出的控制方法在输出电流快速响应和过冲抑制方面表现更好。
{"title":"Improved gray prediction parameter identification sliding mode current control of experimental advanced superconducting tokamak fast control power supply","authors":"Zhao Chen, Haihong Huang, Haixin Wang","doi":"10.1002/cta.4183","DOIUrl":"https://doi.org/10.1002/cta.4183","url":null,"abstract":"Experimental advanced superconducting tokamak (EAST) fast control power supply (FCPS) is an essential device to realize balance control of plasma vertical displacement during controllable nuclear fusion process. The primary control purpose of EAST FCPS is to quickly output current to track reference current. Change of load inductance parameters due to plasma motion poses higher robustness requirements for fast tracking control of output current. Therefore, an improved gray prediction parameter identification sliding mode control method is proposed to achieve fast tracking and robust control of output current under changes in load inductance parameters. Parameter identification sliding mode control method applied to identify load inductance parameters in real‐time, accurate EAST FCPS output current tracking sliding mode control model is established. High‐order terms are added to discrete exponential convergence reaching law, and a new smooth saturation function is designed to replace traditional sign function to achieve chattering suppression and accelerate system convergence speed. Gray prediction used in current sampling to achieve output current trajectory advanced prediction to further accelerate output current response speed. Four times equal interval time sampling within a fixed switching period and new information priority period by period prediction is proposed to improving gray prediction, achieving digital control delay compensation, and improving prediction accuracy of output current trajectory at abrupt edge. Simulation and experimental verification show that the proposed improved gray prediction parameter identification sliding mode control method has good output current tracking control performance under changes in load parameters. Compared with PI control method currently used in engineering, the proposed control method performs better in output current fast response and overshoot suppression.","PeriodicalId":13874,"journal":{"name":"International Journal of Circuit Theory and Applications","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141610814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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