International Journal of Circuit Theory and Applications最新文献

This paper presents a detailed study of a three-phase photovoltaic pumping system (PVPS), comprising a 1.5-kW three-phase induction motor for water pumping, a three-phase voltage source inverter (VSI), and a DC-DC boost converter designed to maximize power extraction from a 1.88-kWp photovoltaic generator (PVG). The system is characterized by its cost-effectiveness, high efficiency, and robust performance. To reduce overall system costs, the inductor current of the boost converter and the rotational speed of the induction motor are estimated rather than measured directly. A nonlinear neural network observer (NNO) is employed to estimate the inductor current, whereas a sliding mode observer (SMO) is utilized to estimate the motor speed. To enhance the system's resilience against internal and external disturbances, a hybrid incremental conductance super-twisting sliding mode controller (InC-STSMC) is implemented for maximum power point tracking (MPPT) from the PVG, and a flux-oriented sliding mode vector control (FO-SMC) is adopted for precise regulation of the motor speed. The effectiveness of the proposed control strategy is evaluated through model-in-the-loop (MIL) simulations conducted in the MATLAB-Simulink environment, demonstrating significant improvements in dynamic performance, particularly in terms of stability and robustness, compared to conventional proportional-integral (PI) control methods. The practicality and suitability of the proposed InC-STSMC combined with the NNO scheme are further validated through a processor-in-the-loop (PIL) test using the STM32F769I board, highlighting its potential for real-world applications.

In the process of designing a DC–DC converter, if the topology is determined first and then the corresponding voltage gain expression is derived based on the volt-second balance principle, this design process is referred to as forward design. In contrast, the reverse design method synthesizes DC–DC converters based on the volt-second balance principle, using the desired voltage gain expression as the condition. This method realizes the demand-oriented converter design, transforming the topology synthesis problem into a mathematical problem of solving the volt-second balance equations. This paper takes the design of a second-order converter as an example, presents a specific method for solving the mathematical problem and details the four steps of the proposed reverse design method. Based on the proposed method, a total of 13 topologies (T1–T13) were derived, of which 11 (T1–T11) meet the design requirements. To identify the optimal topology, these 11 topologies were compared, and topology T9 with superior performance was thoroughly analyzed along with its parameter design methodology. Finally, simulations were conducted on all 13 topologies, and a 100 W experimental prototype of topology T9 was built for experimental validation. The simulation and experimental results demonstrate the effectiveness of the proposed method.

This paper presents a photon transfer curve-supported switching-energy reduction technique for the SAR ADCs used in CMOS image sensor readouts. Here, the energy consumptions of the capacitive DAC and the SAR logic are minimized using selective capacitance reduction supported by PTC-inspired bit-depth compression. When our proposed method is combined with the $�{�V�}_{�\text{CM}�}$-based switching energy reduction technique, the peak and average energy consumptions of the DAC are reduced by 91.28% and 93.99%, respectively, compared to the conventional binary-weighted capacitive DACs for a 10-bit effective resolution. Compared to conventional $�{�V�}_{�\text{CM}�}$-based DACs, our proposed $�{�V�}_{�\text{CM}�}$-based DACs consume 51.86% less energy. Besides decreasing the DAC switching energy, our proposed technique ensures 51% reduction in the energy consumption of the SAR logic compared to conventional $�{�V�}_{�\text{CM}�}$-based switching due to the reduction in the number of clock cycles needed for the data conversion and its associated switching. Similarly, our proposed approach with monotonic switching scheme results in 25% reduction in the energy consumption of a 10-bit DAC following monotonic switching.

This paper demonstrates the co-design of class-F⁻¹ microwave amplifier (MA) and bandpass filtering (BPF) matching network (MN) with harmonics control functionality (HCF). The proposed BPF MN can match arbitrary termination impedances (ATIs) to 50 Ω at fundamental frequency (f₀) and simultaneously control the second harmonic (2f₀) and third harmonic (3f₀) impedances to be open- and short-circuited, respectively. The BPF MN with HCF is realized with the alternative J/K inverters cascaded via quarter wavelength (λ/4) transmission line resonators and the additional shunt-series LC resonators, which produces the resonances at harmonic frequencies. In the realization process, the circuit is implemented using microstrip lines and applied as the output MN (OMN) of the proposed class-F⁻¹ MA. To validate the proposed design method, three class-F⁻¹ MAs with different OMNs are designed with f₀ of 6 GHz using CGHV1F006S GaN HEMT. With the same input power (P_in) level, the output power (P_out) and drain efficiency of the proposed class-F⁻¹ MA with BPF OMN are better than those of the conventional class-F⁻¹ MA (CMA) cascaded with conventional BPF (CBPF) about 0.42 dB and 5.1%, respectively. Moreover, the circuit size is reduced by about 35.68%.

Hybrid conduction mode (HCM) control with a single freewheel phase is applied to reduce switching loss and minimize cross-regulation in single-inductor dual-output (SIDO) dc–dc converter. However, the cross-regulation still exists when the load-step occurs, especially when the freewheel current is instantaneously adjusted based on load conditions. To explore the deep effect of the freewheel current in constant freewheel (CF)/dynamic freewheel (DF) control, the comparison analysis of cross-regulation is presented in this paper. The small-signal models of the HCM SIDO buck converter with CF/DF control are established, and the characteristics of closed-loop cross-regulation and load transient under different load current coefficients for freewheel current are discussed. The simulation results and the experimental results show that compared with the CF control, the transient performance of the output branch is significantly improved at different gain coefficients when the DF control is adopted. When k_a = 1 and k_b = 0, the cross-regulation of the CCM branch on the PCCM branch can decrease from 19.17% to 4.17%, while retaining the zero cross-regulation of the PCCM branch on the CCM branch.

Secondary distributed control in microgrids is susceptible to false data injection attacks (FDIAs), which attackers can leverage to manipulate the original transmitting frequencies. These manipulations can cause the frequencies to deviate from their expected range or be assigned excessively large data, potentially bringing the system to a halt. In order to tackle this issue, this paper proposes a novel attack buffer method that first significantly reduces the impact of stronger interference. It also efficiently handles limited smaller injections within a generalized scope, enabling the system to function within a controllable range. Furthermore, a straightforward error elimination control loop is designed to manage the persistent deviation caused by the lessened FDIA. The proposed method eliminates the need for observer design and complex control parameter tuning. The proposed method can resist unlimited ramp FDIA. Additionally, it exhibits rapid convergence and smaller transient offsets during load changes. In the event of a transmission fault, the system's stability and performance are maintained. This paper also considers multiple FDIA scenarios to thoroughly validate the practicality of the proposed method. The voltage waveforms and quality analysis are also presented to verify the effectiveness of the proposed method. Finally, its effectiveness is further verified through simulation and FPGA-in-the-loop testing.

The memtranstor is a memory element that establishes a direct relationship between charge and magnetic flux through nonlinear magnetic effects and is classified as the fourth memory element after the memristor, memcapacitor, and meminductor. This paper discusses the design of a floating emulator integrating a newly introduced memory element called memtranstor. The proposed memtranstor circuit employs four differential voltage current conveyors (DVCCs), one analog multiplier, three grounded capacitors, and four grounded resistors. The PSPICE simulation results are done using the 0.18-μm CMOS technology parameter to confirm the functionality of the suggested floating emulator circuit. By altering the parameters in the models, a variety of simulations are done including memory effect simulations, Monte Carlo simulations, pinched hysteresis loops using various DC control voltages and frequencies, temperature variation, and output voltage noise simulations. To demonstrate the potential applications of the proposed memtranstor, its artificial synaptic plasticity and its role in a memtranstor-based chaotic oscillator are validated through example simulations.

Multistability emerges in mutually synchronized oscillator systems. In the case of two reactively coupled oscillators, multiple coexisting modes appear, each exhibiting a different self-sustained oscillation phase difference. Since these modes correspond to distinct oscillation frequencies, injection locking with an external signal, whose frequency falls within the system's bandwidth, is theoretically possible, with each mode having a finite lock range. If the amplitude of the external signal is sufficiently large, the lock ranges of different modes can overlap, effectively expanding the overall lock range. In this study, we consider a mutually synchronized system consisting of identically structured tunnel diode oscillators coupled via capacitive elements. We perform a bifurcation analysis of an injection locking system where each oscillator receives an external signal with individually controlled phase. Our results reveal that when the phase difference of the external signals is set to zero, only the in-phase synchronization mode exhibits a finite lock range, while setting it to $�\pi$ results in a finite lock range for the anti-phase mode alone. Furthermore, by optimizing the phase difference of the external signals, the lock ranges of both modes can be overlapped, thereby achieving broadband synchronization.

The true random number generator (TRNG), as the fundamental component of an information security system, is a cryptographic primitive essential for generating keys, random numbers, initialization vectors, and more. With the advancement of lightweight applications and high-speed communication, solving the problem of high resource overhead and low throughput of TRNG becomes increasingly important. To overcome the limitations in terms of resource overhead and throughput posed by traditional single-entropy source TRNG, this paper proposes a hybrid entropy source TRNG based on FPGA. This architecture combines the jitter from a ring oscillator (RO) with metastability triggered by the XOR gate to enhance the entropy generation capability of TRNG. Experimental results demonstrate that this proposed structure can be implemented and tested on multiple FPGAs without manual placement and complex postprocessing circuits. It achieves a minimum throughput of 300 Mbps with the minimum entropy greater than 0.996 while only utilizing 19 lookup tables (LUTs) and 4 D-flip-flops (DFFs) as resource overhead.

The three-phase inverter is a crucial power conversion device in renewable energy generation systems, but its output current contains numerous harmonics. These harmonics necessitate the use of harmonic filters to meet grid connection standards. Compared to L or LC filters, the LCL filter is widely used as a third-order filter due to its higher noise attenuation rate. However, the LCL filter's multiple inductors result in a larger volume and weight, which hinders the improvement of the system's power density. Magnetic integration technology effectively reduces the filter's volume and weight, but the coupling between inductors can impact the high-frequency noise attenuation ability. This article proposes a planar magnetic integration scheme that achieves decoupling of inverter side and grid side inductors, with a low coupling coefficient between both inverter side inductors and grid side inductors. Compared to traditional filters, the proposed magnetic integrated LCL filter is lighter and more compact, thereby enhancing system power density. The harmonic suppression effect of the designed magnetic integrated LCL filter is validated through simulations and experiments. Even under asymmetric load conditions, the proposed filter demonstrates good harmonic suppression performance.