Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646574
S. A. Wadekar, A. C. Parker, C. Ravikumar
We present a novel technique to predict energy and power consumption in an electronic system, given its behavioral specification and library components. The early prediction gives circuit designers the freedom to make numerous high-level choices (such as die size, package type, and latency of the pipeline) with confidence that the final implementation will meet power and energy as well as cost and performance constraints. Our unique statistical estimation technique associates low-level, technology dependent physical and electrical parameters with expected circuit resources and interconnect. Further correlations with switching activity yield accurate results consistent with implementations. All feasible designs are investigated using this technique and the designer may trade off between small size, high speed, low energy and low power. The results for designs of two popular signal processing applications, predicted prior to synthesis, are within 10% accuracy of power estimates performed on synthesized layouts.
{"title":"FREEDOM: statistical behavioral estimation of system energy and power","authors":"S. A. Wadekar, A. C. Parker, C. Ravikumar","doi":"10.1109/ICVD.1998.646574","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646574","url":null,"abstract":"We present a novel technique to predict energy and power consumption in an electronic system, given its behavioral specification and library components. The early prediction gives circuit designers the freedom to make numerous high-level choices (such as die size, package type, and latency of the pipeline) with confidence that the final implementation will meet power and energy as well as cost and performance constraints. Our unique statistical estimation technique associates low-level, technology dependent physical and electrical parameters with expected circuit resources and interconnect. Further correlations with switching activity yield accurate results consistent with implementations. All feasible designs are investigated using this technique and the designer may trade off between small size, high speed, low energy and low power. The results for designs of two popular signal processing applications, predicted prior to synthesis, are within 10% accuracy of power estimates performed on synthesized layouts.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124359308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646600
C. Ravikumar, S. Gupta, Akshay Jajoo
With several commercial tools becoming available, the high-level synthesis of application-specific integrated circuits is finding wide spread acceptance in VLSI industry today. Existing tools for synthesis focus on optimizing cost while meeting performance constraints or vice versa. Yet, verification and testing have emerged as major concerns of IC vendors since the repercussions of chips being recalled are far-reaching. In this paper, we concentrate on the synthesis of testable RTL designs using techniques from Artificial Intelligence. We present an adaptive version of the well known Simulated Annealing algorithm and describe its application to a combinatorial optimization problem arising in the high-level synthesis of digital systems. The conventional annealing algorithm was conceived with a single perturb operator which applies a small modification to the existing solution to derive a new solution. The Metropolis criterion is then used to accept or reject the new solution. In some of the complex optimization problems arising in VLSI design, a set of perturb functions become necessary, leading to the question of how to select a particular function for modifying the current system configuration. The adaptive algorithm described here uses the concept of reward and penalty from the theory of learning automata to "learn" to apply the appropriate perturb function. We have applied both the conventional simulated annealing algorithm and the adaptive simulated annealing algorithm to the problem of testability-oriented datapath synthesis for signal processing applications. Our experimental results indicate that the adaptive algorithm can yield better solutions in shorter time.
{"title":"Synthesis of testable RTL designs","authors":"C. Ravikumar, S. Gupta, Akshay Jajoo","doi":"10.1109/ICVD.1998.646600","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646600","url":null,"abstract":"With several commercial tools becoming available, the high-level synthesis of application-specific integrated circuits is finding wide spread acceptance in VLSI industry today. Existing tools for synthesis focus on optimizing cost while meeting performance constraints or vice versa. Yet, verification and testing have emerged as major concerns of IC vendors since the repercussions of chips being recalled are far-reaching. In this paper, we concentrate on the synthesis of testable RTL designs using techniques from Artificial Intelligence. We present an adaptive version of the well known Simulated Annealing algorithm and describe its application to a combinatorial optimization problem arising in the high-level synthesis of digital systems. The conventional annealing algorithm was conceived with a single perturb operator which applies a small modification to the existing solution to derive a new solution. The Metropolis criterion is then used to accept or reject the new solution. In some of the complex optimization problems arising in VLSI design, a set of perturb functions become necessary, leading to the question of how to select a particular function for modifying the current system configuration. The adaptive algorithm described here uses the concept of reward and penalty from the theory of learning automata to \"learn\" to apply the appropriate perturb function. We have applied both the conventional simulated annealing algorithm and the adaptive simulated annealing algorithm to the problem of testability-oriented datapath synthesis for signal processing applications. Our experimental results indicate that the adaptive algorithm can yield better solutions in shorter time.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116931694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646662
G. Swamy, S. Edwards, R. Brayton
In this paper we solve the problem of identifying a "matching" between two logic circuits or "networks". A matching is a functions that maps each gate or "node" in the new circuit into one in the old circuit (if a matching does not exist it maps it to null). We present both an exact and a heuristic way to solve the maximal matching problem. The matching problem does not require any input correspondences. The purpose is to identify structurally identical regions in the networks, and exploit the commonality between them for more efficient verification and synthesis. Synthesis and verification tools that recognize commonalities both between two versions of the same design, as well within a single design, may be able to outperform their counterparts that do not utilize these commonalities. This work is concerned with detecting structural "matchings" that may be re-utilized.
{"title":"Efficient verification and synthesis using design commonalities","authors":"G. Swamy, S. Edwards, R. Brayton","doi":"10.1109/ICVD.1998.646662","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646662","url":null,"abstract":"In this paper we solve the problem of identifying a \"matching\" between two logic circuits or \"networks\". A matching is a functions that maps each gate or \"node\" in the new circuit into one in the old circuit (if a matching does not exist it maps it to null). We present both an exact and a heuristic way to solve the maximal matching problem. The matching problem does not require any input correspondences. The purpose is to identify structurally identical regions in the networks, and exploit the commonality between them for more efficient verification and synthesis. Synthesis and verification tools that recognize commonalities both between two versions of the same design, as well within a single design, may be able to outperform their counterparts that do not utilize these commonalities. This work is concerned with detecting structural \"matchings\" that may be re-utilized.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"24 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128455404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646632
Johnny Öberg, A. Jantsch, Anshul Kumar
The increasing complexity of electronic systems has led to a core based design methodology where large, predesigned blocks can be reused and configured to compose huge systems with several million transistors on a single chip. In a core based methodology, the designer, or the tool, selects an appropriate core from a library and adapts it to the surrounding environment. However, a specific core configuration in a specific environment very often opens up the potential for performance and cost optimizations which today cannot be utilized due to the inflexibility of cores. In this paper we propose an object oriented concept for a library of cores, which not only contains design models of the cores but also rule based design transformations to optimize the core in the context of a specific configuration and a specific environment.
{"title":"An object-oriented concept for intelligent library functions","authors":"Johnny Öberg, A. Jantsch, Anshul Kumar","doi":"10.1109/ICVD.1998.646632","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646632","url":null,"abstract":"The increasing complexity of electronic systems has led to a core based design methodology where large, predesigned blocks can be reused and configured to compose huge systems with several million transistors on a single chip. In a core based methodology, the designer, or the tool, selects an appropriate core from a library and adapts it to the surrounding environment. However, a specific core configuration in a specific environment very often opens up the potential for performance and cost optimizations which today cannot be utilized due to the inflexibility of cores. In this paper we propose an object oriented concept for a library of cores, which not only contains design models of the cores but also rule based design transformations to optimize the core in the context of a specific configuration and a specific environment.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129574489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646648
D. Saha, A. Chandrakasan
Emerging "systems-on-a-chip" will require a design environment that allows distributed access to libraries, models and design tools. In this paper we present a framework using the Object-Web technologies to implement Web-based CAD. The framework includes the infrastructure to store and manipulate design objects, protocols for tool communication and WebTop, a Java hierarchical schematic/block editor with interfaces to distributed Web tools and cell libraries.
{"title":"Web-based distributed VLSI design","authors":"D. Saha, A. Chandrakasan","doi":"10.1109/ICVD.1998.646648","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646648","url":null,"abstract":"Emerging \"systems-on-a-chip\" will require a design environment that allows distributed access to libraries, models and design tools. In this paper we present a framework using the Object-Web technologies to implement Web-based CAD. The framework includes the infrastructure to store and manipulate design objects, protocols for tool communication and WebTop, a Java hierarchical schematic/block editor with interfaces to distributed Web tools and cell libraries.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129599502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646628
R. Pillai, D. Al-Khalili, A. Al-Khalili
In CMOS logic implementations, the architectural/algorithmic power/delay/area implications of functional units are crucial as far as design economies of the target application are concerned. This paper addresses the architectural design of a low power floating point accumulator by using a transition activity scaled triple data path floating point adder core. The proposed scheme offers a worst case power reduction of 50% in comparison to schemes that use conventional floating point adders. The reduction in power delay product is better than 3X.
{"title":"A low power floating point accumulator","authors":"R. Pillai, D. Al-Khalili, A. Al-Khalili","doi":"10.1109/ICVD.1998.646628","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646628","url":null,"abstract":"In CMOS logic implementations, the architectural/algorithmic power/delay/area implications of functional units are crucial as far as design economies of the target application are concerned. This paper addresses the architectural design of a low power floating point accumulator by using a transition activity scaled triple data path floating point adder core. The proposed scheme offers a worst case power reduction of 50% in comparison to schemes that use conventional floating point adders. The reduction in power delay product is better than 3X.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133603812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646603
D. K. Das, Indrajit Chaudhuri, B. Bhattacharya
A novel design of a test pattern generator (TPG) for built-in self-testing (BIST) of path delay faults, is proposed. For an n-input CUT, the TPG generates a sequence of length (n.2/sup n/+1), that includes all n.2/sup n/ single-input-change (SIC) test pairs, and hence optimal. The generation of such a sequence of minimum length (i.e., n.2/sup n/+1) was an open problem. A simple iterative circuit of the TPG is then constructed. This provides minimum test application time for testing path delay faults, and compares favorably with the earlier BIST designs.
{"title":"Design of an optimal test pattern generator for built-in self testing of path delay faults","authors":"D. K. Das, Indrajit Chaudhuri, B. Bhattacharya","doi":"10.1109/ICVD.1998.646603","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646603","url":null,"abstract":"A novel design of a test pattern generator (TPG) for built-in self-testing (BIST) of path delay faults, is proposed. For an n-input CUT, the TPG generates a sequence of length (n.2/sup n/+1), that includes all n.2/sup n/ single-input-change (SIC) test pairs, and hence optimal. The generation of such a sequence of minimum length (i.e., n.2/sup n/+1) was an open problem. A simple iterative circuit of the TPG is then constructed. This provides minimum test application time for testing path delay faults, and compares favorably with the earlier BIST designs.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133981245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646616
V. Rajesh, Ajai Jain
This paper discusses a new objective function to generate test patterns for sequential circuits using genetic algorithms. This approach is based on the importance of assigning a value (0 or 1) to a line with respect to faults in consideration. This is simulation based and can be used for any circuit that can be simulated logically.
{"title":"Automatic test pattern generation for sequential circuits using genetic algorithms","authors":"V. Rajesh, Ajai Jain","doi":"10.1109/ICVD.1998.646616","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646616","url":null,"abstract":"This paper discusses a new objective function to generate test patterns for sequential circuits using genetic algorithms. This approach is based on the importance of assigning a value (0 or 1) to a line with respect to faults in consideration. This is simulation based and can be used for any circuit that can be simulated logically.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133462026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646582
B. Svantesson, Shashi Kumar, A. Hemani
This paper discusses a methodology and algorithms for efficient hardware synthesis of inter-process communication in systems described in SDL. The basic idea of our approach is to implement an SDL process by two hardware blocks, namely Computation Block and Communication Block. The Computation Block implements the data computation functions of the process as an Extended FSM (EFSM). The Communication Block implements the communication of the process with other processes. We give an algorithm to classify the communication requirements of the process and have an efficient implementation for it. Our scheme also has a supervisor block for every SDL block to manage interprocess communication. Our methodology supports multiple instances of the processes and dynamic processes. In our scheme, a single copy of hardware (Compute block) is shared among multiple copies of a process within a block which leads to efficient hardware implementation.
{"title":"A methodology and algorithms for efficient interprocess communication synthesis from system description in SDL","authors":"B. Svantesson, Shashi Kumar, A. Hemani","doi":"10.1109/ICVD.1998.646582","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646582","url":null,"abstract":"This paper discusses a methodology and algorithms for efficient hardware synthesis of inter-process communication in systems described in SDL. The basic idea of our approach is to implement an SDL process by two hardware blocks, namely Computation Block and Communication Block. The Computation Block implements the data computation functions of the process as an Extended FSM (EFSM). The Communication Block implements the communication of the process with other processes. We give an algorithm to classify the communication requirements of the process and have an efficient implementation for it. Our scheme also has a supervisor block for every SDL block to manage interprocess communication. Our methodology supports multiple instances of the processes and dynamic processes. In our scheme, a single copy of hardware (Compute block) is shared among multiple copies of a process within a block which leads to efficient hardware implementation.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133676660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646604
Subhasish Subhasish, P. Banerjee, M. Sarrafzadeh
A popular approach to reduce power consumption is to identify self-loops in a state transition graph (STG) of a finite state machine (FSM) followed by gating the clock with a suitable function to power down the circuit (implementation of the FSM) during the self-loop cycles. Although this approach is effective in circuits with plenty of self-loops, it fails for FSMs without self-loops. Since self loops may not be inherently present in a given FSM, we decompose it into interacting FSMs such that they have plenty of self-loops. In this paper we present a novel partitioning algorithm to decompose a given finite state machine. By using this approach, we could save upto 71% of the total power on circuits like fetch, where other techniques could not save any power.
{"title":"Partitioning sequential circuits for low power","authors":"Subhasish Subhasish, P. Banerjee, M. Sarrafzadeh","doi":"10.1109/ICVD.1998.646604","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646604","url":null,"abstract":"A popular approach to reduce power consumption is to identify self-loops in a state transition graph (STG) of a finite state machine (FSM) followed by gating the clock with a suitable function to power down the circuit (implementation of the FSM) during the self-loop cycles. Although this approach is effective in circuits with plenty of self-loops, it fails for FSMs without self-loops. Since self loops may not be inherently present in a given FSM, we decompose it into interacting FSMs such that they have plenty of self-loops. In this paper we present a novel partitioning algorithm to decompose a given finite state machine. By using this approach, we could save upto 71% of the total power on circuits like fetch, where other techniques could not save any power.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124277202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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