Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646613
N. Dhanwada, R. Vemuri
In this paper we present a technique for constraint allocation in analog system synthesis. Constraint allocation is the process of assigning constraint budgets to the subsystems so that the user asserted system level constraints are satisfied. Our approach is based on the formulation of the constraint allocation problem as a constraint satisfaction problem (CSP) and solving it. The solution method employed uses interval techniques to check for the satisfiability of the CSP. The generation of the exact set of solutions is done by an interval reduction and instantiation mechanism. We also discuss the constraint allocation mechanism in the context of a mixed-signal synthesis system. Finally, we present a design example to validate the constraint allocation technique.
{"title":"Constraint allocation in analog system synthesis","authors":"N. Dhanwada, R. Vemuri","doi":"10.1109/ICVD.1998.646613","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646613","url":null,"abstract":"In this paper we present a technique for constraint allocation in analog system synthesis. Constraint allocation is the process of assigning constraint budgets to the subsystems so that the user asserted system level constraints are satisfied. Our approach is based on the formulation of the constraint allocation problem as a constraint satisfaction problem (CSP) and solving it. The solution method employed uses interval techniques to check for the satisfiability of the CSP. The generation of the exact set of solutions is done by an interval reduction and instantiation mechanism. We also discuss the constraint allocation mechanism in the context of a mixed-signal synthesis system. Finally, we present a design example to validate the constraint allocation technique.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"89 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131830421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646591
C. G. Hiremath, S. Jayasimha
A novel method exploits the time-reversal of mirror symmetric pairs of polyphase components of a linear-phase prototype filter to obtain more than 25% reduction in required MIPs to perform prototype windowing of either an analysis or synthesis cosine modulated filterbank on a suitable architecture. The architecture required to obtain this MIPs reduction is only a minor modification to many DSP architectures and is, in fact, available in the latest DSP designs. The proposed algorithm is particularly suited for large overlap factors, where the windowing computation dominates the required MIPs., one important example being the filterbank used in MPEG audio compression.
{"title":"Improving concurrency for cosine-modulated filterbank windowing","authors":"C. G. Hiremath, S. Jayasimha","doi":"10.1109/ICVD.1998.646591","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646591","url":null,"abstract":"A novel method exploits the time-reversal of mirror symmetric pairs of polyphase components of a linear-phase prototype filter to obtain more than 25% reduction in required MIPs to perform prototype windowing of either an analysis or synthesis cosine modulated filterbank on a suitable architecture. The architecture required to obtain this MIPs reduction is only a minor modification to many DSP architectures and is, in fact, available in the latest DSP designs. The proposed algorithm is particularly suited for large overlap factors, where the windowing computation dominates the required MIPs., one important example being the filterbank used in MPEG audio compression.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131011081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646589
A. Drolshagen, W. Anheier, C. Sekhar
This paper presents a new design for module multipliers suitable for moduli that are not necessarily prime. The design avoids the need for building special purpose look-up tables. An RNS arithmetic based autocorrelator circuit that uses a large number of these multipliers is designed. The paper also describes the automated design strategy using a hardware compiler for RNS, and presents the results of the synthesis.
{"title":"A residue number arithmetic based circuit for pipelined computation of autocorrelation coefficients of speech signal","authors":"A. Drolshagen, W. Anheier, C. Sekhar","doi":"10.1109/ICVD.1998.646589","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646589","url":null,"abstract":"This paper presents a new design for module multipliers suitable for moduli that are not necessarily prime. The design avoids the need for building special purpose look-up tables. An RNS arithmetic based autocorrelator circuit that uses a large number of these multipliers is designed. The paper also describes the automated design strategy using a hardware compiler for RNS, and presents the results of the synthesis.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124449498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646630
P. Roop, A. Sowmya
Component-based design is a well known engineering design method that uses prefabricated components with known properties to design larger systems. We propose a new language called CFSMcharts for component-based design of microprocessor based systems. In this domain, there exists a vast library of programmable devices, which may be used during design synthesis for cheap bulk production of these systems. However, the use of these components during design synthesis is still low-key. CFSMcharts will alleviate the above problem by encouraging the use of programmable components during design synthesis. The language is an extension of CFSMs proposed recently to model the behaviour of programmable components. We also propose a formal semantics of the above language based on the concept of Sequence Function Trees (SFTs).
{"title":"CFSMcharts: a new language for microprocessor based system design","authors":"P. Roop, A. Sowmya","doi":"10.1109/ICVD.1998.646630","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646630","url":null,"abstract":"Component-based design is a well known engineering design method that uses prefabricated components with known properties to design larger systems. We propose a new language called CFSMcharts for component-based design of microprocessor based systems. In this domain, there exists a vast library of programmable devices, which may be used during design synthesis for cheap bulk production of these systems. However, the use of these components during design synthesis is still low-key. CFSMcharts will alleviate the above problem by encouraging the use of programmable components during design synthesis. The language is an extension of CFSMs proposed recently to model the behaviour of programmable components. We also propose a formal semantics of the above language based on the concept of Sequence Function Trees (SFTs).","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121236751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646595
G. Cauwenberghs
The quality and stability of noise shaping is a concern in the design of higher-order delta-sigma modulators for high-resolution, high-speed oversampled analog-to-digital conversion. We reformulate noise-shaping modulation alternatively as a nonlinear optimal control problem, where the objective is to find the binary modulation sequence that minimizes signal swing in a cascade of integrators operating on the difference between the input signal and the modulation sequence. We use reinforcement learning to adaptively optimize a nonlinear neural classifier which outputs modulation bits from the values of the input signal and integration state variables. Analogous to the classical pole balancing control problem, a punishment signal triggers learning whenever any of the integrators saturate. We train a simple classifier consisting of locally tuned, binary address encoded neurons to produce stable noise shaping modulation, and present experimental results obtained from analog VLSI modulators of orders one and two. The integrated classifier contains an array of 64 neurons trained on-chip with a simplified variant on reinforcement learning.
{"title":"Design and VLSI implementation of an adaptive delta-sigma modulator","authors":"G. Cauwenberghs","doi":"10.1109/ICVD.1998.646595","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646595","url":null,"abstract":"The quality and stability of noise shaping is a concern in the design of higher-order delta-sigma modulators for high-resolution, high-speed oversampled analog-to-digital conversion. We reformulate noise-shaping modulation alternatively as a nonlinear optimal control problem, where the objective is to find the binary modulation sequence that minimizes signal swing in a cascade of integrators operating on the difference between the input signal and the modulation sequence. We use reinforcement learning to adaptively optimize a nonlinear neural classifier which outputs modulation bits from the values of the input signal and integration state variables. Analogous to the classical pole balancing control problem, a punishment signal triggers learning whenever any of the integrators saturate. We train a simple classifier consisting of locally tuned, binary address encoded neurons to produce stable noise shaping modulation, and present experimental results obtained from analog VLSI modulators of orders one and two. The integrated classifier contains an array of 64 neurons trained on-chip with a simplified variant on reinforcement learning.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124998437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646631
B. P. Dave, N. Jha
Hardware-software co-synthesis of an embedded system architecture entails partitioning of its specification into hardware and software modules such that its real-time and other constraints are met. Embedded systems are generally specified in terms of a set of acyclic task graphs. For medium-to-large scale embedded systems, the task graphs are usually hierarchical in nature. The embedded system architecture, which is the output of the co-synthesis system, may itself be non-hierarchical or hierarchical. Traditional non-hierarchical architectures create communication and processing bottlenecks, and are impractical for large embedded systems. Such systems require a large number of processing elements and communication links connected in a hierarchical manner, thus forming a hierarchical distributed architecture, to meet performance and cost objectives. In this paper, we address the problem of hardware-software co-synthesis of hierarchical distributed embedded system architectures from hierarchical or non-hierarchical task graphs. We show how our co-synthesis algorithm can be easily extended to consider fault tolerance or low power objectives or both. Although hierarchical architectures have been proposed before, to the best of our knowledge, this is the first time the notion of hierarchical task graphs and hierarchical architectures has been supported in a co-synthesis algorithm.
{"title":"COHRA: hardware-software co-synthesis of hierarchical distributed embedded system architectures","authors":"B. P. Dave, N. Jha","doi":"10.1109/ICVD.1998.646631","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646631","url":null,"abstract":"Hardware-software co-synthesis of an embedded system architecture entails partitioning of its specification into hardware and software modules such that its real-time and other constraints are met. Embedded systems are generally specified in terms of a set of acyclic task graphs. For medium-to-large scale embedded systems, the task graphs are usually hierarchical in nature. The embedded system architecture, which is the output of the co-synthesis system, may itself be non-hierarchical or hierarchical. Traditional non-hierarchical architectures create communication and processing bottlenecks, and are impractical for large embedded systems. Such systems require a large number of processing elements and communication links connected in a hierarchical manner, thus forming a hierarchical distributed architecture, to meet performance and cost objectives. In this paper, we address the problem of hardware-software co-synthesis of hierarchical distributed embedded system architectures from hierarchical or non-hierarchical task graphs. We show how our co-synthesis algorithm can be easily extended to consider fault tolerance or low power objectives or both. Although hierarchical architectures have been proposed before, to the best of our knowledge, this is the first time the notion of hierarchical task graphs and hierarchical architectures has been supported in a co-synthesis algorithm.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128783678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646573
G. Lakshminarayana, A. Raghunathan, N. Jha, S. Dey
In this paper, we present a power management technique targeted towards high-level synthesis of data-dominated behavioral descriptions. Our method is founded on the observation that variable assignment can significantly affect power management opportunities in the synthesized architecture. Based on this observation, we present a procedure for constraining variable assignment, so that the functional units in the synthesized architecture do not execute any spurious operations. Unlike many previously proposed power management techniques, our method does not have an attendant performance penalty. Experimental results indicate savings of up to 52.5% in power consumption over already power-optimized architectures, at area overheads not exceeding 6.4%.
{"title":"A power management methodology for high-level synthesis","authors":"G. Lakshminarayana, A. Raghunathan, N. Jha, S. Dey","doi":"10.1109/ICVD.1998.646573","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646573","url":null,"abstract":"In this paper, we present a power management technique targeted towards high-level synthesis of data-dominated behavioral descriptions. Our method is founded on the observation that variable assignment can significantly affect power management opportunities in the synthesized architecture. Based on this observation, we present a procedure for constraining variable assignment, so that the functional units in the synthesized architecture do not execute any spurious operations. Unlike many previously proposed power management techniques, our method does not have an attendant performance penalty. Experimental results indicate savings of up to 52.5% in power consumption over already power-optimized architectures, at area overheads not exceeding 6.4%.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129396742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646590
S. Balakrishnan, S. Nandy
Current day general purpose processors have been enhanced with what is called "media instruction set" to achieve performance gains in applications that are media processing intensive. The instruction set that has been added exploits the fact that media applications have small native datatypes and have widths much less than that supported by commercial processors and the plethora of data-parallelism in such applications. Current processors enhanced with the "media instruction set" support arithmetic on sub-datatypes of only 8-bit, 16-bit, 32-bit and 64-bit precision. In this paper we motivate the need for arbitrary precision packed arithmetic wherein the width of the sub-datatypes are programmable by the user and propose an implementation for arithmetic on such packed datatypes. The proposed scheme has marginal hardware overhead over conventional implementations of arithmetic on processors incorporating a multimedia extended instruction set.
{"title":"Arbitrary precision arithmetic-SIMD style","authors":"S. Balakrishnan, S. Nandy","doi":"10.1109/ICVD.1998.646590","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646590","url":null,"abstract":"Current day general purpose processors have been enhanced with what is called \"media instruction set\" to achieve performance gains in applications that are media processing intensive. The instruction set that has been added exploits the fact that media applications have small native datatypes and have widths much less than that supported by commercial processors and the plethora of data-parallelism in such applications. Current processors enhanced with the \"media instruction set\" support arithmetic on sub-datatypes of only 8-bit, 16-bit, 32-bit and 64-bit precision. In this paper we motivate the need for arbitrary precision packed arithmetic wherein the width of the sub-datatypes are programmable by the user and propose an implementation for arithmetic on such packed datatypes. The proposed scheme has marginal hardware overhead over conventional implementations of arithmetic on processors incorporating a multimedia extended instruction set.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114261869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646577
Z. Apanovich, A. Marchuk
The approach to technology migration presented in this paper is based on a compaction and rerouting strategy. It takes as input the full-chip mask layout hierarchical description (CIF format) and produces as output the mask layout in the target design rules. The applicability of the compaction and rerouting facilities, and the flexibility of the routing layers redistribution between different levels of mask layout hierarchy, are provided by a procedure for mask layout decomposition. The decomposition procedure takes as input any node of the mask layout hierarchical description and extracts the fragments which should be transformed by means of compaction. The size of the extracted fragments is controlled by decomposition parameters. Each extracted fragment is processed by a symbolisation procedure which provides resizing and regeneration of elementary objects such as transistors, contacts and wires. The target mask layout for each fragment is generated by a compaction procedure which is controlled by the constraints extracted during the symbolisation step. The resulting chip mask layout is generated by a routing procedure which is controlled by the data structures (netlist and floorplan) extracted during the decomposition step.
{"title":"Top-down approach to technology migration for full-custom mask layouts","authors":"Z. Apanovich, A. Marchuk","doi":"10.1109/ICVD.1998.646577","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646577","url":null,"abstract":"The approach to technology migration presented in this paper is based on a compaction and rerouting strategy. It takes as input the full-chip mask layout hierarchical description (CIF format) and produces as output the mask layout in the target design rules. The applicability of the compaction and rerouting facilities, and the flexibility of the routing layers redistribution between different levels of mask layout hierarchy, are provided by a procedure for mask layout decomposition. The decomposition procedure takes as input any node of the mask layout hierarchical description and extracts the fragments which should be transformed by means of compaction. The size of the extracted fragments is controlled by decomposition parameters. Each extracted fragment is processed by a symbolisation procedure which provides resizing and regeneration of elementary objects such as transistors, contacts and wires. The target mask layout for each fragment is generated by a compaction procedure which is controlled by the constraints extracted during the symbolisation step. The resulting chip mask layout is generated by a routing procedure which is controlled by the data structures (netlist and floorplan) extracted during the decomposition step.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114445574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646607
Abhijit Das, Samrat Sen, Mohan Rangan, Rupesh Nayak, G. Nandakumar
The prevalent concern over static timing analysis is that it might produce a very pessimistic result in presence of false paths in the circuit. It is therefore essential to detect and avoid the false paths during timing analysis, to estimate the timing characteristics of the design better. In this paper a framework is presented to automatically detect false paths at the transistor level. The false path detection involves logic extraction from a transistor level netlist and then detecting false paths, with more accurate estimation of the path delays.
{"title":"False path detection at transistor level","authors":"Abhijit Das, Samrat Sen, Mohan Rangan, Rupesh Nayak, G. Nandakumar","doi":"10.1109/ICVD.1998.646607","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646607","url":null,"abstract":"The prevalent concern over static timing analysis is that it might produce a very pessimistic result in presence of false paths in the circuit. It is therefore essential to detect and avoid the false paths during timing analysis, to estimate the timing characteristics of the design better. In this paper a framework is presented to automatically detect false paths at the transistor level. The false path detection involves logic extraction from a transistor level netlist and then detecting false paths, with more accurate estimation of the path delays.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129961116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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