Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646660
P. Rao, J. Jacob
We present NEWMIN, an efficient cube-based algorithm for minimization of single Boolean functions. The salient features of the algorithm are that it does not generate all the prime cubes, and highly efficient heuristics are used do obtain a minimal SPC cover. This leads to savings in computation time and reduces the cost of the solution as well for some classes of functions. The performance of a prototype implementation of NEWMIN is compared to that of ESPRESSO, the best known logic minimizer currently available. Our algorithm efficiently handles Achilles' heel functions which ESPRESSO finds difficult. Further, as is evident from the results, NEWMIN exhibits better performance on several classes of functions such as parity functions, cyclic functions and most randomly generated functions.
{"title":"A fast two-level logic minimizer","authors":"P. Rao, J. Jacob","doi":"10.1109/ICVD.1998.646660","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646660","url":null,"abstract":"We present NEWMIN, an efficient cube-based algorithm for minimization of single Boolean functions. The salient features of the algorithm are that it does not generate all the prime cubes, and highly efficient heuristics are used do obtain a minimal SPC cover. This leads to savings in computation time and reduces the cost of the solution as well for some classes of functions. The performance of a prototype implementation of NEWMIN is compared to that of ESPRESSO, the best known logic minimizer currently available. Our algorithm efficiently handles Achilles' heel functions which ESPRESSO finds difficult. Further, as is evident from the results, NEWMIN exhibits better performance on several classes of functions such as parity functions, cyclic functions and most randomly generated functions.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129884733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646649
X. Lin, I. Pomeranz, S. Reddy
We describe a test generation system for synchronous sequential circuits described at the gate level. The test generation system, called MIX, combines several test generation approaches to derive test sequences exhibiting very high fault coverages at relatively low CPU times. It is known that different faults in a synchronous sequential circuit may be more amenable to different test generation approaches. The strength of MIX stems from the fact that a large number of different approaches is used to attack faults with different characteristics. Several new techniques are incorporated into MIX, including a new definition of an XD-frontier, storing a partial state transition graph to help in the derivation of justification sequences, utilization of sequences generated for aborted faults, consideration of multiple time frames simultaneously during state justification, and dynamic computation of dependencies among flip-flops. A simplified form of test generation under the restricted multiple observation times test strategy is also employed, based on state expansion. Restricted multiple observation times fault simulation is used in MIX to identify detected faults beyond those detected by conventional fault simulation.
{"title":"MIX: a test generation system for synchronous sequential circuits","authors":"X. Lin, I. Pomeranz, S. Reddy","doi":"10.1109/ICVD.1998.646649","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646649","url":null,"abstract":"We describe a test generation system for synchronous sequential circuits described at the gate level. The test generation system, called MIX, combines several test generation approaches to derive test sequences exhibiting very high fault coverages at relatively low CPU times. It is known that different faults in a synchronous sequential circuit may be more amenable to different test generation approaches. The strength of MIX stems from the fact that a large number of different approaches is used to attack faults with different characteristics. Several new techniques are incorporated into MIX, including a new definition of an XD-frontier, storing a partial state transition graph to help in the derivation of justification sequences, utilization of sequences generated for aborted faults, consideration of multiple time frames simultaneously during state justification, and dynamic computation of dependencies among flip-flops. A simplified form of test generation under the restricted multiple observation times test strategy is also employed, based on state expansion. Restricted multiple observation times fault simulation is used in MIX to identify detected faults beyond those detected by conventional fault simulation.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125509047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646661
C. Bamji, M. Borah
An improved cost heuristic for selecting the transistor to size on the worst-delay path in a CMOS circuit is presented. Traditional cost heuristics used in a TILOS-like approach assume a single dominant critical path, ignoring the interactions among different paths in a circuit. As a result, layouts with larger than necessary active area are produced when the delay constraints are tight. Convex programming based approaches produce layouts with near-optimal area but at the cost of prohibitively long running times. The improved cost heuristic presented in this work takes into account the effect of sizing a given transistor T on many different critical paths in the circuit, based on local information in the neighborhood of T. When used with a TILOS-like algorithm, the heuristic produces layouts with considerably lower active area than layouts generated using the traditional cost heuristics. Moreover the number of iterations required using the improved heuristic is smaller than with the traditional cost heuristic resulting in lower CPU time requirement.
{"title":"An improved cost heuristic for transistor sizing","authors":"C. Bamji, M. Borah","doi":"10.1109/ICVD.1998.646661","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646661","url":null,"abstract":"An improved cost heuristic for selecting the transistor to size on the worst-delay path in a CMOS circuit is presented. Traditional cost heuristics used in a TILOS-like approach assume a single dominant critical path, ignoring the interactions among different paths in a circuit. As a result, layouts with larger than necessary active area are produced when the delay constraints are tight. Convex programming based approaches produce layouts with near-optimal area but at the cost of prohibitively long running times. The improved cost heuristic presented in this work takes into account the effect of sizing a given transistor T on many different critical paths in the circuit, based on local information in the neighborhood of T. When used with a TILOS-like algorithm, the heuristic produces layouts with considerably lower active area than layouts generated using the traditional cost heuristics. Moreover the number of iterations required using the improved heuristic is smaller than with the traditional cost heuristic resulting in lower CPU time requirement.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129033841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646654
T. Tsang
A high performance, area efficient and easy to use ROM compiler was designed. The design has been adapted to many different deep sub-micron processes and proven satisfactorily on silicon. Some design techniques which give the compiler the desirable features for ASIC applications are discussed. The software automation technologies are also covered.
{"title":"A compilable read-only-memory library for ASIC deep sub-micron applications","authors":"T. Tsang","doi":"10.1109/ICVD.1998.646654","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646654","url":null,"abstract":"A high performance, area efficient and easy to use ROM compiler was designed. The design has been adapted to many different deep sub-micron processes and proven satisfactorily on silicon. Some design techniques which give the compiler the desirable features for ASIC applications are discussed. The software automation technologies are also covered.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130034591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646578
B. Krishna, C.Y.R. Chen, N. Sehgal
In any cell-based design methodology, usually, a library of cells is designed without prior knowledge of where each cell may be used. The cells from the library are placed and routed to construct the physical implementation of a circuit. The cells are designed to minimize the layout area and a little consideration is given to the location of the interface terminals. This can hinder the design of high performance circuits as the routing phase may produce interconnects with excessive signal delays. We present a new top-down design flow in which the contents of leaf cells are constructed after the cell placement has been done, with area minimization as the primary goal. Based on this placement, we design the locations of interface terminals for the leaf cells. Our proposed method optimizes leaf cell interface on the basis of cell placement and global interconnect. Our experiments show that, with this new technique, we can achieve denser and high performance layouts. Our algorithm for planning of terminal locations minimizes the number of master cells needed for multiple instances of cells, thus minimizing the cell layout effort. Our results show a reduction in total manhattan net length of 28%-75%, which implies a decrease in interconnect delays and does not cause significant increase in cell area.
{"title":"Technique for planning of terminal locations of leaf cells in cell-based design with routing considerations","authors":"B. Krishna, C.Y.R. Chen, N. Sehgal","doi":"10.1109/ICVD.1998.646578","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646578","url":null,"abstract":"In any cell-based design methodology, usually, a library of cells is designed without prior knowledge of where each cell may be used. The cells from the library are placed and routed to construct the physical implementation of a circuit. The cells are designed to minimize the layout area and a little consideration is given to the location of the interface terminals. This can hinder the design of high performance circuits as the routing phase may produce interconnects with excessive signal delays. We present a new top-down design flow in which the contents of leaf cells are constructed after the cell placement has been done, with area minimization as the primary goal. Based on this placement, we design the locations of interface terminals for the leaf cells. Our proposed method optimizes leaf cell interface on the basis of cell placement and global interconnect. Our experiments show that, with this new technique, we can achieve denser and high performance layouts. Our algorithm for planning of terminal locations minimizes the number of master cells needed for multiple instances of cells, thus minimizing the cell layout effort. Our results show a reduction in total manhattan net length of 28%-75%, which implies a decrease in interconnect delays and does not cause significant increase in cell area.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127809338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646615
C. Bamji, R. Varadarajan
A method for automatically jogging wires to reduce layout area during compaction is described. The method operates incrementally and iteratively by jogging only those wires on the critical path that allow layout area to be reduced. Our modular implementation allows the same algorithm to be effectively used for overconstraint resolution by jogging wires. A novel range space based selection approach provides a theoretical basis for jogpoint selection. This method provides a global view during jogpoint selection that eliminates unnecessary jogs and provides consistency between jog locations on adjacent wires. Our system has been successfully applied to extremely large industrial test cases. Due to its incremental nature and its ability to avoid unnecessary jogs, our method can handle large layouts beyond the capability of existing exhaustive jogging methods.
{"title":"Incremental autojogging using range spaces","authors":"C. Bamji, R. Varadarajan","doi":"10.1109/ICVD.1998.646615","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646615","url":null,"abstract":"A method for automatically jogging wires to reduce layout area during compaction is described. The method operates incrementally and iteratively by jogging only those wires on the critical path that allow layout area to be reduced. Our modular implementation allows the same algorithm to be effectively used for overconstraint resolution by jogging wires. A novel range space based selection approach provides a theoretical basis for jogpoint selection. This method provides a global view during jogpoint selection that eliminates unnecessary jogs and provides consistency between jog locations on adjacent wires. Our system has been successfully applied to extremely large industrial test cases. Due to its incremental nature and its ability to avoid unnecessary jogs, our method can handle large layouts beyond the capability of existing exhaustive jogging methods.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124630518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646597
C. F. Prince, V. Vasudevan
In this paper we describe a new approach to simplification of symbolic expressions obtained using symbolic simulators. We use a combination of matrix-based and flow-graph based technique to generate signal flowgraphs that have frequency-dependent edge weights. The algorithm proceeds by first calculating the DC gain and then iteratively including frequency dependent terms that are significant in the frequency range of interest. This can be used to extract poles and zeroes together with a polynomial division procedure.
{"title":"Symbolic analysis of analog integrated circuits","authors":"C. F. Prince, V. Vasudevan","doi":"10.1109/ICVD.1998.646597","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646597","url":null,"abstract":"In this paper we describe a new approach to simplification of symbolic expressions obtained using symbolic simulators. We use a combination of matrix-based and flow-graph based technique to generate signal flowgraphs that have frequency-dependent edge weights. The algorithm proceeds by first calculating the DC gain and then iteratively including frequency dependent terms that are significant in the frequency range of interest. This can be used to extract poles and zeroes together with a polynomial division procedure.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116875287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646650
S. Kajihara, K. Saluja
Random pattern fault simulation is known to be an efficient method for accelerating test generation process but it is not suited for generating compact test sets because a test set generated by random pattern fault simulation contains many redundant test vectors. In this paper through a set of experiments we first demonstrate the inverse influence of the initial test set size on the final test set size obtained after compaction. We then propose a novel method of deriving compact test sets based on the random pattern fault simulation and compact test generation already proposed. Experimental results show that for the benchmark circuits our method produces minimum or near minimum test sets in substantially less run time than the methods that do not make use of random vectors.
{"title":"On test pattern compaction using random pattern fault simulation","authors":"S. Kajihara, K. Saluja","doi":"10.1109/ICVD.1998.646650","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646650","url":null,"abstract":"Random pattern fault simulation is known to be an efficient method for accelerating test generation process but it is not suited for generating compact test sets because a test set generated by random pattern fault simulation contains many redundant test vectors. In this paper through a set of experiments we first demonstrate the inverse influence of the initial test set size on the final test set size obtained after compaction. We then propose a novel method of deriving compact test sets based on the random pattern fault simulation and compact test generation already proposed. Experimental results show that for the benchmark circuits our method produces minimum or near minimum test sets in substantially less run time than the methods that do not make use of random vectors.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124142420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646584
P. Mishra, Somnath Paul, S. Venkataraman, Rajat Gupta
System level design objectives of cost, performance and time-to-market require a hardware/software co-design methodology comprising realization of custom hardware along with software execution on an embedded processor. In this context is described the architecture of AIM250, a high end mixed signal microcontroller for instrumentation, measurement and control systems. The embedded processor has a concurrently executing DSP engine and a 12-bit analog interface to external world making it one of the more advanced among contemporary microcontrollers. The special emphasis on design reconfigurability made it possible for it to achieve FPGA type flexibility in peripheral modules with negligible silicon overhead.
{"title":"Hardware/software co-design of a high-end mixed signal microcontroller","authors":"P. Mishra, Somnath Paul, S. Venkataraman, Rajat Gupta","doi":"10.1109/ICVD.1998.646584","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646584","url":null,"abstract":"System level design objectives of cost, performance and time-to-market require a hardware/software co-design methodology comprising realization of custom hardware along with software execution on an embedded processor. In this context is described the architecture of AIM250, a high end mixed signal microcontroller for instrumentation, measurement and control systems. The embedded processor has a concurrently executing DSP engine and a 12-bit analog interface to external world making it one of the more advanced among contemporary microcontrollers. The special emphasis on design reconfigurability made it possible for it to achieve FPGA type flexibility in peripheral modules with negligible silicon overhead.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125834024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646606
Aarti Gupta, P. Ashar
There has been much interest in techniques which combine the advantages of function-based methods, such as BDDs, with structure-based methods, such as ATPG, for verifying the equivalence of combinational circuits. However, most existing efforts have focused on exploiting circuit similarity through use of learning and/or ATPG-based methods rather than on making the integration between BDDs and ATPG techniques efficient. This paper presents a new technique, where the focus is on improving the equivalence check itself, thereby making it more robust in the absence of circuit similarity. It is based on tight integration of a Boolean Satisfiability Checker with BDDs, whereby BDDs are effectively used to reduce both the problem size and the number of backtracks for the satisfiability problem. This methodology does not preclude exploitation of circuit similarity, when it exists, since the improved check can be easily incorporated as the inner loop of the well-known iterative framework involving search and replacement of internally equivalent nodes. We demonstrate the significance of our contributions with practical results on the ISCAS benchmark circuits.
{"title":"Integrating a Boolean satisfiability checker and BDDs for combinational equivalence checking","authors":"Aarti Gupta, P. Ashar","doi":"10.1109/ICVD.1998.646606","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646606","url":null,"abstract":"There has been much interest in techniques which combine the advantages of function-based methods, such as BDDs, with structure-based methods, such as ATPG, for verifying the equivalence of combinational circuits. However, most existing efforts have focused on exploiting circuit similarity through use of learning and/or ATPG-based methods rather than on making the integration between BDDs and ATPG techniques efficient. This paper presents a new technique, where the focus is on improving the equivalence check itself, thereby making it more robust in the absence of circuit similarity. It is based on tight integration of a Boolean Satisfiability Checker with BDDs, whereby BDDs are effectively used to reduce both the problem size and the number of backtracks for the satisfiability problem. This methodology does not preclude exploitation of circuit similarity, when it exists, since the improved check can be easily incorporated as the inner loop of the well-known iterative framework involving search and replacement of internally equivalent nodes. We demonstrate the significance of our contributions with practical results on the ISCAS benchmark circuits.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134444009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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