Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646588
A. Abbo
In this paper, we present the design considerations of an embedded signal processor for application in integrated radio navigation. The navigation receiver consists of four different subsystems: GPS, OMEGA, Loran-C and MLS. Due to the complementary features of these subsystems, the combined receiver shows improved performance compared to the individual subsystems. We show how such a multifunction receiver can be built around a single high performance application-specific processor, which consists of both general-purpose and application-specific functional units. The processor customization into these functional units is accomplished through algorithm timing analysis using the MOVE processor development framework. A Loran-C baseband processor design is presented as a case-study. We present a new time-distributed FIR filter algorithm which reduces the computational complexity and hardware cost of the Loran-C subsystem.
{"title":"An embedded processor for integrated navigation receiver","authors":"A. Abbo","doi":"10.1109/ICVD.1998.646588","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646588","url":null,"abstract":"In this paper, we present the design considerations of an embedded signal processor for application in integrated radio navigation. The navigation receiver consists of four different subsystems: GPS, OMEGA, Loran-C and MLS. Due to the complementary features of these subsystems, the combined receiver shows improved performance compared to the individual subsystems. We show how such a multifunction receiver can be built around a single high performance application-specific processor, which consists of both general-purpose and application-specific functional units. The processor customization into these functional units is accomplished through algorithm timing analysis using the MOVE processor development framework. A Loran-C baseband processor design is presented as a case-study. We present a new time-distributed FIR filter algorithm which reduces the computational complexity and hardware cost of the Loran-C subsystem.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120950707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646666
Hugo De Man
Deep-Submicron (DS) technology is rapidly leading to systems-on-a-chip (SoC) designed at the processor-memory level, and containing a lot of mixed-signal and even RF architectures. However, exploitation of DS technology will depend critically on the availability of global system engineers able to bridge the gap between software-centric system thinking and hardware-software implementation, in novel silicon architectures. This requires a rethinking of present engineering schools which are not well equipped to tackle global system engineering aspects. The concept of design institute is introduced where, based on visionary system design demonstrators, new methodologies, tools, libraries and courses are created and distributed over the global network. Design institutes provide a learning school for new design paradigms and form the ideal environment for the education of global system designers and system design minded faculty.
{"title":"Future systems-on-a-chip: impact on engineering education","authors":"Hugo De Man","doi":"10.1109/ICVD.1998.646666","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646666","url":null,"abstract":"Deep-Submicron (DS) technology is rapidly leading to systems-on-a-chip (SoC) designed at the processor-memory level, and containing a lot of mixed-signal and even RF architectures. However, exploitation of DS technology will depend critically on the availability of global system engineers able to bridge the gap between software-centric system thinking and hardware-software implementation, in novel silicon architectures. This requires a rethinking of present engineering schools which are not well equipped to tackle global system engineering aspects. The concept of design institute is introduced where, based on visionary system design demonstrators, new methodologies, tools, libraries and courses are created and distributed over the global network. Design institutes provide a learning school for new design paradigms and form the ideal environment for the education of global system designers and system design minded faculty.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124035097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646576
N. Sherwani, Prashant S. Sawkar
ASIC as well as microprocessor design needs require very area efficient, timing driven, power and noise aware synthesis and layout capabilities. However, historically synthesis and layout have been optimized separately. Conventional synthesis aims to reduce the gate count without layout information, as a result, it might reduce logic where it may not result in significant area/power saving or timing benefit. As a consequence, several researchers have focused on integration of synthesis and layout. Some have attempted to provide layout information to synthesis while others have attempted local re-synthesis within the layout. In this tutorial, we review the existing work in the areas of logic and layout interaction. We present a classification of these approaches and their salient features.
{"title":"Layout driven synthesis or synthesis driven layout?","authors":"N. Sherwani, Prashant S. Sawkar","doi":"10.1109/ICVD.1998.646576","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646576","url":null,"abstract":"ASIC as well as microprocessor design needs require very area efficient, timing driven, power and noise aware synthesis and layout capabilities. However, historically synthesis and layout have been optimized separately. Conventional synthesis aims to reduce the gate count without layout information, as a result, it might reduce logic where it may not result in significant area/power saving or timing benefit. As a consequence, several researchers have focused on integration of synthesis and layout. Some have attempted to provide layout information to synthesis while others have attempted local re-synthesis within the layout. In this tutorial, we review the existing work in the areas of logic and layout interaction. We present a classification of these approaches and their salient features.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122337902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646638
W. Jone, Sunil R. Das
Pseudorandom testing has been widely used in built-in self-testing of VLSI circuits. Although the defect level estimation for pseudorandom testing has been performed using sequential statical analysis, no closed form can be accomplished as complex combinatorial enumerations are involved. In this work, a Markov model is employed to describe the pseudorandom test behaviors. For the first time, a closed form of the defect level equation is derived by solving the differential equation extracted from the Markov model. The defect level equation clearly describes the relationships among defect level, fabrication yield, the number of all input combinations, circuit detectability (in terms of the worst single stuck-at fault), and pseudorandom test length. Although our discussions are primarily based on the single stuck-at fault model, it is not difficult to extend the results to other fault types.
{"title":"A stochastic method for defect level analysis of pseudorandom testing","authors":"W. Jone, Sunil R. Das","doi":"10.1109/ICVD.1998.646638","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646638","url":null,"abstract":"Pseudorandom testing has been widely used in built-in self-testing of VLSI circuits. Although the defect level estimation for pseudorandom testing has been performed using sequential statical analysis, no closed form can be accomplished as complex combinatorial enumerations are involved. In this work, a Markov model is employed to describe the pseudorandom test behaviors. For the first time, a closed form of the defect level equation is derived by solving the differential equation extracted from the Markov model. The defect level equation clearly describes the relationships among defect level, fabrication yield, the number of all input combinations, circuit detectability (in terms of the worst single stuck-at fault), and pseudorandom test length. Although our discussions are primarily based on the single stuck-at fault model, it is not difficult to extend the results to other fault types.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122160011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646598
M. Hsiao, Gurjeet S. Saund, E. Rudnick, J. Patel
A partial scan selection strategy is proposed in which flip-flops are selected via newly proposed dynamic reachability and observability measures such that the remaining hard-to-detect faults are easily detected. This is done by taking advantage of the information available when a target fault is aborted by the test generator. A partial scan selection tool, IDROPS, has been developed which selects the best and smallest set of flip-flops to scan that will result in a high fault coverage. Results indicate that high fault coverage in hard-to-test circuits can be achieved using fewer scan flip-flops than in previous methods.
{"title":"Partial scan selection based on dynamic reachability and observability information","authors":"M. Hsiao, Gurjeet S. Saund, E. Rudnick, J. Patel","doi":"10.1109/ICVD.1998.646598","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646598","url":null,"abstract":"A partial scan selection strategy is proposed in which flip-flops are selected via newly proposed dynamic reachability and observability measures such that the remaining hard-to-detect faults are easily detected. This is done by taking advantage of the information available when a target fault is aborted by the test generator. A partial scan selection tool, IDROPS, has been developed which selects the best and smallest set of flip-flops to scan that will result in a high fault coverage. Results indicate that high fault coverage in hard-to-test circuits can be achieved using fewer scan flip-flops than in previous methods.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"73 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131878340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646619
A. Majhi, V. Agrawal
The test process for analog circuits currently focuses on performance verification, generally known as functional testing. For many classes of analog circuits, there are already well-known and accepted functional tests. However, the test development time and test set application time are too long for today's circuits. For new products, short product cycles and time-to-market are critical considerations. Test development time has two main factors: the presence of noise and a lack of powerful tools, models and practices. Besides, functional testing has been reported to fail in many system applications. Today, more often than before, there is a consensus that structural testing is a viable solution. A brief survey of the current trends and challenges in mixed-signal testing is given in this paper.
{"title":"Mixed-signal test","authors":"A. Majhi, V. Agrawal","doi":"10.1109/ICVD.1998.646619","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646619","url":null,"abstract":"The test process for analog circuits currently focuses on performance verification, generally known as functional testing. For many classes of analog circuits, there are already well-known and accepted functional tests. However, the test development time and test set application time are too long for today's circuits. For new products, short product cycles and time-to-market are critical considerations. Test development time has two main factors: the presence of noise and a lack of powerful tools, models and practices. Besides, functional testing has been reported to fail in many system applications. Today, more often than before, there is a consensus that structural testing is a viable solution. A brief survey of the current trends and challenges in mixed-signal testing is given in this paper.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128901579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ICVD.1998.646596
S. Pradeep Kiran, K. Radhakrishna Rao
A transconductor that exploits the square law relation of the FET in conjunction with the translinear relation for the bipolar transistors is proposed. Linear output is achieved by taking the square root of the drain current. Simulation results of the transconductor are given.
{"title":"A novel translinear principle based BiMOS transconductor","authors":"S. Pradeep Kiran, K. Radhakrishna Rao","doi":"10.1109/ICVD.1998.646596","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646596","url":null,"abstract":"A transconductor that exploits the square law relation of the FET in conjunction with the translinear relation for the bipolar transistors is proposed. Linear output is achieved by taking the square root of the drain current. Simulation results of the transconductor are given.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"4 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113955688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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