Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646643
Atul Wokhlu, R. Krishna, S. Agarwal
This paper describes a mixed signal, low voltage, digital clinical thermometer chip. Temperature is sensed using a thermistor sensor. A modified Schmitt trigger based relaxation oscillator is used to convert thermistor resistance into a frequency signal. A ROM is used to map the Schmitt trigger frequency onto temperature. An extensive analysis of various errors in temperature measurement is provided. The chip can measure temperature to an accuracy of better than 0.1/spl deg/C down to 1.1 V battery voltage. It has a die size of 87/spl times/91 mils and is implemented in a 1.2 /spl mu/m double metal single poly CMOS process.
{"title":"A low voltage mixed signal ASIC for digital clinical thermometer","authors":"Atul Wokhlu, R. Krishna, S. Agarwal","doi":"10.1109/ICVD.1998.646643","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646643","url":null,"abstract":"This paper describes a mixed signal, low voltage, digital clinical thermometer chip. Temperature is sensed using a thermistor sensor. A modified Schmitt trigger based relaxation oscillator is used to convert thermistor resistance into a frequency signal. A ROM is used to map the Schmitt trigger frequency onto temperature. An extensive analysis of various errors in temperature measurement is provided. The chip can measure temperature to an accuracy of better than 0.1/spl deg/C down to 1.1 V battery voltage. It has a die size of 87/spl times/91 mils and is implemented in a 1.2 /spl mu/m double metal single poly CMOS process.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129343890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646639
H. Selvaraj, M. Nowicka, T. Luba
Existing FPGA-oriented algorithms can be divided into two categories: minimising the number of LUTs in the solution (MIS-pga, Trade, and ASYL); and minimising the delay in the solution (DAG-Map, SWEEP, and Flow-map). Several algorithms have been implemented with both area and delay minimisation versions, for example MIS-pga and ASYL. Two collaborating groups from Warsaw University of Technology, Poland and Monash University, Australia have developed decomposition theory and procedures for single and multiple-output Boolean functions. These include a balanced decomposition algorithm which applies either parallel or serial decomposition at each phase of the synthesis process. The algorithm has been implemented in an experimental logic synthesis tool DEMAIN. Recent tests on MCNC and industrial benchmarks show that DEMAIN produces much more economical designs than major FPGA vendors software.
{"title":"Decomposition strategies and their performance in FPGA-based technology mapping","authors":"H. Selvaraj, M. Nowicka, T. Luba","doi":"10.1109/ICVD.1998.646639","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646639","url":null,"abstract":"Existing FPGA-oriented algorithms can be divided into two categories: minimising the number of LUTs in the solution (MIS-pga, Trade, and ASYL); and minimising the delay in the solution (DAG-Map, SWEEP, and Flow-map). Several algorithms have been implemented with both area and delay minimisation versions, for example MIS-pga and ASYL. Two collaborating groups from Warsaw University of Technology, Poland and Monash University, Australia have developed decomposition theory and procedures for single and multiple-output Boolean functions. These include a balanced decomposition algorithm which applies either parallel or serial decomposition at each phase of the synthesis process. The algorithm has been implemented in an experimental logic synthesis tool DEMAIN. Recent tests on MCNC and industrial benchmarks show that DEMAIN produces much more economical designs than major FPGA vendors software.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130127530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646634
A. Majhi, V. Agrawal
Failures that cause logic circuits to malfunction at the desired clock rate and thus violate timing specifications are currently receiving much attention. Such failures are modeled as delay faults. They facilitate delay testing. The use of delay fault models in VLSI test generation is very likely to gain industry acceptance in the near future. In this paper, we review delay fault models, discuss their classifications and examine fault coverage metrics that have been proposed in the recent literature. A comparison between delay fault models, namely, gate delay, transition, path delay, line delay and segment delay faults, shows their benefits and limitations. Various classifications of the path delay fault model, that have received the most attention in recent years, are reviewed. We believe an understanding of delay fault models is essential in today's VLSI design and test environment.
{"title":"Delay fault models and coverage","authors":"A. Majhi, V. Agrawal","doi":"10.1109/ICVD.1998.646634","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646634","url":null,"abstract":"Failures that cause logic circuits to malfunction at the desired clock rate and thus violate timing specifications are currently receiving much attention. Such failures are modeled as delay faults. They facilitate delay testing. The use of delay fault models in VLSI test generation is very likely to gain industry acceptance in the near future. In this paper, we review delay fault models, discuss their classifications and examine fault coverage metrics that have been proposed in the recent literature. A comparison between delay fault models, namely, gate delay, transition, path delay, line delay and segment delay faults, shows their benefits and limitations. Various classifications of the path delay fault model, that have received the most attention in recent years, are reviewed. We believe an understanding of delay fault models is essential in today's VLSI design and test environment.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128972540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646610
A. M. Pereira, T. Pimenta, R. Moreno, R. EdgarCharry, A. Jorge
Dynamic current mirrors, or SI current cells, are widely used in analog signal processing circuits. They could be implemented using a standard cell methodology if an SI cell library is available. Aiming at the creation of that library, this work presents the design of the measuring system and the interface circuits (on a chip) necessary to test SI cells with precision of 450 ppm and operation frequency of 3 MHz. Measurements performed on the prototypes show that the harmonics components and the noise level are 70 dB smaller than the fundamental and the total harmonic distortion is 0.04%.
{"title":"Design of a measurement and interface integrated circuit for characterization of switched current memory cells","authors":"A. M. Pereira, T. Pimenta, R. Moreno, R. EdgarCharry, A. Jorge","doi":"10.1109/ICVD.1998.646610","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646610","url":null,"abstract":"Dynamic current mirrors, or SI current cells, are widely used in analog signal processing circuits. They could be implemented using a standard cell methodology if an SI cell library is available. Aiming at the creation of that library, this work presents the design of the measuring system and the interface circuits (on a chip) necessary to test SI cells with precision of 450 ppm and operation frequency of 3 MHz. Measurements performed on the prototypes show that the harmonics components and the noise level are 70 dB smaller than the fundamental and the total harmonic distortion is 0.04%.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121265230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646633
Dong-Hyun Heo, A. C. Parker, C. Ravikumar
This paper considers the system redesign problem where an existing digital electronic system must be redesigned for reasons such as better performance, technology upgrade, lower power, and so on. The designer may wish to retain certain design for purely, technical reasons or reasons of propriety. We presented an algorithm based on the evolutionary paradigm for optimally redesigning an existing design. A tool called GRAFT which implements the evolutionary algorithm is described.
{"title":"An evolutionary approach to system redesign","authors":"Dong-Hyun Heo, A. C. Parker, C. Ravikumar","doi":"10.1109/ICVD.1998.646633","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646633","url":null,"abstract":"This paper considers the system redesign problem where an existing digital electronic system must be redesigned for reasons such as better performance, technology upgrade, lower power, and so on. The designer may wish to retain certain design for purely, technical reasons or reasons of propriety. We presented an algorithm based on the evolutionary paradigm for optimally redesigning an existing design. A tool called GRAFT which implements the evolutionary algorithm is described.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123108259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646663
S. Rajan, M. Fujita
We present a high-level ATM switch design methodology, beginning with parametric high-level model, debugging the model using a combination of formal verification and simulation, and synthesizing the model to a gate-level implementation. Our parametric model of an ATM switch has been used to automatically synthesize ATM switches of customers' choices by choosing concrete values of the generic parameters. The difficulty in validating ATM switch design arises not only due to parametrization, but also due to delicate control module design involved in concurrent processes communicating through shared signals. We provide a pragmatic combination of simulation, model checking, and theorem proving to gain confidence in the correctness of ATM switch design.
{"title":"Integration of high-level modeling, formal verification, and high-level synthesis in ATM switch design","authors":"S. Rajan, M. Fujita","doi":"10.1109/ICVD.1998.646663","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646663","url":null,"abstract":"We present a high-level ATM switch design methodology, beginning with parametric high-level model, debugging the model using a combination of formal verification and simulation, and synthesizing the model to a gate-level implementation. Our parametric model of an ATM switch has been used to automatically synthesize ATM switches of customers' choices by choosing concrete values of the generic parameters. The difficulty in validating ATM switch design arises not only due to parametrization, but also due to delicate control module design involved in concurrent processes communicating through shared signals. We provide a pragmatic combination of simulation, model checking, and theorem proving to gain confidence in the correctness of ATM switch design.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127470994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646570
T. Meng
Our present ability to work with video has been confined to a wired environment, requiring both the video encoder and decoder to be physically connected to a power supply and a wired communication link. This paper presents a portable video-on-demand system capable of delivering high-quality image and video data in a wireless environment. The discussion will focus on both the architectural and circuit design techniques developed for implementing a high-performance, error-resistant video compression/decompression system at power levels that are two orders of magnitude below existing solutions. This low-power video compression system not only provides a compression efficiency better than industry standards, but also embeds a high degree of error tolerance in the compression algorithm itself to guard against transmission errors often encountered in wireless communication.
{"title":"A wireless portable video-on-demand system","authors":"T. Meng","doi":"10.1109/ICVD.1998.646570","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646570","url":null,"abstract":"Our present ability to work with video has been confined to a wired environment, requiring both the video encoder and decoder to be physically connected to a power supply and a wired communication link. This paper presents a portable video-on-demand system capable of delivering high-quality image and video data in a wireless environment. The discussion will focus on both the architectural and circuit design techniques developed for implementing a high-performance, error-resistant video compression/decompression system at power levels that are two orders of magnitude below existing solutions. This low-power video compression system not only provides a compression efficiency better than industry standards, but also embeds a high degree of error tolerance in the compression algorithm itself to guard against transmission errors often encountered in wireless communication.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122629468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646594
S. Venkatraman, S. Natarajan, K. Rao
A new tuning loop is presented for tuning continuous time filters. This tuning loop is applicable mainly to all MOS circuits, in which the tuning range of the filter is severely restricted. It is shown that the tuning loop helps in operating the filter at the desired power efficiency levels, and also extends the tuning range of the filter.
{"title":"A new tuning scheme for continuous time filters","authors":"S. Venkatraman, S. Natarajan, K. Rao","doi":"10.1109/ICVD.1998.646594","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646594","url":null,"abstract":"A new tuning loop is presented for tuning continuous time filters. This tuning loop is applicable mainly to all MOS circuits, in which the tuning range of the filter is severely restricted. It is shown that the tuning loop helps in operating the filter at the desired power efficiency levels, and also extends the tuning range of the filter.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115500031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646612
P. Gopalakrishnan, V. Vasudevan
CAD tools developed for routing analog circuits have to give special consideration for the quality of the routes developed, owing to the high sensitivity of these circuits to small changes in the layout geometry. Cost based path-finding algorithms that find globally optimal solutions are thus best suited for implementing routing in analog circuits. In this paper, we propose a modification to the line expansion algorithm used previously, that results in significant savings in time and memory consumed.
{"title":"A modified line expansion algorithm for device-level routing of analog integrated circuits","authors":"P. Gopalakrishnan, V. Vasudevan","doi":"10.1109/ICVD.1998.646612","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646612","url":null,"abstract":"CAD tools developed for routing analog circuits have to give special consideration for the quality of the routes developed, owing to the high sensitivity of these circuits to small changes in the layout geometry. Cost based path-finding algorithms that find globally optimal solutions are thus best suited for implementing routing in analog circuits. In this paper, we propose a modification to the line expansion algorithm used previously, that results in significant savings in time and memory consumed.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129723981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-01-04DOI: 10.1109/ICVD.1998.646611
S. Nooshabadi, G. Visweswaran, D. Nagchoudhuri
In this paper current mirror sources have been employed to design a ternary D/A converter. A much better performance and area saving over the 3R-4R resistive network has been achieved.
本文采用电流镜像源设计了一个三元数模转换器。与3R-4R电阻网络相比，具有更好的性能和面积节约。
{"title":"Current mode ternary D/A converter","authors":"S. Nooshabadi, G. Visweswaran, D. Nagchoudhuri","doi":"10.1109/ICVD.1998.646611","DOIUrl":"https://doi.org/10.1109/ICVD.1998.646611","url":null,"abstract":"In this paper current mirror sources have been employed to design a ternary D/A converter. A much better performance and area saving over the 3R-4R resistive network has been achieved.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129755866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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