Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7468210
C. Bakker, B. Vermulst, A. Driessen
Soft-switching of resonant dc-dc converters is used to enable high switching-frequencies and miniaturization of filter components. These converters are typically modeled using a first-harmonic approximation. This results in generalization of the operating modes, by only using the first harmonic of the converter. In this paper a phase-shift controlled series-resonant converter is analyzed per operating mode using an accurate analysis. For each operating mode, an analytical expression is derived resulting in a more accurate representation of the converter behavior when compared to first-harmonic approximation. Experimental results show that the model accurately predicts the converter.
{"title":"Analytical model of a phase-shift controlled three-level zero-voltage switching converter","authors":"C. Bakker, B. Vermulst, A. Driessen","doi":"10.1109/APEC.2016.7468210","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468210","url":null,"abstract":"Soft-switching of resonant dc-dc converters is used to enable high switching-frequencies and miniaturization of filter components. These converters are typically modeled using a first-harmonic approximation. This results in generalization of the operating modes, by only using the first harmonic of the converter. In this paper a phase-shift controlled series-resonant converter is analyzed per operating mode using an accurate analysis. For each operating mode, an analytical expression is derived resulting in a more accurate representation of the converter behavior when compared to first-harmonic approximation. Experimental results show that the model accurately predicts the converter.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116640371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7468056
Marzieh Ekhtiari, T. Andersen, Zhe Zhang, M. Andersen
A new method is implemented in designing of self-oscillating loop for driving piezoelectric transformers. The implemented method is based on combining both analog and digital control systems. Digitized delay, or digitized phase shift through the self-oscillating loop results in a very precise frequency control and ensures an optimum operation of the piezoelectric transformer in terms of voltage gain and efficiency. In this work, additional time delay is implemented digitally for the first time through 16 bit digital-to-analog converter to the self-oscillating loop. Delay control setpoints updates at a rate of 417 kHz. This allows the control loop to dynamically follow frequency changes of the transformer in each resonant cycle. The operation principle behind self-oscillating is discussed in this paper. Moreover, experimental results are reported.
{"title":"Digitized self-oscillating loop for piezoelectric transformer-based power converters","authors":"Marzieh Ekhtiari, T. Andersen, Zhe Zhang, M. Andersen","doi":"10.1109/APEC.2016.7468056","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468056","url":null,"abstract":"A new method is implemented in designing of self-oscillating loop for driving piezoelectric transformers. The implemented method is based on combining both analog and digital control systems. Digitized delay, or digitized phase shift through the self-oscillating loop results in a very precise frequency control and ensures an optimum operation of the piezoelectric transformer in terms of voltage gain and efficiency. In this work, additional time delay is implemented digitally for the first time through 16 bit digital-to-analog converter to the self-oscillating loop. Delay control setpoints updates at a rate of 417 kHz. This allows the control loop to dynamically follow frequency changes of the transformer in each resonant cycle. The operation principle behind self-oscillating is discussed in this paper. Moreover, experimental results are reported.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116770945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7467907
Saeed Anwar, Weimin Zhang, Fred Wang, D. Costinett
In this paper, an integrated, reconfigurable DC-DC converter for plugin and hybrid Electric Vehicles (EV) is proposed. The converter integrates functionality for both EV powertrain and charging operation into a single unit. During charging, the proposed converter functions as a DAB converter, providing galvanic isolation. For powertrain operation, the converter functions as an interleaved boost converter. During light load powertrain operation, the efficiency of the converter can be further improved by employing the integrated DAB. The proposed integrated converter does not require any extra relays or contactors for charging and powertrain operation. By using such integration, the overall volume and weight of the power electronics circuits, passives and associated cooling system can be improved. In addition, the power flow efficiency from EV battery to the high voltage DC bus for the motor inverter can be improved. The experimental results of the prototype are presented to verify the functionality of the proposed converter.
{"title":"Integrated DC-DC converter design for Electric Vehicle powertrains","authors":"Saeed Anwar, Weimin Zhang, Fred Wang, D. Costinett","doi":"10.1109/APEC.2016.7467907","DOIUrl":"https://doi.org/10.1109/APEC.2016.7467907","url":null,"abstract":"In this paper, an integrated, reconfigurable DC-DC converter for plugin and hybrid Electric Vehicles (EV) is proposed. The converter integrates functionality for both EV powertrain and charging operation into a single unit. During charging, the proposed converter functions as a DAB converter, providing galvanic isolation. For powertrain operation, the converter functions as an interleaved boost converter. During light load powertrain operation, the efficiency of the converter can be further improved by employing the integrated DAB. The proposed integrated converter does not require any extra relays or contactors for charging and powertrain operation. By using such integration, the overall volume and weight of the power electronics circuits, passives and associated cooling system can be improved. In addition, the power flow efficiency from EV battery to the high voltage DC bus for the motor inverter can be improved. The experimental results of the prototype are presented to verify the functionality of the proposed converter.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127165231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7467994
E. Jones, Fred Wang, D. Costinett, Zheyu Zhang, Ben Guo
Enhancement-mode GaN HFETs enable efficient high-frequency converter design, but this technology is relatively new and exhibits different characteristics from Si or SiC MOSFETs. GaN performance at elevated temperature is especially unique. Turn-on time increases significantly with temperature, and turn-on losses increase as a result. This phenomenon can be explained based on the relationships between junction temperature and GaN device transconductance, and between transconductance and turn-on time. An analytical relationship between temperature and turn-on loss has been derived for the 650-V GS66508 from GaN Systems, and verified with experimental results. Based on this relationship, a detailed model is developed, and a simplified scaling factor is proposed for estimating turn-on loss in e-mode GaN HFETs, using room-temperature switching characterization and typically published datasheet parameters.
{"title":"Temperature-dependent turn-on loss analysis for GaN HFETs","authors":"E. Jones, Fred Wang, D. Costinett, Zheyu Zhang, Ben Guo","doi":"10.1109/APEC.2016.7467994","DOIUrl":"https://doi.org/10.1109/APEC.2016.7467994","url":null,"abstract":"Enhancement-mode GaN HFETs enable efficient high-frequency converter design, but this technology is relatively new and exhibits different characteristics from Si or SiC MOSFETs. GaN performance at elevated temperature is especially unique. Turn-on time increases significantly with temperature, and turn-on losses increase as a result. This phenomenon can be explained based on the relationships between junction temperature and GaN device transconductance, and between transconductance and turn-on time. An analytical relationship between temperature and turn-on loss has been derived for the 650-V GS66508 from GaN Systems, and verified with experimental results. Based on this relationship, a detailed model is developed, and a simplified scaling factor is proposed for estimating turn-on loss in e-mode GaN HFETs, using room-temperature switching characterization and typically published datasheet parameters.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124819025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7468072
Jeppe Pedersen, A. Knott, M. Andersen
This paper focuses on the electromagnetic compatibility (EMC) performance of a Very High Frequency (VHF) converter and how to lower the emissions. To test the EMC performance a VHF converter is implemented with a Class-E inverter and a Class-DE rectifier. The converter is designed to deliver 3 W to a 60 V LED, it has a switching frequency of 37 MHz and achieves an efficiency of 80%. For an LED driver to be used on the consumer market it has to fulfil the standard regarding EMC emissions. The conducted emission is often used as a reason to increase the switching frequency to the VHF range to avoid the regulations. This converter shows to be well below the levels for conducted emission even without filtering. For the radiated emissions the converter is above the limits without input and output filters. Several designs with different ways to lower the emissions are implemented and the different layouts and filtering are compared and discussed.
{"title":"EMC investigation of a Very High Frequency self-oscillating resonant power converter","authors":"Jeppe Pedersen, A. Knott, M. Andersen","doi":"10.1109/APEC.2016.7468072","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468072","url":null,"abstract":"This paper focuses on the electromagnetic compatibility (EMC) performance of a Very High Frequency (VHF) converter and how to lower the emissions. To test the EMC performance a VHF converter is implemented with a Class-E inverter and a Class-DE rectifier. The converter is designed to deliver 3 W to a 60 V LED, it has a switching frequency of 37 MHz and achieves an efficiency of 80%. For an LED driver to be used on the consumer market it has to fulfil the standard regarding EMC emissions. The conducted emission is often used as a reason to increase the switching frequency to the VHF range to avoid the regulations. This converter shows to be well below the levels for conducted emission even without filtering. For the radiated emissions the converter is above the limits without input and output filters. Several designs with different ways to lower the emissions are implemented and the different layouts and filtering are compared and discussed.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124947853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7468283
Xiangyu Han, Qichen Yang, L. Wu, M. Saeedifard
Thermal cycling stress is one of the most potential factors challenging the reliability/lifetime of semiconductor devices and cause of their failures. This paper analyzes and investigates the impacts of various control strategies on thermal cycling stress of the semiconductor devices of the Modular Multilevel Converter (MMC) for drive applications. Various control strategies based on injecting a common-mode voltage and a circulating current are investigated and their impacts on power loss distribution and thermal cycling of the semiconductor devices of the MMC-based drive systems are evaluated. Simulation results in the MATLAB/SIMULINK software environment are presented to evaluate the accuracy of the analysis and impacts of three control strategies on power losses and thermal distribution of semiconductor devices of the MMC-based drive system.
{"title":"Analysis of thermal cycling stress on semiconductor devices of the Modular Multilevel Converter for drive applications","authors":"Xiangyu Han, Qichen Yang, L. Wu, M. Saeedifard","doi":"10.1109/APEC.2016.7468283","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468283","url":null,"abstract":"Thermal cycling stress is one of the most potential factors challenging the reliability/lifetime of semiconductor devices and cause of their failures. This paper analyzes and investigates the impacts of various control strategies on thermal cycling stress of the semiconductor devices of the Modular Multilevel Converter (MMC) for drive applications. Various control strategies based on injecting a common-mode voltage and a circulating current are investigated and their impacts on power loss distribution and thermal cycling of the semiconductor devices of the MMC-based drive systems are evaluated. Simulation results in the MATLAB/SIMULINK software environment are presented to evaluate the accuracy of the analysis and impacts of three control strategies on power losses and thermal distribution of semiconductor devices of the MMC-based drive system.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125024292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7468158
S. Dusmez, B. Akin
Thermal/power cycles are widely acknowledged methods to accelerate the package related extrinsic failures. Many studies have focused on particular failure precursor at a time and continuously monitored it using custom-built circuits. Due to the difficulties in taking sensitive measurements, the reported findings are more on the quantities requiring less sensitive measurements such as on-state resistance. In this paper, a custom-designed test bed is used to age a number of power MOSFETs and an automated curve tracer is utilized to capture parametric variations in I-V curves, transfer capacitances and gate charges at certain time intervals throughout the aging. The results suggest that the failure precursors which exhibit continuously increasing trend are the on-state resistance, body diode voltage drop, parasitic capacitances and threshold voltage. Based on the results, an exponential empirical model for the gate threshold voltage that fits successfully with the experimental data is proposed. Furthermore, Kalman Filter is employed to filter out the measurement noise and model uncertainties, which is also used to estimate the remaining useful lifetime of the degraded switches.
{"title":"Comprehensive parametric analyses of thermally aged power MOSFETs for failure precursor identification and lifetime estimation based on gate threshold voltage","authors":"S. Dusmez, B. Akin","doi":"10.1109/APEC.2016.7468158","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468158","url":null,"abstract":"Thermal/power cycles are widely acknowledged methods to accelerate the package related extrinsic failures. Many studies have focused on particular failure precursor at a time and continuously monitored it using custom-built circuits. Due to the difficulties in taking sensitive measurements, the reported findings are more on the quantities requiring less sensitive measurements such as on-state resistance. In this paper, a custom-designed test bed is used to age a number of power MOSFETs and an automated curve tracer is utilized to capture parametric variations in I-V curves, transfer capacitances and gate charges at certain time intervals throughout the aging. The results suggest that the failure precursors which exhibit continuously increasing trend are the on-state resistance, body diode voltage drop, parasitic capacitances and threshold voltage. Based on the results, an exponential empirical model for the gate threshold voltage that fits successfully with the experimental data is proposed. Furthermore, Kalman Filter is employed to filter out the measurement noise and model uncertainties, which is also used to estimate the remaining useful lifetime of the degraded switches.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123279617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7468130
H. Le, K. Orikawa, J. Itoh
This paper clarifies the relationship between the current ripple and the power density in bidirectional DC-DC converters. In the conventional power density design method, in order to obtain the pareto-front curve of the power density and the efficiency, the current ripple is designed as constant value, whereas the switching frequency is varied. As a result, the possibilities of higher power density or higher efficiency at different current ripple are not considered. Therefore, in this paper, the current ripple is also varied in order to evaluate all the designable power density. Specifically, a design flow chart is introduced to show step-by-step how to express all the losses and the volume of the converter as functions of the current ripple. Several 1-kW prototypes are constructed in order to confirm the validity of the design flow chart. By varying the current ripple, the highest power density of 10.1 kW/dm3 with the efficiency of 98.55% is achieved at the current ripple of 60%. Furthermore, the maximum error between the calculated and experimental power density and efficiency are 19.5% and 0.22 pt. respectively.
{"title":"Clarification of relationship between current ripple and power density in bidirectional DC-DC converter","authors":"H. Le, K. Orikawa, J. Itoh","doi":"10.1109/APEC.2016.7468130","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468130","url":null,"abstract":"This paper clarifies the relationship between the current ripple and the power density in bidirectional DC-DC converters. In the conventional power density design method, in order to obtain the pareto-front curve of the power density and the efficiency, the current ripple is designed as constant value, whereas the switching frequency is varied. As a result, the possibilities of higher power density or higher efficiency at different current ripple are not considered. Therefore, in this paper, the current ripple is also varied in order to evaluate all the designable power density. Specifically, a design flow chart is introduced to show step-by-step how to express all the losses and the volume of the converter as functions of the current ripple. Several 1-kW prototypes are constructed in order to confirm the validity of the design flow chart. By varying the current ripple, the highest power density of 10.1 kW/dm3 with the efficiency of 98.55% is achieved at the current ripple of 60%. Furthermore, the maximum error between the calculated and experimental power density and efficiency are 19.5% and 0.22 pt. respectively.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125378387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7467873
S. Sahoo, T. Bhattacharya
This paper proposes synchronization strategies for cascaded H-Bridge multi level inverter (CHBMLI) topologies with carrier based sinusoidal pulse width modulation (PWM) techniques. It is presented how synchronous carriers are generated in desired phase and frequency from the instantaneous voltage references to maintain 3-Φ, half wave and quarter wave symmetries among inverter pole voltage outputs for carrier based sinusoidal PWM of CHBMLI. To achieve dynamic synchronization, the triangular carriers are generated from the instantaneous voltage references in a phase locked manner. The scheme is experimentally tested with phase shifted PWM technique for both open loop Vbyf and closed loop vector control of squirrel cage induction motor drive supplied from a 3-Φ 5 level CHBMLI and the results are presented.
{"title":"Synchronization strategies in cascaded H-Bridge multi level inverters for carrier based sinusoidal PWM techniques","authors":"S. Sahoo, T. Bhattacharya","doi":"10.1109/APEC.2016.7467873","DOIUrl":"https://doi.org/10.1109/APEC.2016.7467873","url":null,"abstract":"This paper proposes synchronization strategies for cascaded H-Bridge multi level inverter (CHBMLI) topologies with carrier based sinusoidal pulse width modulation (PWM) techniques. It is presented how synchronous carriers are generated in desired phase and frequency from the instantaneous voltage references to maintain 3-Φ, half wave and quarter wave symmetries among inverter pole voltage outputs for carrier based sinusoidal PWM of CHBMLI. To achieve dynamic synchronization, the triangular carriers are generated from the instantaneous voltage references in a phase locked manner. The scheme is experimentally tested with phase shifted PWM technique for both open loop Vbyf and closed loop vector control of squirrel cage induction motor drive supplied from a 3-Φ 5 level CHBMLI and the results are presented.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126730364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-20DOI: 10.1109/APEC.2016.7468320
Ping-an Tan, Haibing He, Xieping Gao
Wireless power transfer (WPT) technology is now recognized as an efficient means of transferring power because having numerous advantages over conventional wired power transfer system. The phase delays, for example induced in the sampling process, the algorithm implementation process, the signal transduction process, etc. are widely found during the implementation of WPT system, which significantly degrade the system performance. Moreover, it would be extremely necessary to implement the Soft-Switching of the converter and the necessary dead time imposed by the drivers should be compatible with the resonant current phase lag control. This paper proposes a Direct Phase Control (DPC) approach, based on Second-Order Generalized Integrator Phase-Locked Loop (SOGI-PLL), to provide accurate phase compensation and stable ZVS operation in the WPT. The DPC determines the phase difference Δθ of WPT, which include the phase difference θι between the output voltage and current of the converter and the phase delay θ"ι derived from the sampling process. The SOGI-PLL provides the phase of system for adjusting the output voltage frequency of the converter dynamically. Experimental results convincingly demonstrate that with the proposed method the phase delay can be compensated accurately and the ZVS operation can be achieved simultaneously.
{"title":"Phase compensation, ZVS operation of wireless power transfer system based on SOGI-PLL","authors":"Ping-an Tan, Haibing He, Xieping Gao","doi":"10.1109/APEC.2016.7468320","DOIUrl":"https://doi.org/10.1109/APEC.2016.7468320","url":null,"abstract":"Wireless power transfer (WPT) technology is now recognized as an efficient means of transferring power because having numerous advantages over conventional wired power transfer system. The phase delays, for example induced in the sampling process, the algorithm implementation process, the signal transduction process, etc. are widely found during the implementation of WPT system, which significantly degrade the system performance. Moreover, it would be extremely necessary to implement the Soft-Switching of the converter and the necessary dead time imposed by the drivers should be compatible with the resonant current phase lag control. This paper proposes a Direct Phase Control (DPC) approach, based on Second-Order Generalized Integrator Phase-Locked Loop (SOGI-PLL), to provide accurate phase compensation and stable ZVS operation in the WPT. The DPC determines the phase difference Δθ of WPT, which include the phase difference θι between the output voltage and current of the converter and the phase delay θ\"ι derived from the sampling process. The SOGI-PLL provides the phase of system for adjusting the output voltage frequency of the converter dynamically. Experimental results convincingly demonstrate that with the proposed method the phase delay can be compensated accurately and the ZVS operation can be achieved simultaneously.","PeriodicalId":143091,"journal":{"name":"2016 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116004836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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