Pub Date : 2016-09-01DOI: 10.1109/THERMINIC.2016.7749073
B. Plesz, J. Mizsei
One of nowadays crucial questions with crystalline silicon solar cells is the reduction of manufacturing costs. One possible concept of reducing cost is to produce solar cells with thin photoactive layers, in order to use less amount of good quality and thus expensive raw material. In addition photovoltaic devices are one of the most obvious solutions for on-chip energy harvesting. There are basically two approaches: the monolithically integrated photovoltaic devices, and photovoltaic devices that are attached to the chip surface and connected to the integrated circuit. These devices also feature a thin photoactive layer in the majority of the cases. This paper aims to investigate the influence of the photoactive layer thickness on the on the photocurrent and the spectral response. It was found that the temperature dependence of these parameters increases with decreasing photoactive layer thickness. A possible explanation for this phenomenon is also presented.
{"title":"Influence of the photoactive layer thickness on the device parameters and their temperature dependence in thin crystalline silicon photovoltaic devices","authors":"B. Plesz, J. Mizsei","doi":"10.1109/THERMINIC.2016.7749073","DOIUrl":"https://doi.org/10.1109/THERMINIC.2016.7749073","url":null,"abstract":"One of nowadays crucial questions with crystalline silicon solar cells is the reduction of manufacturing costs. One possible concept of reducing cost is to produce solar cells with thin photoactive layers, in order to use less amount of good quality and thus expensive raw material. In addition photovoltaic devices are one of the most obvious solutions for on-chip energy harvesting. There are basically two approaches: the monolithically integrated photovoltaic devices, and photovoltaic devices that are attached to the chip surface and connected to the integrated circuit. These devices also feature a thin photoactive layer in the majority of the cases. This paper aims to investigate the influence of the photoactive layer thickness on the on the photocurrent and the spectral response. It was found that the temperature dependence of these parameters increases with decreasing photoactive layer thickness. A possible explanation for this phenomenon is also presented.","PeriodicalId":143150,"journal":{"name":"2016 22nd International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125226655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/THERMINIC.2016.7749038
J. Ordonez-Miranda, M. A. Ras, B. Wunderle, S. Volz
The effective thermal conductivity of composites made up of silver micro-particles embedded in a resin matrix is modelled and measured. This is done for spherical and flake-like particles to analyse the effects of the particles geometry and concentration on the composite thermal performance. It is experimentally found that spherical particles yield a higher thermal conductivity than the one given by flakes, such that it takes the value of 16 Wm-1 K-1 for a 50% volume fraction of particles. Furthermore, this behaviour is well described by a simple and analytical model, which takes into account the particle-particle interactions through a crowding factor. The obtained results could be useful to optimize the design and manufacture of composites with metallic particles.
{"title":"Modelling and measurement of the thermal conductivity of composites with silver particles","authors":"J. Ordonez-Miranda, M. A. Ras, B. Wunderle, S. Volz","doi":"10.1109/THERMINIC.2016.7749038","DOIUrl":"https://doi.org/10.1109/THERMINIC.2016.7749038","url":null,"abstract":"The effective thermal conductivity of composites made up of silver micro-particles embedded in a resin matrix is modelled and measured. This is done for spherical and flake-like particles to analyse the effects of the particles geometry and concentration on the composite thermal performance. It is experimentally found that spherical particles yield a higher thermal conductivity than the one given by flakes, such that it takes the value of 16 Wm-1 K-1 for a 50% volume fraction of particles. Furthermore, this behaviour is well described by a simple and analytical model, which takes into account the particle-particle interactions through a crowding factor. The obtained results could be useful to optimize the design and manufacture of composites with metallic particles.","PeriodicalId":143150,"journal":{"name":"2016 22nd International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128735621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/THERMINIC.2016.7749078
A. Kozlov
The method of modelling the temperature and heat flux distribution in the structure consisting of the heat flux sensor and the object with the investigated heat flux is presented. In the structure, the domain of modelling is marked out and is replaced by the equivalent structure with three rectangular regions. For each region, the analytical expression for the temperature distribution is determined using the eigenfunction method. Heat flux densities on boundaries of regions are defined as the sums of orthogonal functions with unknown weighting coefficients. To find the unknown weighting coefficients the boundary conditions on boundaries of the regions are used. In general, the determination of the weighting coefficients is reduced to solving a system of linear equations. The present method is applied to determine the temperature distribution in the structure with the heat flux sensor and the thermally conductive wall and the heat flux densities on their surfaces.
{"title":"Modelling of thermal processes in heat flux sensors","authors":"A. Kozlov","doi":"10.1109/THERMINIC.2016.7749078","DOIUrl":"https://doi.org/10.1109/THERMINIC.2016.7749078","url":null,"abstract":"The method of modelling the temperature and heat flux distribution in the structure consisting of the heat flux sensor and the object with the investigated heat flux is presented. In the structure, the domain of modelling is marked out and is replaced by the equivalent structure with three rectangular regions. For each region, the analytical expression for the temperature distribution is determined using the eigenfunction method. Heat flux densities on boundaries of regions are defined as the sums of orthogonal functions with unknown weighting coefficients. To find the unknown weighting coefficients the boundary conditions on boundaries of the regions are used. In general, the determination of the weighting coefficients is reduced to solving a system of linear equations. The present method is applied to determine the temperature distribution in the structure with the heat flux sensor and the thermally conductive wall and the heat flux densities on their surfaces.","PeriodicalId":143150,"journal":{"name":"2016 22nd International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124596940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/THERMINIC.2016.7749034
M. Stan, Ke Wang, K. Skadron
The semiconductor industry is poised to continue the historic Moore's law trend of doubling the level of integration every 1.5-2 years, even as the virtuous cycle benefits of Dennard scaling are quickly vanishing. Once devices no longer scale laterally, the only way to continue to increase areal density is by going vertical using 3D-IC. However, 3D-IC raises several fundamental difficulties in addition to the clear fabrication challenges: as the number of physical layers in a 3D-IC stack increases, from the present 2.5D multi-layer solutions (with an interposer, or only a couple of layers), to true 3D many-layer stacks, the energy cycle problem of delivering power to and removing heat from the 3D stack become daunting. The main reason for this power wall is the mismatch between the volumetric (cubic) power consumption and heat dissipation in 3D-IC, and the areal (quadratic) power delivery and heat removal through a 2D surface (top and/or bottom of the stack). In this paper we propose MultiSpot, a framework to provide fundamental solutions to the 3D-IC power wall that are also practical.
{"title":"Closing the power delivery/heat removal cycle for heterogeneous multi-scale systems","authors":"M. Stan, Ke Wang, K. Skadron","doi":"10.1109/THERMINIC.2016.7749034","DOIUrl":"https://doi.org/10.1109/THERMINIC.2016.7749034","url":null,"abstract":"The semiconductor industry is poised to continue the historic Moore's law trend of doubling the level of integration every 1.5-2 years, even as the virtuous cycle benefits of Dennard scaling are quickly vanishing. Once devices no longer scale laterally, the only way to continue to increase areal density is by going vertical using 3D-IC. However, 3D-IC raises several fundamental difficulties in addition to the clear fabrication challenges: as the number of physical layers in a 3D-IC stack increases, from the present 2.5D multi-layer solutions (with an interposer, or only a couple of layers), to true 3D many-layer stacks, the energy cycle problem of delivering power to and removing heat from the 3D stack become daunting. The main reason for this power wall is the mismatch between the volumetric (cubic) power consumption and heat dissipation in 3D-IC, and the areal (quadratic) power delivery and heat removal through a 2D surface (top and/or bottom of the stack). In this paper we propose MultiSpot, a framework to provide fundamental solutions to the 3D-IC power wall that are also practical.","PeriodicalId":143150,"journal":{"name":"2016 22nd International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127899919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/THERMINIC.2016.7749056
N. Peter, Péter Tóth, Boldizsár Kovács, G. Kristóf
Polymeric materials are often used in assembling and packaging MEMS devices. Polymers are prone to absorb moisture which can lead to reliability issues and different types of failures of the package. In contrast to the IC components cavities are usually essential part of the MEMS devices. The gas tightness of these cavities must be ensured for proper operation. This paper presents an extension of the moisture diffusion simulation methodology towards gas filled cavities embedded in multi material systems. The formulation involves the transformation of convection diffusion vapour transport equation into the form of a general transport equation which is solved by a commercially available simulation package. The implementation allows the coupling of additional physical models to the simulation such as condensation models.
{"title":"Implementation of moisture diffusion model in multi-material system including air cavities","authors":"N. Peter, Péter Tóth, Boldizsár Kovács, G. Kristóf","doi":"10.1109/THERMINIC.2016.7749056","DOIUrl":"https://doi.org/10.1109/THERMINIC.2016.7749056","url":null,"abstract":"Polymeric materials are often used in assembling and packaging MEMS devices. Polymers are prone to absorb moisture which can lead to reliability issues and different types of failures of the package. In contrast to the IC components cavities are usually essential part of the MEMS devices. The gas tightness of these cavities must be ensured for proper operation. This paper presents an extension of the moisture diffusion simulation methodology towards gas filled cavities embedded in multi material systems. The formulation involves the transformation of convection diffusion vapour transport equation into the form of a general transport equation which is solved by a commercially available simulation package. The implementation allows the coupling of additional physical models to the simulation such as condensation models.","PeriodicalId":143150,"journal":{"name":"2016 22nd International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130039548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/THERMINIC.2016.7749043
R. Bornoff, J. Parry, John Wilson
Typical Heatsink design includes deciding base and fin thickness, fin height, and fin gap optimization. In situations where material cost or mass of the heat sink are also a design priority, further optimization with respect to mass removal can be significant. This paper discusses a `Subtractive Design' method to further evolve the heat sink topology by the systematic removal of heat sink mass where the Thermal BottleNeck (BN) Number [1] was found to be lowest. The aim is to identify topologies that optimise the use of material but do not unduly affect thermal performance.
{"title":"A novel approach to Heatsink mass minimisation","authors":"R. Bornoff, J. Parry, John Wilson","doi":"10.1109/THERMINIC.2016.7749043","DOIUrl":"https://doi.org/10.1109/THERMINIC.2016.7749043","url":null,"abstract":"Typical Heatsink design includes deciding base and fin thickness, fin height, and fin gap optimization. In situations where material cost or mass of the heat sink are also a design priority, further optimization with respect to mass removal can be significant. This paper discusses a `Subtractive Design' method to further evolve the heat sink topology by the systematic removal of heat sink mass where the Thermal BottleNeck (BN) Number [1] was found to be lowest. The aim is to identify topologies that optimise the use of material but do not unduly affect thermal performance.","PeriodicalId":143150,"journal":{"name":"2016 22nd International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131165712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/THERMINIC.2016.7749047
J. Maquet
We are presenting a methodology to optimize the design of a thermally challenging Single Board Computer (SBC) in order to achieve ambitious thermal management goals at reasonable cost. The case study presented describes the design of a conduction cooled SBC in 6U-VPX [1] form factor, dissipating up to 130 W (2 high performance CPUs) and presenting a high density of components (ca 4500 on 640cm2). In order to achieve high reliability (low MTBF), all components must be operated at least 5°C below their maximum rating, while the board's thermal interface, i.e. the upper and lower board edges, are kept at 85°C. Any “active” cooling (including heat pipes) is prohibited. This puts tight constraints on the allowable temperature gradients between the board edges and any of the thermally critical components. It turns out that a heat frame design based on advanced composite materials (aluminium, copper and graphite) can meet these constraints even in the presence of layout constraints that impose a less-than-optimal placement of thermally critical components.
{"title":"Methodology to achieve the thermal management of a 6U conduction-cooled board with 130W power dissipation and an operating temperature of 85°C","authors":"J. Maquet","doi":"10.1109/THERMINIC.2016.7749047","DOIUrl":"https://doi.org/10.1109/THERMINIC.2016.7749047","url":null,"abstract":"We are presenting a methodology to optimize the design of a thermally challenging Single Board Computer (SBC) in order to achieve ambitious thermal management goals at reasonable cost. The case study presented describes the design of a conduction cooled SBC in 6U-VPX [1] form factor, dissipating up to 130 W (2 high performance CPUs) and presenting a high density of components (ca 4500 on 640cm2). In order to achieve high reliability (low MTBF), all components must be operated at least 5°C below their maximum rating, while the board's thermal interface, i.e. the upper and lower board edges, are kept at 85°C. Any “active” cooling (including heat pipes) is prohibited. This puts tight constraints on the allowable temperature gradients between the board edges and any of the thermally critical components. It turns out that a heat frame design based on advanced composite materials (aluminium, copper and graphite) can meet these constraints even in the presence of layout constraints that impose a less-than-optimal placement of thermally critical components.","PeriodicalId":143150,"journal":{"name":"2016 22nd International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131903315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/THERMINIC.2016.7749065
Charles-Alexis Lefebvre, Leire Rubio, Jose Luis Montero
The impact of the temperature is one of the most critical issues when designing an industrial embedded systems. Plenty of them are centered on a System-on-Chip, composed of a programmable logic similar to a FPGA and a processing system with one or more processors. Ring oscillators are often used to measure physical parameter such as the temperature in a FPGA. Therefore, this paper presents a ring-oscillator-based digital temperature sensor implemented as an AXI-Lite Intellectual Property on a Xilinx Zynq Z-7020 28 nm System-on-Chip. Both the impact of the measurement time and the number of gates are studied with the objective of getting a fast sensor to give the chip a fast thermal protection. The sensor is then calibrated with a thermal chamber. As a conclusion, even though its architecture is somewhat different from past works, the designed sensor was found to be functional for the targeted application.
{"title":"Digital thermal sensor based on ring-oscillators in Zynq SoC technology","authors":"Charles-Alexis Lefebvre, Leire Rubio, Jose Luis Montero","doi":"10.1109/THERMINIC.2016.7749065","DOIUrl":"https://doi.org/10.1109/THERMINIC.2016.7749065","url":null,"abstract":"The impact of the temperature is one of the most critical issues when designing an industrial embedded systems. Plenty of them are centered on a System-on-Chip, composed of a programmable logic similar to a FPGA and a processing system with one or more processors. Ring oscillators are often used to measure physical parameter such as the temperature in a FPGA. Therefore, this paper presents a ring-oscillator-based digital temperature sensor implemented as an AXI-Lite Intellectual Property on a Xilinx Zynq Z-7020 28 nm System-on-Chip. Both the impact of the measurement time and the number of gates are studied with the objective of getting a fast sensor to give the chip a fast thermal protection. The sensor is then calibrated with a thermal chamber. As a conclusion, even though its architecture is somewhat different from past works, the designed sensor was found to be functional for the targeted application.","PeriodicalId":143150,"journal":{"name":"2016 22nd International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129651212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/THERMINIC.2016.7749063
Tung Ching Lui, B. Muthuraman
Wafer Level Chip Scale Package (WLCSP) is one of the most compact packages which provide good electrical and thermal performance depending on the reliability of the solder joint interconnections to the printed circuit board (PCB). Due to rapid advancements in integrated circuit (IC) fabrication, lower cost per die is achieved when the die count per wafer is high. With the number of IOs (input/output) per die increase which induces the die size and distance to neutral point also increases. Board-level reliability is always a main concern for WLCSP especially without underfill (UF). A common failure mechanism would be solder joint fatigue due to the coefficient of thermal expansion (CTE) mismatch. This would become worse by increasing the distance-to-neutral point (DNP). To improve the reliability, understanding of DNP limitation is necessary. In this paper, different wafer level package configurations are analysed through thermo-mechanical finite element method (FEM) simulation and validated with the thermal cyclic test.
{"title":"Relibability assessment of wafer level chip scale package (WLCSP) based on distance-to-neutral point (DNP)","authors":"Tung Ching Lui, B. Muthuraman","doi":"10.1109/THERMINIC.2016.7749063","DOIUrl":"https://doi.org/10.1109/THERMINIC.2016.7749063","url":null,"abstract":"Wafer Level Chip Scale Package (WLCSP) is one of the most compact packages which provide good electrical and thermal performance depending on the reliability of the solder joint interconnections to the printed circuit board (PCB). Due to rapid advancements in integrated circuit (IC) fabrication, lower cost per die is achieved when the die count per wafer is high. With the number of IOs (input/output) per die increase which induces the die size and distance to neutral point also increases. Board-level reliability is always a main concern for WLCSP especially without underfill (UF). A common failure mechanism would be solder joint fatigue due to the coefficient of thermal expansion (CTE) mismatch. This would become worse by increasing the distance-to-neutral point (DNP). To improve the reliability, understanding of DNP limitation is necessary. In this paper, different wafer level package configurations are analysed through thermo-mechanical finite element method (FEM) simulation and validated with the thermal cyclic test.","PeriodicalId":143150,"journal":{"name":"2016 22nd International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130109819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/THERMINIC.2016.7749079
A. Cardoso, Hugo Barros, G. Hantos
The leading Fan-Out Wafer-Level Packaging technology, WLFO by NANIUM, stemmed from Infineon's embedded Wafer-Level BGA (eWLB) technology, has limited heat dissipation capability, as the materials used in, namely the epoxy mold compound (EMC), originally aimed process ability and mechanical stability, but not heat conduction. As WLFO technology expands to WLSiP (Wafer-Level System-in-Package) for very high-density system integration, the thermal performance becomes a critical factor. In a broader scope, improving heat dissipation capabilities opens WLFO technology platform to power applications. The main challenge for power dissipation on WLSiP packaging is that the EMC must be electrical insulator, placing challenges on both heat conduction and bonding to metallic heat spreader. Whereas mold compounds are typically organic resins filled with inorganic fillers, high performance thermal interface material (TIM) are designed for metal-metal interfaces, not for organic-metal interface as required for chip backside overmolded WLFO package. Another challenge is the assembly of an integrated heatsink, over and larger than the package, on a volume manufacturing capable process, to yield both good thermal conduction and reliable thermomechanical bonding. The work done is part of the collaborative European FP7-ICT project NANOTHERM (Innovative Nano and Micro Technologies for Advanced Thermo and Mechanical Interfaces), together with a consortium of leading IDM, OEM, OSAT, material suppliers and academic/institutes.
{"title":"Fabrication, performance and reliability of a thermally enhanced wafer level fan out demonstrator with integrated heatsink","authors":"A. Cardoso, Hugo Barros, G. Hantos","doi":"10.1109/THERMINIC.2016.7749079","DOIUrl":"https://doi.org/10.1109/THERMINIC.2016.7749079","url":null,"abstract":"The leading Fan-Out Wafer-Level Packaging technology, WLFO by NANIUM, stemmed from Infineon's embedded Wafer-Level BGA (eWLB) technology, has limited heat dissipation capability, as the materials used in, namely the epoxy mold compound (EMC), originally aimed process ability and mechanical stability, but not heat conduction. As WLFO technology expands to WLSiP (Wafer-Level System-in-Package) for very high-density system integration, the thermal performance becomes a critical factor. In a broader scope, improving heat dissipation capabilities opens WLFO technology platform to power applications. The main challenge for power dissipation on WLSiP packaging is that the EMC must be electrical insulator, placing challenges on both heat conduction and bonding to metallic heat spreader. Whereas mold compounds are typically organic resins filled with inorganic fillers, high performance thermal interface material (TIM) are designed for metal-metal interfaces, not for organic-metal interface as required for chip backside overmolded WLFO package. Another challenge is the assembly of an integrated heatsink, over and larger than the package, on a volume manufacturing capable process, to yield both good thermal conduction and reliable thermomechanical bonding. The work done is part of the collaborative European FP7-ICT project NANOTHERM (Innovative Nano and Micro Technologies for Advanced Thermo and Mechanical Interfaces), together with a consortium of leading IDM, OEM, OSAT, material suppliers and academic/institutes.","PeriodicalId":143150,"journal":{"name":"2016 22nd International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131004995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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