We present a lightweight scheme for watermarking or annotating video clips with information describing the workload that would be incurred while decoding the clip. This information can be used at run time to scale the operating voltage/frequency of the processor on which the video clip is to be decoded. Our main contribution is a fast, low-cost bitstream analysis technique for estimating the decoding workload of a video clip. Using this technique the workload information can be inserted into a clip while it is being downloaded onto a battery-powered portable device from a desktop computer or a server, for later playback. In contrast to control-theoretic feedback techniques that have been traditionally used for predicting video decoding workload at runtime for dynamic voltage/frequency scaling, we show that our scheme performs better in terms of energy savings and has significantly lower buffer requirements.
{"title":"Watermarking Video Clips with Workload Information for DVS","authors":"Yicheng Huang, S. Chakraborty, Ye Wang","doi":"10.1109/VLSI.2008.103","DOIUrl":"https://doi.org/10.1109/VLSI.2008.103","url":null,"abstract":"We present a lightweight scheme for watermarking or annotating video clips with information describing the workload that would be incurred while decoding the clip. This information can be used at run time to scale the operating voltage/frequency of the processor on which the video clip is to be decoded. Our main contribution is a fast, low-cost bitstream analysis technique for estimating the decoding workload of a video clip. Using this technique the workload information can be inserted into a clip while it is being downloaded onto a battery-powered portable device from a desktop computer or a server, for later playback. In contrast to control-theoretic feedback techniques that have been traditionally used for predicting video decoding workload at runtime for dynamic voltage/frequency scaling, we show that our scheme performs better in terms of energy savings and has significantly lower buffer requirements.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131266287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. O. Simsir, S. Cadambi, Franjo Ivancic, M. Rötteler, N. Jha
Architectures based on nanoscale molecular devices are attracting attention for replacing CMOS architectures at the end of the semiconductor roadmap. The two most promising nanotechnologies, according to ITRS, are silicon nanowires and carbon nanotubes. Although they offer unmatched densities for building logic, interconnect and memory, they suffer from very defect-prone manufacturing processes. This is further exacerbated by testing complexities where it is nearly impossible to detect all defects in a large nanoscale chip. Furthermore, the small structures in nanoscale architectures are susceptible to transient faults which can produce arbitrary soft errors. As a result, fault tolerance is necessary to make nanoscale architectures practical and realistic. We propose an architecture that can tolerate a large number of undetected manufacturing faults as well as a large rate of transient faults. Our architecture is characterized by multiple levels of redundancy and majority voting to correct errors caused by such faults. A key aspect of the architecture is that it contains a judicious balance of both nanoscale and traditional CMOS components. A companion to the architecture is a compiler with heuristics tailored to quickly and compactly map logic onto partially defective components. Experimental results demonstrate the efficacy of the architecture.
{"title":"Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture","authors":"M. O. Simsir, S. Cadambi, Franjo Ivancic, M. Rötteler, N. Jha","doi":"10.1109/VLSI.2008.71","DOIUrl":"https://doi.org/10.1109/VLSI.2008.71","url":null,"abstract":"Architectures based on nanoscale molecular devices are attracting attention for replacing CMOS architectures at the end of the semiconductor roadmap. The two most promising nanotechnologies, according to ITRS, are silicon nanowires and carbon nanotubes. Although they offer unmatched densities for building logic, interconnect and memory, they suffer from very defect-prone manufacturing processes. This is further exacerbated by testing complexities where it is nearly impossible to detect all defects in a large nanoscale chip. Furthermore, the small structures in nanoscale architectures are susceptible to transient faults which can produce arbitrary soft errors. As a result, fault tolerance is necessary to make nanoscale architectures practical and realistic. We propose an architecture that can tolerate a large number of undetected manufacturing faults as well as a large rate of transient faults. Our architecture is characterized by multiple levels of redundancy and majority voting to correct errors caused by such faults. A key aspect of the architecture is that it contains a judicious balance of both nanoscale and traditional CMOS components. A companion to the architecture is a compiler with heuristics tailored to quickly and compactly map logic onto partially defective components. Experimental results demonstrate the efficacy of the architecture.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133376824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.
{"title":"Memory Architecture Exploration Framework for Cache Based Embedded SOC","authors":"T. Kumar, C. Ravikumar, R. Govindarajan","doi":"10.1109/VLSI.2008.113","DOIUrl":"https://doi.org/10.1109/VLSI.2008.113","url":null,"abstract":"Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133146007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Chauhan, D. Tsamados, N. Abelé, Christoph Eggimann, M. Declercq, A. Ionescu
For the first time, a compact model for suspended gate (SG) FET valid for entire bias range is proposed. The model is capable of simulating both pull-in and pull-out effects, which are the two important phenomena of this device. A novel hybrid numerical simulation approach combining ANSYS Multiphysics and ISE-DESSIS in a self-consistent system is developed. The model is then validated on this numerical device simulation of SGFET. The model shows excellent performance over the entire drain and gate voltage range. The model has been implemented in Verilog-A code and tested on ELDO and Spectre simulators, which makes it useful for circuit simulations using SGFET devices.
{"title":"Compact Modeling of Suspended Gate FET","authors":"Y. Chauhan, D. Tsamados, N. Abelé, Christoph Eggimann, M. Declercq, A. Ionescu","doi":"10.1109/VLSI.2008.11","DOIUrl":"https://doi.org/10.1109/VLSI.2008.11","url":null,"abstract":"For the first time, a compact model for suspended gate (SG) FET valid for entire bias range is proposed. The model is capable of simulating both pull-in and pull-out effects, which are the two important phenomena of this device. A novel hybrid numerical simulation approach combining ANSYS Multiphysics and ISE-DESSIS in a self-consistent system is developed. The model is then validated on this numerical device simulation of SGFET. The model shows excellent performance over the entire drain and gate voltage range. The model has been implemented in Verilog-A code and tested on ELDO and Spectre simulators, which makes it useful for circuit simulations using SGFET devices.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130301916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Aditya Jagirdar, Roystein Oliveira, T. Chakraborty
Soft-errors are a leading cause of reliability issues during field operations. High-energy particles, either from cosmic rays or from impurities in the packaging material can disrupt charge stored on the internal node capacitances leading to a malfunction of the device. Although this is usually a temporary effect, it may lead to Silent Data Corruption(SDC) when not detected in time. SDC may be detrimental to many real-time commercial applications of the device and demands an effective solution that is cheap in terms of various design overheads. In this paper, we propose two novel flip-flop designs aimed at detecting and correcting soft-errors and transients from combinational circuits.Each design is optimized for a different set of constraints and they have area overheads of 40% and 21% as compared to the standard industrial design of a scan flip- flop.
{"title":"A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits","authors":"Aditya Jagirdar, Roystein Oliveira, T. Chakraborty","doi":"10.1109/VLSI.2008.99","DOIUrl":"https://doi.org/10.1109/VLSI.2008.99","url":null,"abstract":"Soft-errors are a leading cause of reliability issues during field operations. High-energy particles, either from cosmic rays or from impurities in the packaging material can disrupt charge stored on the internal node capacitances leading to a malfunction of the device. Although this is usually a temporary effect, it may lead to Silent Data Corruption(SDC) when not detected in time. SDC may be detrimental to many real-time commercial applications of the device and demands an effective solution that is cheap in terms of various design overheads. In this paper, we propose two novel flip-flop designs aimed at detecting and correcting soft-errors and transients from combinational circuits.Each design is optimized for a different set of constraints and they have area overheads of 40% and 21% as compared to the standard industrial design of a scan flip- flop.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114015473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Today's customizable processors allow the to augment the base processor with custom accelerators. By choosing appropriate set of accelerators, designer can significantly enhance the performance and power of an application. Due to the large number of accelerator choices and their complex trade-offs among reuse, gain and area, manually deciding the optimal combination of accelerators is quite cumbersome and time consuming. This calls for CAD tools that select optimal combination of accelerators by thoroughly searching the entire design space. The term pattern is commonly used to represent the computation performed by a custom accelerator. In this paper, we propose an algorithm for rapidly enumerating all the legal patterns taking into account several constraints posed by a typical micro-architecture. The proposed algorithm achieves significant reduction in run-time by a) enumerating the patterns in the increasing order of sizes and b) relating the characteristics of a (k + 1) node pattern with the characteristics of its k node subgraphs. Also, in scenarios where I/O is not a bottleneck, designer can optionally relax the I/O constraint and our algorithm efficiently enumerates all legal I/O unbound legal patterns. The experimental evidence indicate an order of two run-time speedup over state of the art techniques.
{"title":"Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors","authors":"N. Pothineni, Anshul Kumar, K. Paul","doi":"10.1109/VLSI.2008.93","DOIUrl":"https://doi.org/10.1109/VLSI.2008.93","url":null,"abstract":"Today's customizable processors allow the to augment the base processor with custom accelerators. By choosing appropriate set of accelerators, designer can significantly enhance the performance and power of an application. Due to the large number of accelerator choices and their complex trade-offs among reuse, gain and area, manually deciding the optimal combination of accelerators is quite cumbersome and time consuming. This calls for CAD tools that select optimal combination of accelerators by thoroughly searching the entire design space. The term pattern is commonly used to represent the computation performed by a custom accelerator. In this paper, we propose an algorithm for rapidly enumerating all the legal patterns taking into account several constraints posed by a typical micro-architecture. The proposed algorithm achieves significant reduction in run-time by a) enumerating the patterns in the increasing order of sizes and b) relating the characteristics of a (k + 1) node pattern with the characteristics of its k node subgraphs. Also, in scenarios where I/O is not a bottleneck, designer can optionally relax the I/O constraint and our algorithm efficiently enumerates all legal I/O unbound legal patterns. The experimental evidence indicate an order of two run-time speedup over state of the art techniques.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129084832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. This tutorial is about OpenSPARC and provides details on the first chip multi-threading 64-bit, 32-thread microprocessor made available as open source under the GNU General Public License (GPL).
{"title":"OpenSPARC - A Scalable Chip Multi-Threading Design","authors":"Dwayne Lee","doi":"10.1109/VLSI.2008.136","DOIUrl":"https://doi.org/10.1109/VLSI.2008.136","url":null,"abstract":"Summary form only given. This tutorial is about OpenSPARC and provides details on the first chip multi-threading 64-bit, 32-thread microprocessor made available as open source under the GNU General Public License (GPL).","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129150775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As on-chip interconnect in deep-submicron designs contribute to the system-wide power consumption, minimization of interconnect power consumption has become one of the important design issues in deep-submicron technologies. As transition activity mainly determines the interconnect power consumption, several bus encoding techniques have been proposed to minimize the activity. Unlike the existing low-power or energy-efficient bus encoding techniques, in this paper, we propose a scheme which exploits both dynamic voltage scaling and variable cycle transmission mechanisms for minimizing on-chip interconnect energy consumption. We transmit data using variable cycle transmission method and, based on the delay savings achieved through variable cycle transmission method at regular intervals, scale the voltage and frequency to obtain significant energy savings. Using our technique for a 5 mm interconnect wire we achieved energy savings of 30% and 45% over the base case in the address bus and data bus, respectively. Our technique also reduces the energy-delay-product by 34% and 52% for address bus and data bus, respectively.
{"title":"Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design","authors":"T. V. Kalyan, M. Mutyam, V. Pasupureddi","doi":"10.1109/VLSI.2008.15","DOIUrl":"https://doi.org/10.1109/VLSI.2008.15","url":null,"abstract":"As on-chip interconnect in deep-submicron designs contribute to the system-wide power consumption, minimization of interconnect power consumption has become one of the important design issues in deep-submicron technologies. As transition activity mainly determines the interconnect power consumption, several bus encoding techniques have been proposed to minimize the activity. Unlike the existing low-power or energy-efficient bus encoding techniques, in this paper, we propose a scheme which exploits both dynamic voltage scaling and variable cycle transmission mechanisms for minimizing on-chip interconnect energy consumption. We transmit data using variable cycle transmission method and, based on the delay savings achieved through variable cycle transmission method at regular intervals, scale the voltage and frequency to obtain significant energy savings. Using our technique for a 5 mm interconnect wire we achieved energy savings of 30% and 45% over the base case in the address bus and data bus, respectively. Our technique also reduces the energy-delay-product by 34% and 52% for address bus and data bus, respectively.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128495948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The design of inputs and outputs to integrated circuits has traditionally been a straightforward task involving procurement of a specification and its implementation. In the past few technology generations design and implementation of integrated circuit I/O's have become much more complex. Just as Moore's Law predicts that functions per chip will double every 1.5-2 years to keep up with consumer demand, there is a corresponding demand for processing electrical signals at progressively higher rates. The international technology roadmap for semiconductors (ITRS) predicts the I/O bandwidth (Gb/s) for high performance ASICs to be 30 Gb/s by the year 2015. Adding to the complexity is the need to conform to a plethora of emerging I/O specifications and continued focus on reliability regarding electro static discharge (ESD) and simultaneous switching noise (SSN), and the circuit designer has about as much challenges as one can stand. This tutorial presents the techniques and methods employed to build a low power, high bandwidth, highly reliable I/O. It covers the popular signaling standards like LVDS, DDR, XAUI and PCI-Express. Also to be covered are concepts of ESD and Signal Integrity. This section of the tutorial will cover the origins of ESD failures in chips, circuit and layout guidelines to avoid ESD failures and ESD testing procedures. Finally, the tutorial will give a detailed architectural overview of various emerging I/O's such as the DDR, LVDS, and the USB-PHY.
{"title":"Gateway to Chips: High Speed I/O Signalling and Interface","authors":"N. Kumar, S. Velu, Rajan Verma","doi":"10.1109/VLSI.2008.121","DOIUrl":"https://doi.org/10.1109/VLSI.2008.121","url":null,"abstract":"The design of inputs and outputs to integrated circuits has traditionally been a straightforward task involving procurement of a specification and its implementation. In the past few technology generations design and implementation of integrated circuit I/O's have become much more complex. Just as Moore's Law predicts that functions per chip will double every 1.5-2 years to keep up with consumer demand, there is a corresponding demand for processing electrical signals at progressively higher rates. The international technology roadmap for semiconductors (ITRS) predicts the I/O bandwidth (Gb/s) for high performance ASICs to be 30 Gb/s by the year 2015. Adding to the complexity is the need to conform to a plethora of emerging I/O specifications and continued focus on reliability regarding electro static discharge (ESD) and simultaneous switching noise (SSN), and the circuit designer has about as much challenges as one can stand. This tutorial presents the techniques and methods employed to build a low power, high bandwidth, highly reliable I/O. It covers the popular signaling standards like LVDS, DDR, XAUI and PCI-Express. Also to be covered are concepts of ESD and Signal Integrity. This section of the tutorial will cover the origins of ESD failures in chips, circuit and layout guidelines to avoid ESD failures and ESD testing procedures. Finally, the tutorial will give a detailed architectural overview of various emerging I/O's such as the DDR, LVDS, and the USB-PHY.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128612551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of power-aware design methodologies have resulted in potentially significant variations in power consumption under different process, voltage and temperature (PVT) corners. In this paper, we first investigate the impact of PVT corners on power consumption at the System-on-Chip (SoC) level, especially for the on-chip communication infrastructure. Given a target technology library, we then show how it is possible to "scale up" and abstract the PVT variability at the system level, allowing characterization of the PVT-aware design space early in the design flow. We conducted several experiments to estimate power for PVT corner cases, at the gate-level, as well as at the higher system-level. Our preliminary results are very interesting and indicate that: (i) there are significant variations in power consumption across PVT corners, and (ii) the PVT-aware power estimation problem may be amenable to a reasonably simple abstraction at the system-level.
{"title":"Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures","authors":"S. Pasricha, Young-Hwan Park, F. Kurdahi, N. Dutt","doi":"10.1109/VLSI.2008.14","DOIUrl":"https://doi.org/10.1109/VLSI.2008.14","url":null,"abstract":"With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of power-aware design methodologies have resulted in potentially significant variations in power consumption under different process, voltage and temperature (PVT) corners. In this paper, we first investigate the impact of PVT corners on power consumption at the System-on-Chip (SoC) level, especially for the on-chip communication infrastructure. Given a target technology library, we then show how it is possible to \"scale up\" and abstract the PVT variability at the system level, allowing characterization of the PVT-aware design space early in the design flow. We conducted several experiments to estimate power for PVT corner cases, at the gate-level, as well as at the higher system-level. Our preliminary results are very interesting and indicate that: (i) there are significant variations in power consumption across PVT corners, and (ii) the PVT-aware power estimation problem may be amenable to a reasonably simple abstraction at the system-level.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116974569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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