With extensive use of dynamic voltage scaling (DVS) there is increasing need for voltage scalable models. Similarly, leakage being very sensitive to temperature motivates the need for a temperature scalable model as well. We characterize standard cell libraries for statistical leakage analysis based on models for transistor stacks. Modeling stacks has the advantage of using a single model across many gates there by reducing the number of models that need to be characterized. Our experiments on 15 different gates show that we needed only 23 models to predict the leakage across 126 input vector combinations. We investigate the use of neural networks for the combined PVT model, for the stacks, which can capture the effect of inter die, intra gate variations, supply voltage(0.6-1.2 V) and temperature (0 - 100degC) on leakage. Results show that neural network based stack models can predict the PDF of leakage current across supply voltage and temperature accurately with the average error in mean being less than 2% and that in standard deviation being less than 5% across a range of voltage, temperature.
{"title":"Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization","authors":"Janakiraman Viraraghavan, B. P. Das, B. Amrutur","doi":"10.1109/VLSI.2008.38","DOIUrl":"https://doi.org/10.1109/VLSI.2008.38","url":null,"abstract":"With extensive use of dynamic voltage scaling (DVS) there is increasing need for voltage scalable models. Similarly, leakage being very sensitive to temperature motivates the need for a temperature scalable model as well. We characterize standard cell libraries for statistical leakage analysis based on models for transistor stacks. Modeling stacks has the advantage of using a single model across many gates there by reducing the number of models that need to be characterized. Our experiments on 15 different gates show that we needed only 23 models to predict the leakage across 126 input vector combinations. We investigate the use of neural networks for the combined PVT model, for the stacks, which can capture the effect of inter die, intra gate variations, supply voltage(0.6-1.2 V) and temperature (0 - 100degC) on leakage. Results show that neural network based stack models can predict the PDF of leakage current across supply voltage and temperature accurately with the average error in mean being less than 2% and that in standard deviation being less than 5% across a range of voltage, temperature.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129812178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In recent years, Differential Power Analysis (DPA) attack has become a major threat to the security of embedded cryptographic ICs (secure ICs) like smart cards. DPA attack is a powerful side-channel attack. During a DPA attack, the attacker uses power consumption measurements from the secure IC and statistical techniques to correlate the power consumption information leaked with the secret key stored in the secure IC, thus retrieving the secret key, and effectively breaking the secure IC. In this paper, we present a Reduced Complementary Dynamic and Differential Logic (RCDDL) style to design DPA-resistant, secure ICs. RCDDL style ensures that the power consumption of the secure IC remains invariant, and hence, uncorrelated to the input data (secret key). As opposed to existing DDL styles that complement every gate in the uncomplementary logic to generate the differential output, RCDDL style proposes reuse of gates, thus ensuring that a reduced number of gates in the uncomplementary logic are complemented to generate the differential output. Further, we present an analysis of how reduced complementation is achieved while maintaining the capacitance and switching requirements for power invariance. To evaluate the proposed logic style, we built a set of logic gates typically used to design secure ICs. Experiments on a set of circuits, designed using the set of RCDDL gates, show significant improvements in security strength, power consumption and area.
{"title":"Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-Resistant Secure IC Design","authors":"S. Rammohan, V. Sundaresan, R. Vemuri","doi":"10.1109/VLSI.2008.77","DOIUrl":"https://doi.org/10.1109/VLSI.2008.77","url":null,"abstract":"In recent years, Differential Power Analysis (DPA) attack has become a major threat to the security of embedded cryptographic ICs (secure ICs) like smart cards. DPA attack is a powerful side-channel attack. During a DPA attack, the attacker uses power consumption measurements from the secure IC and statistical techniques to correlate the power consumption information leaked with the secret key stored in the secure IC, thus retrieving the secret key, and effectively breaking the secure IC. In this paper, we present a Reduced Complementary Dynamic and Differential Logic (RCDDL) style to design DPA-resistant, secure ICs. RCDDL style ensures that the power consumption of the secure IC remains invariant, and hence, uncorrelated to the input data (secret key). As opposed to existing DDL styles that complement every gate in the uncomplementary logic to generate the differential output, RCDDL style proposes reuse of gates, thus ensuring that a reduced number of gates in the uncomplementary logic are complemented to generate the differential output. Further, we present an analysis of how reduced complementation is achieved while maintaining the capacitance and switching requirements for power invariance. To evaluate the proposed logic style, we built a set of logic gates typically used to design secure ICs. Experiments on a set of circuits, designed using the set of RCDDL gates, show significant improvements in security strength, power consumption and area.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121523106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a modified, inverter based transconductor using double CMOS pair for implementation of Gm-C filters . The advantage of this scheme is that, instead of varying the power supply, the bias voltages at high impedance nodes are varied for frequency (F) tuning. A current steering DAC is proposed for controlling these bias voltages. Another major contribution of this paper is the use of switchable transconductance cell for Q-tuning. This dispenses with the need for two separate biasing circuits (for F and Q tuning). To study the performance of proposed schemes, a bandpass filter is implemented on TSMC-0.18 mum CMOS process using Gm/Id design methodology. The simulation results show a good centre frequency (10 MHz-120 MHz) and pass band (10MH-80MHz) tuning. The proposed approach guarantees the upper bound on THD to be -40 dB for 1 Vw signal swing. The use of inverters with double CMOS pair results in 21 dB higher PSRR compared to those using push pull inverter.
{"title":"VLSI Implementation of a Digitally Tunable Gm-C Filter with Double CMOS Pair","authors":"S. Ramasamy, B. Venkataramani, K. Anbugeetha","doi":"10.1109/VLSI.2008.39","DOIUrl":"https://doi.org/10.1109/VLSI.2008.39","url":null,"abstract":"This paper proposes a modified, inverter based transconductor using double CMOS pair for implementation of Gm-C filters . The advantage of this scheme is that, instead of varying the power supply, the bias voltages at high impedance nodes are varied for frequency (F) tuning. A current steering DAC is proposed for controlling these bias voltages. Another major contribution of this paper is the use of switchable transconductance cell for Q-tuning. This dispenses with the need for two separate biasing circuits (for F and Q tuning). To study the performance of proposed schemes, a bandpass filter is implemented on TSMC-0.18 mum CMOS process using Gm/Id design methodology. The simulation results show a good centre frequency (10 MHz-120 MHz) and pass band (10MH-80MHz) tuning. The proposed approach guarantees the upper bound on THD to be -40 dB for 1 Vw signal swing. The use of inverters with double CMOS pair results in 21 dB higher PSRR compared to those using push pull inverter.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132507979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser diode array, are a type of programmable gate array that can achieve rapid reconfiguration and numerous reconfiguration contexts. The gate array of an ORGA is optically reconfigured using diffraction patterns from a holographic memory that is addressed using a laser diode array. It is noteworthy that ORGA-VLSIs which can be reconfigured in nanoseconds without any overhead have already been fabricated. However, to date, no multi- holographic reconfiguration system that is suitable for such rapidly reconfigurable ORGA-VLSIs without any overhead has ever been developed. As the first step toward realizing such a device, a four-context optical system is demonstrated experimentally using a liquid crystal spatial light modulator and a He-Ne laser. This paper describes those experimental results and plans for future work.
{"title":"An Optical Reconfiguration System with Four Contexts","authors":"N. Yamaguchi, Minoru Watanabe","doi":"10.1109/VLSI.2008.27","DOIUrl":"https://doi.org/10.1109/VLSI.2008.27","url":null,"abstract":"Optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser diode array, are a type of programmable gate array that can achieve rapid reconfiguration and numerous reconfiguration contexts. The gate array of an ORGA is optically reconfigured using diffraction patterns from a holographic memory that is addressed using a laser diode array. It is noteworthy that ORGA-VLSIs which can be reconfigured in nanoseconds without any overhead have already been fabricated. However, to date, no multi- holographic reconfiguration system that is suitable for such rapidly reconfigurable ORGA-VLSIs without any overhead has ever been developed. As the first step toward realizing such a device, a four-context optical system is demonstrated experimentally using a liquid crystal spatial light modulator and a He-Ne laser. This paper describes those experimental results and plans for future work.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128614737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes a dynamic voltage frequency control scheme for a 256 X 64 SRAM block for reducing the energy in active mode and stand-by mode. The DVFM control system monitors the external clock and changes the supply voltage and the body bias so as to achieve a significant reduction in energy. The behavioral model of the proposed DVFM control system algorithm is described and simulated in HDL using delay and energy parameters obtained through SPICE simulation. The frequency range dictated by an external controller is 100 MHz to I GHz. The supply voltage of the complete memory system is varied in steps of 50 mV over the range of 500 mV to IV. The threshold voltage range of operation is plusmn100 mV around the nominal value, achieving 83.4% energy reduction in the active mode and 86.7% in the stand-by mode. This paper also proposes a energy replica that is used in the energy monitor subsystem of the DVFM system.
{"title":"Energy Reduction in SRAM using Dynamic Voltage and Frequency Management","authors":"I. MohammedShareef, P. Nair, B. Amrutur","doi":"10.1109/VLSI.2008.47","DOIUrl":"https://doi.org/10.1109/VLSI.2008.47","url":null,"abstract":"This paper describes a dynamic voltage frequency control scheme for a 256 X 64 SRAM block for reducing the energy in active mode and stand-by mode. The DVFM control system monitors the external clock and changes the supply voltage and the body bias so as to achieve a significant reduction in energy. The behavioral model of the proposed DVFM control system algorithm is described and simulated in HDL using delay and energy parameters obtained through SPICE simulation. The frequency range dictated by an external controller is 100 MHz to I GHz. The supply voltage of the complete memory system is varied in steps of 50 mV over the range of 500 mV to IV. The threshold voltage range of operation is plusmn100 mV around the nominal value, achieving 83.4% energy reduction in the active mode and 86.7% in the stand-by mode. This paper also proposes a energy replica that is used in the energy monitor subsystem of the DVFM system.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126762677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Analog design traditionally relies on designer's knowldge and expertise. Numerous automated synthesis methods have been proposed over the years; they reduce time complexity and explore wider design space. Manufacturing induced defects in the process parameters, render device characteristics inconsistent with their prediced behavior. Device mismatch causes significant variation in analog circuit performance. Monte Carlo simulation is known to be the most accurate method of measuring performance under random variation. But monte-carlo simulation is prohivitively expensive during synthesis process. In this work we present a novel Spline Center and Range Regression (SCRR) technique on adaptive samples to model performance in the presence of process variation. Mismatch aware macromodels can provide considerable speedup during synthesis with minimal loss in accuracy. Experimental results demonstrate the accuracy of the macromodels on an independent validation set using 180nm and 65nm technologies.
{"title":"Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples","authors":"Shubhankar Basu, Balaji Kommineni, R. Vemuri","doi":"10.1109/VLSI.2008.76","DOIUrl":"https://doi.org/10.1109/VLSI.2008.76","url":null,"abstract":"Analog design traditionally relies on designer's knowldge and expertise. Numerous automated synthesis methods have been proposed over the years; they reduce time complexity and explore wider design space. Manufacturing induced defects in the process parameters, render device characteristics inconsistent with their prediced behavior. Device mismatch causes significant variation in analog circuit performance. Monte Carlo simulation is known to be the most accurate method of measuring performance under random variation. But monte-carlo simulation is prohivitively expensive during synthesis process. In this work we present a novel Spline Center and Range Regression (SCRR) technique on adaptive samples to model performance in the presence of process variation. Mismatch aware macromodels can provide considerable speedup during synthesis with minimal loss in accuracy. Experimental results demonstrate the accuracy of the macromodels on an independent validation set using 180nm and 65nm technologies.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124503643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. Design chain standards are all ultimately aimed to make the task of the design integration and manufacture of system on chip products more efficient, improving turn around time, and effective improving quality and yield. Dr Goodenough outlined the standardization activities in which ARM is currently involved {including those managed by Si2 Accellera, SPIRIT, JEDEC, Eclipse, OpenMax OpenGL} and their relevance to the issues of the IP supply chain. He discussed types of standards an their impact on IP. The presentation will also focus on some of the challenges in managing viable standards to broad market acceptance and the consequent need for an integrated roadmap between various standardization activities to give maximum benefit and leverage to the final end customers.
{"title":"Design Automation Standards: The IP Providers Perspective","authors":"J. Goodenough","doi":"10.1109/VLSI.2008.140","DOIUrl":"https://doi.org/10.1109/VLSI.2008.140","url":null,"abstract":"Summary form only given. Design chain standards are all ultimately aimed to make the task of the design integration and manufacture of system on chip products more efficient, improving turn around time, and effective improving quality and yield. Dr Goodenough outlined the standardization activities in which ARM is currently involved {including those managed by Si2 Accellera, SPIRIT, JEDEC, Eclipse, OpenMax OpenGL} and their relevance to the issues of the IP supply chain. He discussed types of standards an their impact on IP. The presentation will also focus on some of the challenges in managing viable standards to broad market acceptance and the consequent need for an integrated roadmap between various standardization activities to give maximum benefit and leverage to the final end customers.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115096442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The last decade has seen a phenomenal increase in the use of electronic components in automotive systems, resulting in the replacement of purely mechanical or hydraulic-implementations of different functionalities. Today, in high-end cars, it is common to have around 70 electronic control units (ECUs), each consisting of programmable processors, one or more microcontrollers and a set of sensors and actuators. Different functionalities (e.g. adaptive cruise control or anti-lock braking) are then implemented in a distributed fashion with parts of a task being mapped onto one or more ECUs and these ECUs exchanging messages and signals via high-speed communication buses. The heterogeneity and the distributed nature of these implementations, coupled with the emergence of new standards and protocols for the automotive domain have given rise to new challenges - both in terms of programming large-scale ECU networks, as well as in evaluating their performance and timing properties. This tutorial will provide a comprehensive overview of the recent developments in this domain and also highlight some of the challenges facing embedded systems designers and programmers. The topics covered will include time-triggered architectures for implementing safety-critical applications, emerging protocols for the automotive domain such as FlexRay, techniques for performance and timing analysis of FlexRay-based ECU networks, and languages and tools for developing distributed implementations of automotive functionality around FlexRay and other related protocols. Apart from discussing the relevant protocols, languages and modelling/analysis techniques, the tutorial will also cover practical case studies and some commercially available tools and their functionality.
{"title":"Programming and Performance Modelling of Automotive ECU Networks","authors":"S. Chakraborty, S. Ramesh","doi":"10.1109/VLSI.2008.131","DOIUrl":"https://doi.org/10.1109/VLSI.2008.131","url":null,"abstract":"The last decade has seen a phenomenal increase in the use of electronic components in automotive systems, resulting in the replacement of purely mechanical or hydraulic-implementations of different functionalities. Today, in high-end cars, it is common to have around 70 electronic control units (ECUs), each consisting of programmable processors, one or more microcontrollers and a set of sensors and actuators. Different functionalities (e.g. adaptive cruise control or anti-lock braking) are then implemented in a distributed fashion with parts of a task being mapped onto one or more ECUs and these ECUs exchanging messages and signals via high-speed communication buses. The heterogeneity and the distributed nature of these implementations, coupled with the emergence of new standards and protocols for the automotive domain have given rise to new challenges - both in terms of programming large-scale ECU networks, as well as in evaluating their performance and timing properties. This tutorial will provide a comprehensive overview of the recent developments in this domain and also highlight some of the challenges facing embedded systems designers and programmers. The topics covered will include time-triggered architectures for implementing safety-critical applications, emerging protocols for the automotive domain such as FlexRay, techniques for performance and timing analysis of FlexRay-based ECU networks, and languages and tools for developing distributed implementations of automotive functionality around FlexRay and other related protocols. Apart from discussing the relevant protocols, languages and modelling/analysis techniques, the tutorial will also cover practical case studies and some commercially available tools and their functionality.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115491182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Logic circuit design with future nanoscale devices using dense and regular fabrics such as crossbar is promising in terms of integration density, performance and power dissipation. Among the emerging alternatives to CMOS, molecular electronics based "diode-resistor logic" has generated considerable interest in recent times. However, some major challenges associated with circuit design using molecular switches are: 1) high defect rate; 2) lack of voltage gain of these switches that prevent logic cascading; and 3) large output voltage level degradation that affect robustness of operation. In this paper, we analyze the issue of input-dependent logic level degradation in diode-resistor style molecular crossbar and develop a simple analytical model for fast and accurate estimation of logic level degradation in a circuit. We also propose a voltage level-aware circuit design technique that limits the worst-case output level degradation. We verify the model by SPICE simulation which shows an average absolute error of less than 2%. Moreover, the proposed design technique improves the logic degradation level from 27% to 7% on an average compared to conventional design.
{"title":"Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits","authors":"R. Chakraborty, Somnath Paul, S. Bhunia","doi":"10.1109/VLSI.2008.44","DOIUrl":"https://doi.org/10.1109/VLSI.2008.44","url":null,"abstract":"Logic circuit design with future nanoscale devices using dense and regular fabrics such as crossbar is promising in terms of integration density, performance and power dissipation. Among the emerging alternatives to CMOS, molecular electronics based \"diode-resistor logic\" has generated considerable interest in recent times. However, some major challenges associated with circuit design using molecular switches are: 1) high defect rate; 2) lack of voltage gain of these switches that prevent logic cascading; and 3) large output voltage level degradation that affect robustness of operation. In this paper, we analyze the issue of input-dependent logic level degradation in diode-resistor style molecular crossbar and develop a simple analytical model for fast and accurate estimation of logic level degradation in a circuit. We also propose a voltage level-aware circuit design technique that limits the worst-case output level degradation. We verify the model by SPICE simulation which shows an average absolute error of less than 2%. Moreover, the proposed design technique improves the logic degradation level from 27% to 7% on an average compared to conventional design.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122466464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Kannan, Aviral Shrivastava, V. Mohan, Sarvesh Bhardwaj, S. Vrudhula
Technology scaling has resulted in an exponential increase in the leakage power as well as the variations in leakage power of fabricated chips. Functional units (FUs), like Integer ALUs are regions of high power density and significantly contribute to the variation in the whole processor power consumption. Hence, it is important to reduce both the power consumption and the variation in power consumption of the FUs. Among existing FU power reduction techniques, power gating (PG) has been most effective. In this paper, we introduce a leakage sensor inside the FUs and propose a temperature and process variation aware power gating scheme, Leakage Aware Power Gating (LA-PG). Our experimental results demonstrate that LA-PG results in 22% reduction in mean and a 25% reduction in standard deviation of the ALU energy consumption when compared to existing power gating techniques, without significant performance penalty.
{"title":"Temperature and Process Variations Aware Power Gating of Functional Units","authors":"D. Kannan, Aviral Shrivastava, V. Mohan, Sarvesh Bhardwaj, S. Vrudhula","doi":"10.1109/VLSI.2008.83","DOIUrl":"https://doi.org/10.1109/VLSI.2008.83","url":null,"abstract":"Technology scaling has resulted in an exponential increase in the leakage power as well as the variations in leakage power of fabricated chips. Functional units (FUs), like Integer ALUs are regions of high power density and significantly contribute to the variation in the whole processor power consumption. Hence, it is important to reduce both the power consumption and the variation in power consumption of the FUs. Among existing FU power reduction techniques, power gating (PG) has been most effective. In this paper, we introduce a leakage sensor inside the FUs and propose a temperature and process variation aware power gating scheme, Leakage Aware Power Gating (LA-PG). Our experimental results demonstrate that LA-PG results in 22% reduction in mean and a 25% reduction in standard deviation of the ALU energy consumption when compared to existing power gating techniques, without significant performance penalty.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124972643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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