A fully differential CMOS sample and hold amplifier SHA) is described here.The circuit is designed as a front end sampler of a low-power, high-speed analog to digital converter. The SHA uses double-sampling technique to achieve high speed with reasonably low power consumption. Using 0.18oc CMOS technology, a resolution of 9 bit has been achieved at a sampling rate of 400 MHz. Also, to acquire superior linearity, boot-strapping technique has been used while implementing the switches and to reduce clock feed through, concept of bottom plate sampling has been utilized. Using a supply voltage of 1.8 V and a signal swing of 0.6Vpp the circuit consumes approximately 10 mW of power.
{"title":"A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier","authors":"Sounak Roy, S. Banerjee","doi":"10.1109/VLSI.2008.78","DOIUrl":"https://doi.org/10.1109/VLSI.2008.78","url":null,"abstract":"A fully differential CMOS sample and hold amplifier SHA) is described here.The circuit is designed as a front end sampler of a low-power, high-speed analog to digital converter. The SHA uses double-sampling technique to achieve high speed with reasonably low power consumption. Using 0.18oc CMOS technology, a resolution of 9 bit has been achieved at a sampling rate of 400 MHz. Also, to acquire superior linearity, boot-strapping technique has been used while implementing the switches and to reduce clock feed through, concept of bottom plate sampling has been utilized. Using a supply voltage of 1.8 V and a signal swing of 0.6Vpp the circuit consumes approximately 10 mW of power.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134646086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Motivated by the potential of reversible computing, we present a systematic method for the designing reversible arithmetic circuits for finite field or Galois fields of form GF(2m). It is shown that an adder over GF(2m) can be designed with m garbage bits and that of a PB multiplier with 2m garbage bits. To tackle the problem of errors in computation, we also extend the circuit with error detection feature. Gate count and technology oriented cost metrics are used for evaluation. The expression for the upper bound for gate size is also derived for special primitive polynomials. Our technique, when compared with existing CAD tool gives the same gate size and quantum cost.
{"title":"Design of Reversible Finite Field Arithmetic Circuits with Error Detection","authors":"J. Mathew, H. Rahaman, B. R. Jose, D. Pradhan","doi":"10.1109/VLSI.2008.96","DOIUrl":"https://doi.org/10.1109/VLSI.2008.96","url":null,"abstract":"Motivated by the potential of reversible computing, we present a systematic method for the designing reversible arithmetic circuits for finite field or Galois fields of form GF(2m). It is shown that an adder over GF(2m) can be designed with m garbage bits and that of a PB multiplier with 2m garbage bits. To tackle the problem of errors in computation, we also extend the circuit with error detection feature. Gate count and technology oriented cost metrics are used for evaluation. The expression for the upper bound for gate size is also derived for special primitive polynomials. Our technique, when compared with existing CAD tool gives the same gate size and quantum cost.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132019904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The IEEE has collaborated with numerous consortia to develop EDA standards for more than a decade. The recent success of new and emerging standards have borrowed from the market- oriented approaches to ensure immediate suppliers of tools and technology that embrace IEEE standards that give consumers confidence they should plan for their immediate use. The SystemVerilog success will be explored and it will be demonstrated how it can apply to other work in the IEEE.
{"title":"IEEE Market-Oriented Standards Process and the EDA Industry","authors":"Dennis Brophy","doi":"10.1109/VLSI.2008.139","DOIUrl":"https://doi.org/10.1109/VLSI.2008.139","url":null,"abstract":"The IEEE has collaborated with numerous consortia to develop EDA standards for more than a decade. The recent success of new and emerging standards have borrowed from the market- oriented approaches to ensure immediate suppliers of tools and technology that embrace IEEE standards that give consumers confidence they should plan for their immediate use. The SystemVerilog success will be explored and it will be demonstrated how it can apply to other work in the IEEE.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114040409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The complexity of today's SoCs and applications are driving the need for faster and more accurate mixed signal verification. Additionally the percentage of analog content in mixed-signal designs is increasing rapidly. This requires a change in mindset: no longer can the analog and digital modules be verified independantly. For these reasons Accellera has been leading the development of the Verilog-AMS standard, to enable accurate mixed signal design verification of systems containing thousands of analog/digital interface connections. The presentation will discuss the recent language enhancements that have been driven by the Verilog-AMS technical committee, to make system level analysis of analog and mixed signal designs much more efficient and accurate.
{"title":"Driving Analog Mixed Signal Verification through Verilog-AMS","authors":"Sri Chandra","doi":"10.1109/VLSI.2008.141","DOIUrl":"https://doi.org/10.1109/VLSI.2008.141","url":null,"abstract":"The complexity of today's SoCs and applications are driving the need for faster and more accurate mixed signal verification. Additionally the percentage of analog content in mixed-signal designs is increasing rapidly. This requires a change in mindset: no longer can the analog and digital modules be verified independantly. For these reasons Accellera has been leading the development of the Verilog-AMS standard, to enable accurate mixed signal design verification of systems containing thousands of analog/digital interface connections. The presentation will discuss the recent language enhancements that have been driven by the Verilog-AMS technical committee, to make system level analysis of analog and mixed signal designs much more efficient and accurate.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114589595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Various non-conventional methods have been employed in the past, to reduce the cost and weight of traditional conducted EMI filters and radiation screens for EMI suppression in switching power electronic converters. This paper points out various shortcomings of these methods which are mainly frequency modulation based, and describes the design of a ramp-generator IC based on a modified modulation scheme. This IC can be used on any voltage mode controlled converter and has a feature that enables the user to tune the same converter to various EMC norms. Test results from a prototype showing significant reduction in harmonic power level have been presented. Moreover, this paper discusses a theoretical formulation for calculating the output capacitor size to maintain ripple specifications, when operating under chaotic modulation.
{"title":"Chaos-Modulated Ramp IC for EMI Reduction in PWM Buck Converters Design and Analysis of Critical Issues","authors":"R. Mukherjee, A. Patra, S. Banerjee","doi":"10.1109/VLSI.2008.58","DOIUrl":"https://doi.org/10.1109/VLSI.2008.58","url":null,"abstract":"Various non-conventional methods have been employed in the past, to reduce the cost and weight of traditional conducted EMI filters and radiation screens for EMI suppression in switching power electronic converters. This paper points out various shortcomings of these methods which are mainly frequency modulation based, and describes the design of a ramp-generator IC based on a modified modulation scheme. This IC can be used on any voltage mode controlled converter and has a feature that enables the user to tune the same converter to various EMC norms. Test results from a prototype showing significant reduction in harmonic power level have been presented. Moreover, this paper discusses a theoretical formulation for calculating the output capacitor size to maintain ripple specifications, when operating under chaotic modulation.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133058105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Optically reconfigurable gate arrays (ORGAs), by exploiting the large storage capacity of holographic memory, offer the possibility of providing a virtual gate count that is much larger than those of currently available VLSI circuits. Because circuits implemented on a gate array must often be changed using virtual circuits stored in a holographic memory, rapid reconfiguration is necessary to reduce the reconfiguration overhead. A simple means to realize a short reconfiguration time in ORGAs is to implement a high-power laser array. However, such an array presents the disadvantages of high power consumption, large implementation space, high cost, and so on. Therefore, this paper presents an acceleration method to increase ORGAs' reconfiguration frequency without the necessity for any increase of laser power. This technique also includes optimization between the number of reconfiguration contexts and the reconfiguration frequency. The description in this paper clarifies the advantages using simulation and experimental results.
{"title":"An Acceleration and Optimization Method for Optical Reconfiguration","authors":"Minoru Watanabe, N. Yamaguchi","doi":"10.1109/VLSI.2008.26","DOIUrl":"https://doi.org/10.1109/VLSI.2008.26","url":null,"abstract":"Optically reconfigurable gate arrays (ORGAs), by exploiting the large storage capacity of holographic memory, offer the possibility of providing a virtual gate count that is much larger than those of currently available VLSI circuits. Because circuits implemented on a gate array must often be changed using virtual circuits stored in a holographic memory, rapid reconfiguration is necessary to reduce the reconfiguration overhead. A simple means to realize a short reconfiguration time in ORGAs is to implement a high-power laser array. However, such an array presents the disadvantages of high power consumption, large implementation space, high cost, and so on. Therefore, this paper presents an acceleration method to increase ORGAs' reconfiguration frequency without the necessity for any increase of laser power. This technique also includes optimization between the number of reconfiguration contexts and the reconfiguration frequency. The description in this paper clarifies the advantages using simulation and experimental results.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116154350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mahshid Sedghi, Elnaz Koopahi, Armin Alaghi, M. Fathy, Z. Navabi
A test strategy for testing NoC switches based on flooding is presented in this paper. This test strategy tests all switch ports and network routes, while it avoids sending a test packet arriving at a switch in every direction. This test strategy is referred to as pseudo-exhaustive, versus the exhaustive testing that sends an incoming test packet of a switch in every direction. As compared with the exhaustive strategy, the pseudo- exhaustive testing consumes lower power consumption, has a lower test time and still has 100% switch port fault coverage. This paper discusses our test strategy, test mode switch hardware requirements, and evaluates test power, time, and coverage.
{"title":"An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations","authors":"Mahshid Sedghi, Elnaz Koopahi, Armin Alaghi, M. Fathy, Z. Navabi","doi":"10.1109/VLSI.2008.111","DOIUrl":"https://doi.org/10.1109/VLSI.2008.111","url":null,"abstract":"A test strategy for testing NoC switches based on flooding is presented in this paper. This test strategy tests all switch ports and network routes, while it avoids sending a test packet arriving at a switch in every direction. This test strategy is referred to as pseudo-exhaustive, versus the exhaustive testing that sends an incoming test packet of a switch in every direction. As compared with the exhaustive strategy, the pseudo- exhaustive testing consumes lower power consumption, has a lower test time and still has 100% switch port fault coverage. This paper discusses our test strategy, test mode switch hardware requirements, and evaluates test power, time, and coverage.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122381185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kyuho Shim, Kesava R. Talupuru, M. Ciesielski, Seiyang Yang
This work is based on a premise that in traditional, simulation-based RTL functional verification reducing total debugging turnaround time (which includes both the simulation execution time and the compilation time) is much more desirable than simply increasing the simulation speed. This is due to the repeated nature of the debugging process, which includes a large number of simulation and compilation steps. While the HDL compilation process is fast, pure HDL simulation suffers from extremely long simulation execution time. On the other hand, HW-assisted simulation acceleration is characterized by fast execution, but suffers from a long HW re-compilation time, required whenever the design is modified for debugging. This paper proposes an efficient HW-assisted simulation acceleration method based on HW re-compilation avoidance, which can significantly reduce the debugging turnaround time, while maintaining its high execution speed.
{"title":"Simulation Acceleration with HW Re-Compilation Avoidance","authors":"Kyuho Shim, Kesava R. Talupuru, M. Ciesielski, Seiyang Yang","doi":"10.1109/VLSI.2008.62","DOIUrl":"https://doi.org/10.1109/VLSI.2008.62","url":null,"abstract":"This work is based on a premise that in traditional, simulation-based RTL functional verification reducing total debugging turnaround time (which includes both the simulation execution time and the compilation time) is much more desirable than simply increasing the simulation speed. This is due to the repeated nature of the debugging process, which includes a large number of simulation and compilation steps. While the HDL compilation process is fast, pure HDL simulation suffers from extremely long simulation execution time. On the other hand, HW-assisted simulation acceleration is characterized by fast execution, but suffers from a long HW re-compilation time, required whenever the design is modified for debugging. This paper proposes an efficient HW-assisted simulation acceleration method based on HW re-compilation avoidance, which can significantly reduce the debugging turnaround time, while maintaining its high execution speed.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127802001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, S. Vrudhula
Continuous technology scaling has resulted in an increase in both, the power density as well as the variation in device dimensions (process variations) of the manufactured processors. Both power density and process variations have a significant impact on the leakage power. Therefore, power optimization techniques should be sensitive to the variation in leakage power due to both temperature as well as process variations. Operation to functional units binding mechanism (OFBM) is the mechanism to dynamically issue operations to functional units (FUs) in superscalar processors. We propose a leakage-aware OFBM (LA-OFBM), which is both temperature and process variation aware. Our experimental results demostrate that LA-OFBM reduces the mean and standard deviation of the total energy consumption of ALUs by 18%, and 46% respectively, as compared to the traditional OFBM, without any performance penalty.
{"title":"Power Reduction of Functional Units Considering Temperature and Process Variations","authors":"D. Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, S. Vrudhula","doi":"10.1109/VLSI.2008.81","DOIUrl":"https://doi.org/10.1109/VLSI.2008.81","url":null,"abstract":"Continuous technology scaling has resulted in an increase in both, the power density as well as the variation in device dimensions (process variations) of the manufactured processors. Both power density and process variations have a significant impact on the leakage power. Therefore, power optimization techniques should be sensitive to the variation in leakage power due to both temperature as well as process variations. Operation to functional units binding mechanism (OFBM) is the mechanism to dynamically issue operations to functional units (FUs) in superscalar processors. We propose a leakage-aware OFBM (LA-OFBM), which is both temperature and process variation aware. Our experimental results demostrate that LA-OFBM reduces the mean and standard deviation of the total energy consumption of ALUs by 18%, and 46% respectively, as compared to the traditional OFBM, without any performance penalty.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129944176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Ramírez-Angulo, L.M. Kalyani-Garimella, A. Garimella, S. Garimella, A. López-Martín, R. Carvajal
A rail-to-rail differential input stage with programmable threshold levels and offset compensation is introduced. Applications for the implementation of differential and double differential comparators are discussed. Experimental results obtained from a MOSIS 0.5 mum CMOS technology test chip are shown that validate rail-to-rail operation with a 1.5 V supply voltage.
介绍了一种具有可编程阈值电平和偏移补偿的轨对轨差分输入级。讨论了微分比较器和双微分比较器的实现应用。在MOSIS 0.5 μ m CMOS技术测试芯片上获得的实验结果表明，在1.5 V电源电压下，可以验证轨道到轨道的运行。
{"title":"An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators","authors":"J. Ramírez-Angulo, L.M. Kalyani-Garimella, A. Garimella, S. Garimella, A. López-Martín, R. Carvajal","doi":"10.1109/VLSI.2008.30","DOIUrl":"https://doi.org/10.1109/VLSI.2008.30","url":null,"abstract":"A rail-to-rail differential input stage with programmable threshold levels and offset compensation is introduced. Applications for the implementation of differential and double differential comparators are discussed. Experimental results obtained from a MOSIS 0.5 mum CMOS technology test chip are shown that validate rail-to-rail operation with a 1.5 V supply voltage.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130456542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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