We present a top-down dynamic power estimation methodology for delay constrained sequential circuits. The methodology works at the register transfer level (RT-Level), and applies to both structural and behavioral descriptions of circuits. The average power consumption of a circuit varies with the worst case cycle-time or frequency of operation. As the cycle-time is reduced, the increase in the capacitance of the circuit due to technology mapping and optimization is captured by our technique at the RT-Level using the principles of logical effort. Switching activity is obtained at the RT-Level visible nodes through RT-Level functional simulation. This information is utilized to approximate the activities at the remaining nodes of the circuit and combined with capacitance to estimate dynamic power. Power estimation results for RT-Level sequential circuits indicate good accuracy (average error<10%) with respect to the reference values obtained by detailed gate-level power analysis. The power consumed by a circuit varies with the target library and technology. Our methodology is parameterizable and the results obtained for different target libraries at 0.18 mum TSMC and 0.13 mum UMC technologies are consistent, indicating the robustness of our technique. The applicability of our methodology in design frameworks consisting of bottom-up techniques is also discussed.
提出了一种自顶向下的时延约束顺序电路动态功率估计方法。该方法在寄存器转移级(rt级)工作，并适用于电路的结构和行为描述。电路的平均功耗随最坏情况下的周期时间或工作频率而变化。随着循环时间的减少，由于技术映射和优化而导致的电路电容的增加被我们的技术在rt级使用逻辑努力原则捕获。通过RT-Level功能仿真，在RT-Level可见节点上获得切换活动。利用这些信息来估计电路剩余节点的活动，并结合电容来估计动态功率。rt级时序电路的功率估计结果表明，与详细的门级功率分析得到的参考值相比，精度较高(平均误差<10%)。电路所消耗的功率随目标库和技术的不同而不同。我们的方法是可参数化的，并且在0.18 μ m TSMC和0.13 μ m UMC技术下获得的不同目标库的结果是一致的，表明我们的技术具有鲁棒性。本文还讨论了我们的方法在由自下而上技术组成的设计框架中的适用性。
{"title":"A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits","authors":"Sriram Sambamurthy, J. Abraham, R. Tupuri","doi":"10.1109/VLSI.2008.56","DOIUrl":"https://doi.org/10.1109/VLSI.2008.56","url":null,"abstract":"We present a top-down dynamic power estimation methodology for delay constrained sequential circuits. The methodology works at the register transfer level (RT-Level), and applies to both structural and behavioral descriptions of circuits. The average power consumption of a circuit varies with the worst case cycle-time or frequency of operation. As the cycle-time is reduced, the increase in the capacitance of the circuit due to technology mapping and optimization is captured by our technique at the RT-Level using the principles of logical effort. Switching activity is obtained at the RT-Level visible nodes through RT-Level functional simulation. This information is utilized to approximate the activities at the remaining nodes of the circuit and combined with capacitance to estimate dynamic power. Power estimation results for RT-Level sequential circuits indicate good accuracy (average error<10%) with respect to the reference values obtained by detailed gate-level power analysis. The power consumed by a circuit varies with the target library and technology. Our methodology is parameterizable and the results obtained for different target libraries at 0.18 mum TSMC and 0.13 mum UMC technologies are consistent, indicating the robustness of our technique. The applicability of our methodology in design frameworks consisting of bottom-up techniques is also discussed.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132269756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Delay defects that degrade performance and cause timing related reliability failures are emerging to be a major concern in nanometer technologies. Extensive at-speed functional testing to screen out such defects can be prohibitively expensive. Scan based structural delay tests are being pursued as a possible cost effective solution to this problem. However, recent research indicates that several formidable challenges must be overcome before such an approach can be fully effective. These include poor delay test coverage, and inaccuracies in the observed circuit timing due to false paths, power supply noise, clock stretching etc. This tutorial aims at a comprehensive discussion of these challenges and proposed solutions, aided by data from recently published industrial studies from Intel, IBM. TI, Freescale, LSI Logic, and universities.
{"title":"Scan Delay Testing of Nanometer SoCs","authors":"A. Singh","doi":"10.1109/VLSI.2008.134","DOIUrl":"https://doi.org/10.1109/VLSI.2008.134","url":null,"abstract":"Delay defects that degrade performance and cause timing related reliability failures are emerging to be a major concern in nanometer technologies. Extensive at-speed functional testing to screen out such defects can be prohibitively expensive. Scan based structural delay tests are being pursued as a possible cost effective solution to this problem. However, recent research indicates that several formidable challenges must be overcome before such an approach can be fully effective. These include poor delay test coverage, and inaccuracies in the observed circuit timing due to false paths, power supply noise, clock stretching etc. This tutorial aims at a comprehensive discussion of these challenges and proposed solutions, aided by data from recently published industrial studies from Intel, IBM. TI, Freescale, LSI Logic, and universities.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116423130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In modern circuits, interconnect efficiency is a central determinant of circuit efficiency. Moreover, as technology is scaled down, the importance of efficient interconnect design is increasing. In this paper, we explore an option for low-power interconnect synthesis at the 32 nm node and beyond, using fin-type field-effect transistors (FinFETs) which are a promising substitute for bulk CMOS at the considered gate lengths. We consider a previously-unexplored mechanism for improving FinFET efficiency, called threshold voltage control through multiple supply voltages (TCMS), which is significantly different from conventional multiple-supply voltage schemes. We develop a circuit design for a FinFET buffer using TCMS. We describe a variation of van Ginneken's classic dynamic programming framework for solving the problem of power-optimal TCMS buffer insertion on a given routing tree. We show that, on an average, TCMS can provide power savings of 50.41% and device area savings of 9.17% compared to a state-of-the-art dual-Vdd interconnect synthesis scheme.
{"title":"Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects","authors":"Anish Muttreja, Prateek Mishra, N. Jha","doi":"10.1109/VLSI.2008.117","DOIUrl":"https://doi.org/10.1109/VLSI.2008.117","url":null,"abstract":"In modern circuits, interconnect efficiency is a central determinant of circuit efficiency. Moreover, as technology is scaled down, the importance of efficient interconnect design is increasing. In this paper, we explore an option for low-power interconnect synthesis at the 32 nm node and beyond, using fin-type field-effect transistors (FinFETs) which are a promising substitute for bulk CMOS at the considered gate lengths. We consider a previously-unexplored mechanism for improving FinFET efficiency, called threshold voltage control through multiple supply voltages (TCMS), which is significantly different from conventional multiple-supply voltage schemes. We develop a circuit design for a FinFET buffer using TCMS. We describe a variation of van Ginneken's classic dynamic programming framework for solving the problem of power-optimal TCMS buffer insertion on a given routing tree. We show that, on an average, TCMS can provide power savings of 50.41% and device area savings of 9.17% compared to a state-of-the-art dual-Vdd interconnect synthesis scheme.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129517472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Adders and multipliers are the most important arithmetic units in a general microprocessor and the major source of power dissipation. Various architecture styles exist to implement these units, each having their own merits and demerits. However, due to continuing integrating intensity and growing needs of portable devices, low power design is of prime importance. In addition, much power is dissipated due to a large number of spurious transitions on internal nodes in power hungry multiplier structures. We present a new full adder structure based on complementary pass transistor logic (CPL) which is faster and more energy efficient than the existing structures. We also propose a new technique of implementing multiplier circuit using decomposition logic which improves speed and reduces power consumption by reducing the spurious transitions on internal nodes. Combined with the new adder structure and the decomposition logic, there is substantial improvement in the performance of the multiplier structures. With the help of these state of the art designs, it would be possible to design highly power efficient processors, especially digital signal processors. We have used TSPICE for simulation in the TSMC 180 nm technology.
{"title":"Energy-Efficient, High Performance Circuits for Arithmetic Units","authors":"S. Agarwal, K. PavankumarV., R. Yokesh","doi":"10.1109/VLSI.2008.49","DOIUrl":"https://doi.org/10.1109/VLSI.2008.49","url":null,"abstract":"Adders and multipliers are the most important arithmetic units in a general microprocessor and the major source of power dissipation. Various architecture styles exist to implement these units, each having their own merits and demerits. However, due to continuing integrating intensity and growing needs of portable devices, low power design is of prime importance. In addition, much power is dissipated due to a large number of spurious transitions on internal nodes in power hungry multiplier structures. We present a new full adder structure based on complementary pass transistor logic (CPL) which is faster and more energy efficient than the existing structures. We also propose a new technique of implementing multiplier circuit using decomposition logic which improves speed and reduces power consumption by reducing the spurious transitions on internal nodes. Combined with the new adder structure and the decomposition logic, there is substantial improvement in the performance of the multiplier structures. With the help of these state of the art designs, it would be possible to design highly power efficient processors, especially digital signal processors. We have used TSPICE for simulation in the TSMC 180 nm technology.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127066225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Accellera's (www.accellera.orq) mission is to drive worldwide development and use of standards required by systems, semiconductors and design tools companies, which enhance a language based design automation process. Overview of different standards from Accellera and how they fit into the design flow process will be presented. Status of various technical sub-committees like Open Compression Interface (OCI), Unified Power Format (UPF), Unified Coverage Interoperatbility (UCIS) and Open Verification Library(OVL) will also be covered.
{"title":"Industry Standards from Accellera","authors":"S. Mehta","doi":"10.1109/VLSI.2008.123","DOIUrl":"https://doi.org/10.1109/VLSI.2008.123","url":null,"abstract":"Accellera's (www.accellera.orq) mission is to drive worldwide development and use of standards required by systems, semiconductors and design tools companies, which enhance a language based design automation process. Overview of different standards from Accellera and how they fit into the design flow process will be presented. Status of various technical sub-committees like Open Compression Interface (OCI), Unified Power Format (UPF), Unified Coverage Interoperatbility (UCIS) and Open Verification Library(OVL) will also be covered.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130536726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Ghosh, S. Mukhopadhyay, A. Patra, B. Culpepper, Tawen Mei
This paper presents an accurate and fast technique for the estimation of on-resistance (RDS(on)) of large lateral power MOSFET switch layouts in on-chip DC-DC converter and determination of the current distribution pattern in the switch layouts. In the proposed approach an extracted netlist is created which consists of the lumped parasitic resistances formed in the metal interconnects and the MOS devices present in the layout. The extracted resistance values are computed from the metal geometry using models that relate resistance values to the geometric patterns in the layout. This approach exploits the highly symmetric and repetitive pattern of power MOSFET layouts to generate the resistance netlist efficiently. Similarly the modeling of very high W/L MOS finger channels is also described in this paper. Results from the numerical experiments show that the extracted resistances are within 2.6% of results obtained from standard FEM solver tool ANSYS.
{"title":"A New Approach for Estimation of On-Resistance and Current Distribution in Power Array Layouts","authors":"J. Ghosh, S. Mukhopadhyay, A. Patra, B. Culpepper, Tawen Mei","doi":"10.1109/VLSI.2008.87","DOIUrl":"https://doi.org/10.1109/VLSI.2008.87","url":null,"abstract":"This paper presents an accurate and fast technique for the estimation of on-resistance (RDS(on)) of large lateral power MOSFET switch layouts in on-chip DC-DC converter and determination of the current distribution pattern in the switch layouts. In the proposed approach an extracted netlist is created which consists of the lumped parasitic resistances formed in the metal interconnects and the MOS devices present in the layout. The extracted resistance values are computed from the metal geometry using models that relate resistance values to the geometric patterns in the layout. This approach exploits the highly symmetric and repetitive pattern of power MOSFET layouts to generate the resistance netlist efficiently. Similarly the modeling of very high W/L MOS finger channels is also described in this paper. Results from the numerical experiments show that the extracted resistances are within 2.6% of results obtained from standard FEM solver tool ANSYS.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132863809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Bansal, Jae-Joon Kim, Keunwoo Kim, S. Mukhopadhyay, C. Chuang, K. Roy
Dual-VT CMOS is an effective way to reduce leakage power in high-performance VLSI circuits. In this paper, we explore the technology design space for dual-threshold voltage transistor design in deep sub-100 nm technology nodes. We propose a technique of achieving high-VT devices - longer gate sidewall offset spacers to increase the channel length without increasing the printed gate length. Effectiveness of all the dual-VT technology options - increasing channel doping, increasing gate length and proposed technique of increasing spacer thickness - are analyzed at transistor to basic logic gate level. Results indicate that the proposed technique yields lower dynamic power consumption and lower performance penalty compared with longer gate length and high body doping devices. Our proposed technique, however, incurs extra fabrication mask similar to high-VT by increasing body doping.
{"title":"Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies","authors":"A. Bansal, Jae-Joon Kim, Keunwoo Kim, S. Mukhopadhyay, C. Chuang, K. Roy","doi":"10.1109/VLSI.2008.50","DOIUrl":"https://doi.org/10.1109/VLSI.2008.50","url":null,"abstract":"Dual-VT CMOS is an effective way to reduce leakage power in high-performance VLSI circuits. In this paper, we explore the technology design space for dual-threshold voltage transistor design in deep sub-100 nm technology nodes. We propose a technique of achieving high-VT devices - longer gate sidewall offset spacers to increase the channel length without increasing the printed gate length. Effectiveness of all the dual-VT technology options - increasing channel doping, increasing gate length and proposed technique of increasing spacer thickness - are analyzed at transistor to basic logic gate level. Results indicate that the proposed technique yields lower dynamic power consumption and lower performance penalty compared with longer gate length and high body doping devices. Our proposed technique, however, incurs extra fabrication mask similar to high-VT by increasing body doping.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131976306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently, the trade-off between power consumption and fault tolerance in embedded processors has been highlighted. This paper proposes an approach to reduce dynamic power of conventional high-level fault-tolerant techniques used in the register file of processors, without affecting the effectiveness of the fault-tolerant techniques. The power reduction is based on the reduction of dynamic power of the unaccessed parts of the register file. This approach is applied to three transient fault-tolerant techniques: single error correction (SEC) Hamming code, duplication with parity, and triple modular redundancy (TMR). As a case study, this approach is implemented on the register file of an OpenRISC 1200 processor. The experimental calculation of the power consumption shows that the proposed approach saves about 67%, 62%, and 58% power for TMR, duplication with parity, and SEC Hamming code, respectively.
{"title":"A Power Efficient Approach to Fault-Tolerant Register File Design","authors":"Mojtaba Amiri-Kamalabad, S. Miremadi, M. Fazeli","doi":"10.1109/VLSI.2008.53","DOIUrl":"https://doi.org/10.1109/VLSI.2008.53","url":null,"abstract":"Recently, the trade-off between power consumption and fault tolerance in embedded processors has been highlighted. This paper proposes an approach to reduce dynamic power of conventional high-level fault-tolerant techniques used in the register file of processors, without affecting the effectiveness of the fault-tolerant techniques. The power reduction is based on the reduction of dynamic power of the unaccessed parts of the register file. This approach is applied to three transient fault-tolerant techniques: single error correction (SEC) Hamming code, duplication with parity, and triple modular redundancy (TMR). As a case study, this approach is implemented on the register file of an OpenRISC 1200 processor. The experimental calculation of the power consumption shows that the proposed approach saves about 67%, 62%, and 58% power for TMR, duplication with parity, and SEC Hamming code, respectively.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131006686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In state-of-the-art digital signal processing (DSP) and graphics applications, the arithmetic sum-of-product (SOP) is an important and computationally intensive operation, consuming a significant amount of area, delay and power. This paper presents a new algorithmic approach to synthesize a non-timing critical SOP block in an area-efficient and power-efficient way, which can be very useful to reduce the size and power consumption of the non timing-critical portion in the design. We have divided the problem of generating the SOP into three parts: inversion-based creation of the BitClusters (sets of individual partial-product bits, which belong to the ith bitslice), propagation-based reduction of the BitClusters and selective-inversion based computation of the final sum result. Techniques used in these three steps help to reduce the implementation area and power consumption for the SOP block. Our experimental data shows that the SOP block generated by our approach is significantly smaller (8.59% on average) and marginally faster (0.42% on average) than the SOP block generated by a commercially available best-in-class datapath synthesis tool. In addition, our proposed SOP netlist consumes significantly less dynamic power (7.92% on average) and leakage power (5.65% on average) than the netlist generated by the synthesis tool. These improvements were verified on placed-and-routed designs as well.
{"title":"An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products","authors":"Sabyasachi Das, S. Khatri","doi":"10.1109/VLSI.2008.18","DOIUrl":"https://doi.org/10.1109/VLSI.2008.18","url":null,"abstract":"In state-of-the-art digital signal processing (DSP) and graphics applications, the arithmetic sum-of-product (SOP) is an important and computationally intensive operation, consuming a significant amount of area, delay and power. This paper presents a new algorithmic approach to synthesize a non-timing critical SOP block in an area-efficient and power-efficient way, which can be very useful to reduce the size and power consumption of the non timing-critical portion in the design. We have divided the problem of generating the SOP into three parts: inversion-based creation of the BitClusters (sets of individual partial-product bits, which belong to the ith bitslice), propagation-based reduction of the BitClusters and selective-inversion based computation of the final sum result. Techniques used in these three steps help to reduce the implementation area and power consumption for the SOP block. Our experimental data shows that the SOP block generated by our approach is significantly smaller (8.59% on average) and marginally faster (0.42% on average) than the SOP block generated by a commercially available best-in-class datapath synthesis tool. In addition, our proposed SOP netlist consumes significantly less dynamic power (7.92% on average) and leakage power (5.65% on average) than the netlist generated by the synthesis tool. These improvements were verified on placed-and-routed designs as well.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122221972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently, dynamically reconfigurable processors (DRPs) have been proposed. In this paper, we describe a model of a DRP using a dynamic module library (DML), which we have developed for the modeling of general-purpose dynamically reconfigurable systems. The DML is an extended SystemC library and enables the modeling of the dynamic generation and elimination of modules, ports and channels and the dynamic connection and dispatch between port and channel. Using the DML, we can model the DRP naturally. The architecture of the proposed DRP is based on an MlPS-type architecture and supports the instructions, which are for the dynamically reconfigurable operational units and for their generation and elimination. We describe the proposed DRP model and its evaluation results.
{"title":"A Modeling of a Dynamically Reconfigurable Processor Using SystemC","authors":"J. Kitamichi, K. Ueda, Kenichi Kuroda","doi":"10.1109/VLSI.2008.13","DOIUrl":"https://doi.org/10.1109/VLSI.2008.13","url":null,"abstract":"Recently, dynamically reconfigurable processors (DRPs) have been proposed. In this paper, we describe a model of a DRP using a dynamic module library (DML), which we have developed for the modeling of general-purpose dynamically reconfigurable systems. The DML is an extended SystemC library and enables the modeling of the dynamic generation and elimination of modules, ports and channels and the dynamic connection and dispatch between port and channel. Using the DML, we can model the DRP naturally. The architecture of the proposed DRP is based on an MlPS-type architecture and supports the instructions, which are for the dynamically reconfigurable operational units and for their generation and elimination. We describe the proposed DRP model and its evaluation results.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131174698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：