Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811877
Zhiheng Lin, Xi Tan, Hao Min
A CMOS passive mixer-first receiver front-end for UHF RFID Reader is presented in this paper. Instead of LNA input structure, we choose single-balanced passive mixer as the input stage to improve compression point, and can handle the large jammer noise from the leakage of the transmitter. The transimpedance amplifiers are followed by the mixers to provide enough gain and suppress the noise behind. We also use complex impedance match at baseband to control the real and imaginary part of the antenna equivalent impedance. This can leave out the matching network off chip. The receiver front-end circuit is designed in SMIC 0.13μm CMOS process.
{"title":"A CMOS passive mixer-first receiver front-end for UHF RFID Reader","authors":"Zhiheng Lin, Xi Tan, Hao Min","doi":"10.1109/ASICON.2013.6811877","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811877","url":null,"abstract":"A CMOS passive mixer-first receiver front-end for UHF RFID Reader is presented in this paper. Instead of LNA input structure, we choose single-balanced passive mixer as the input stage to improve compression point, and can handle the large jammer noise from the leakage of the transmitter. The transimpedance amplifiers are followed by the mixers to provide enough gain and suppress the noise behind. We also use complex impedance match at baseband to control the real and imaginary part of the antenna equivalent impedance. This can leave out the matching network off chip. The receiver front-end circuit is designed in SMIC 0.13μm CMOS process.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126882867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Retinex is widely used in image enhancement field. Mathematical analysis is performed in this paper and the implementability in hardware is improved. Performance and power consumption are balanced by a configurable control unit for different application requirements. The configurable image enhancement unit is designed with SueprV DSP as prototype, experiments show that the chip area only increases by 8.5%, and the power consumption in SSR mode is 69% less than that of MSR.
{"title":"A design of configurable image enhancement unit","authors":"Zhiyuan Xue, Huan Ying, Yingke Gao, Tiejun Zhang, Donghui Wang, C. Hou","doi":"10.1109/ASICON.2013.6811999","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811999","url":null,"abstract":"Retinex is widely used in image enhancement field. Mathematical analysis is performed in this paper and the implementability in hardware is improved. Performance and power consumption are balanced by a configurable control unit for different application requirements. The configurable image enhancement unit is designed with SueprV DSP as prototype, experiments show that the chip area only increases by 8.5%, and the power consumption in SSR mode is 69% less than that of MSR.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123117528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812011
Longxiang Zhang, Hantian Xu, Yingbo Dai, Hao Min
This paper presents a high-sensitivity NFC system based on Labview platform using SDR (Software Defined Radio) approach. Protocol ISO14443-A is used in this work. This paper analyses the entire transceiver system and sensitivity of the system. Test results show that the receiver reaches the sensitivity of -80 dBm and maximum reading distance of 24 cm.
{"title":"An NFC system with high sensitivity based on SDR","authors":"Longxiang Zhang, Hantian Xu, Yingbo Dai, Hao Min","doi":"10.1109/ASICON.2013.6812011","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812011","url":null,"abstract":"This paper presents a high-sensitivity NFC system based on Labview platform using SDR (Software Defined Radio) approach. Protocol ISO14443-A is used in this work. This paper analyses the entire transceiver system and sensitivity of the system. Test results show that the receiver reaches the sensitivity of -80 dBm and maximum reading distance of 24 cm.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120896303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811917
Jhih-Rong Gao, Bei Yu, Duo Ding, D. Pan
With continued feature size scaling, even state of the art semiconductor manufacturing processes will often run into layouts with poor printability and yield. Identifying lithography hotspots is important at both physical verification and early physical design stages. While detailed lithography simulations can be very accurate, they may be too computationally expensive for full-chip scale and physical design inner loops. Meanwhile, pattern matching and machine learning based hotspot detection methods can provide acceptable quality and yet fast turn-around-time for full-chip scale physical verification and design. In this paper, we discuss some key issues and recent results on lithography hotspot detection and mitigation in nanometer VLSI.
{"title":"Lithography hotspot detection and mitigation in nanometer VLSI","authors":"Jhih-Rong Gao, Bei Yu, Duo Ding, D. Pan","doi":"10.1109/ASICON.2013.6811917","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811917","url":null,"abstract":"With continued feature size scaling, even state of the art semiconductor manufacturing processes will often run into layouts with poor printability and yield. Identifying lithography hotspots is important at both physical verification and early physical design stages. While detailed lithography simulations can be very accurate, they may be too computationally expensive for full-chip scale and physical design inner loops. Meanwhile, pattern matching and machine learning based hotspot detection methods can provide acceptable quality and yet fast turn-around-time for full-chip scale physical verification and design. In this paper, we discuss some key issues and recent results on lithography hotspot detection and mitigation in nanometer VLSI.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123856210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811854
Dexin Kong, T. Yu, Fengqi Yu
A temperature sensing front-end of temperature sensor based on CMOS substrate pnp transistors is presented. It uses ΔVBE which is proportional to absolute temperature (PTAT) to realize temperature measurement. Non-idealities of the resulting PTAT voltage are analyzed and circuit compensation techniques for these non-idealities are introduced. The circuit is implemented in Chartered 0.18μm CMOS technology, and by taking the reverse Early effect into account. Experimental results show that temperature accuracy which is extracted from experiment can reach ±0.5°C in the range of -40°C to 40°C.
{"title":"A temperature sensing front-end using CMOS substrate PNP transistors","authors":"Dexin Kong, T. Yu, Fengqi Yu","doi":"10.1109/ASICON.2013.6811854","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811854","url":null,"abstract":"A temperature sensing front-end of temperature sensor based on CMOS substrate pnp transistors is presented. It uses ΔVBE which is proportional to absolute temperature (PTAT) to realize temperature measurement. Non-idealities of the resulting PTAT voltage are analyzed and circuit compensation techniques for these non-idealities are introduced. The circuit is implemented in Chartered 0.18μm CMOS technology, and by taking the reverse Early effect into account. Experimental results show that temperature accuracy which is extracted from experiment can reach ±0.5°C in the range of -40°C to 40°C.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125296115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812016
Shengye Wang, Wei Cao, Lingli Wang, Na Wang, Ping Tao
Most of the implementations of boundary scan chains are of fixed length, typically hundreds or thousands. Because the whole chain is scanned every time, many clock cycles are wasted when only a small part of it is concerned. In this paper, a novel structure of configurable boundary scan chain is proposed. Its length and content can be reconfigured without interrupting the chip's functionality. Experimental result shows that the maximum frequency can be as high as 510.4MHz for a full-configurable chain with 512 cells, under 32 nm process, which is 15.7x better than the intuitive method. The proposed structure has been applied to a processor prototype design, and is expected to meet requirements of different applications.
{"title":"A novel structure of dynamic configurable scan chain bypassing unconcerned segments on the fly","authors":"Shengye Wang, Wei Cao, Lingli Wang, Na Wang, Ping Tao","doi":"10.1109/ASICON.2013.6812016","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812016","url":null,"abstract":"Most of the implementations of boundary scan chains are of fixed length, typically hundreds or thousands. Because the whole chain is scanned every time, many clock cycles are wasted when only a small part of it is concerned. In this paper, a novel structure of configurable boundary scan chain is proposed. Its length and content can be reconfigured without interrupting the chip's functionality. Experimental result shows that the maximum frequency can be as high as 510.4MHz for a full-configurable chain with 512 cells, under 32 nm process, which is 15.7x better than the intuitive method. The proposed structure has been applied to a processor prototype design, and is expected to meet requirements of different applications.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125319921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A kind of novel method is discussed to design the high speed prescaler in GHz frequency-hopping PLL frequency synthesizer. The structure of the dual-modulus prescaler (DMP) is optimized and a novel high speed D-latch integrated with multiple-input OR gate is used. The improved structure can make all separated logic gates be integrated with correlative D flip-flops completely. The circuit can work stably and accurately under all kinds of simulation condition such as different process corners. It is fabricated in 0.18μm mixed-signal CMOS technology. The measured results show that the high speed prscaler 's operating frequency range is 2.25~ 2.75GHz in 1.8V power supply, the current consumption is 5.4mA (including buffer) and higher speed and lower power dissipation are obtained.
{"title":"Design of novel high speed dual-modulus prescaler based on new optimized structure","authors":"Zheng Sun, Yong Xu, Cheng Hu, G. Ma, Yuanliang Wu, Ying Huang","doi":"10.1109/ASICON.2013.6811890","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811890","url":null,"abstract":"A kind of novel method is discussed to design the high speed prescaler in GHz frequency-hopping PLL frequency synthesizer. The structure of the dual-modulus prescaler (DMP) is optimized and a novel high speed D-latch integrated with multiple-input OR gate is used. The improved structure can make all separated logic gates be integrated with correlative D flip-flops completely. The circuit can work stably and accurately under all kinds of simulation condition such as different process corners. It is fabricated in 0.18μm mixed-signal CMOS technology. The measured results show that the high speed prscaler 's operating frequency range is 2.25~ 2.75GHz in 1.8V power supply, the current consumption is 5.4mA (including buffer) and higher speed and lower power dissipation are obtained.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127687457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812000
Jianping Wu, Ming Ling, Yang Zhang, Chen Mei, Huan Wang
A novel dynamic reconfigurable on-chip unified memory hierarchy, RcfgMem (Reconfigurable on-chip Unified memory) is introduced in this paper. The given resource of RcfgMem can be divided into certain size of Cache and SPM (Scratch-pad Memory) by configuration. Then, a dynamic reconfiguration algorithm is provided based on CBPG (Cache Behavior Phase Graph). The characteristics of program execution is studied, and a phase detect logic based on basic block vector is used to check the phases' Eigenvalues such as IPC etc. The experimental and exploration results showed that, compared with 4kB (kBytes) 4-way set-associative traditional I-Cache, the total energy consumption of 4kB RcfgMem can be reduced by 15.98% on average and up to 34.03% with a small performance promotion.
{"title":"A novel energy-oriented reconfigurable on-chip unified memory architecture based on Cache Behavior Phase Graph","authors":"Jianping Wu, Ming Ling, Yang Zhang, Chen Mei, Huan Wang","doi":"10.1109/ASICON.2013.6812000","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812000","url":null,"abstract":"A novel dynamic reconfigurable on-chip unified memory hierarchy, RcfgMem (Reconfigurable on-chip Unified memory) is introduced in this paper. The given resource of RcfgMem can be divided into certain size of Cache and SPM (Scratch-pad Memory) by configuration. Then, a dynamic reconfiguration algorithm is provided based on CBPG (Cache Behavior Phase Graph). The characteristics of program execution is studied, and a phase detect logic based on basic block vector is used to check the phases' Eigenvalues such as IPC etc. The experimental and exploration results showed that, compared with 4kB (kBytes) 4-way set-associative traditional I-Cache, the total energy consumption of 4kB RcfgMem can be reduced by 15.98% on average and up to 34.03% with a small performance promotion.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134313827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811864
Hanyu Wang, Jinxiang Wang, Yu Lu, F. Fu
In radar system, as the most important part of IF radar receiver, digital down converter (DDC) extracts the baseband signal needed from modulated IF signal, and down-samples the signal with decimation factor of 20. This paper proposes an efficient low-cost structure of DDC, including NCO, mixer and a modified filter bank. The modified filter bank adopts a high-efficiency structure, including a 5-stage CIC filter, a 9-tap CFIR filter and a 15-tap HB filter, which reduces the complexity and cost of implementation compared with the traditional filter bank. Then an optimized fixed-point programming is designed in order to implement DDC on fixed-point DSP or FPGA. The simulation results show that the proposed DDC achieves an expectant specification in application of IF radar receiver.
{"title":"An efficient low-cost fixed-point digital down converter with modified filter bank","authors":"Hanyu Wang, Jinxiang Wang, Yu Lu, F. Fu","doi":"10.1109/ASICON.2013.6811864","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811864","url":null,"abstract":"In radar system, as the most important part of IF radar receiver, digital down converter (DDC) extracts the baseband signal needed from modulated IF signal, and down-samples the signal with decimation factor of 20. This paper proposes an efficient low-cost structure of DDC, including NCO, mixer and a modified filter bank. The modified filter bank adopts a high-efficiency structure, including a 5-stage CIC filter, a 9-tap CFIR filter and a 15-tap HB filter, which reduces the complexity and cost of implementation compared with the traditional filter bank. Then an optimized fixed-point programming is designed in order to implement DDC on fixed-point DSP or FPGA. The simulation results show that the proposed DDC achieves an expectant specification in application of IF radar receiver.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134561280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811848
Tianlong Ma, Cong Liu, Yibo Fan, Xiaoyang Zeng
As an approximation to the Discrete Cosine Transform (DCT), Integer Cosine Transform (ICT) is widely used in latest video coding standards, such as H.264/AVC, VC-1 and AVS. High Efficiency Video Coding (HEVC), the next generation of video compression standard, adopts 4/8/16/32 integer transform. Since the size of matrices themselves and the numerical magnitude of matrix elements are very large, HEVC transform suffers from huge computational complexity. To alleviate this problem, we proposed a fast algorithm for order-8 integer transform for HEVC. This algorithm has 66% less multiplications and 46% less additions than direct method and saves 60% area for hardware implementation. It is illustrated by signal-flow graph, which is easy to be translated to hardware or software implementation.
整数余弦变换(ICT)作为离散余弦变换(DCT)的一种近似方法，被广泛应用于最新的视频编码标准中，如H.264/AVC、VC-1和AVS。HEVC (High Efficiency Video Coding)是新一代视频压缩标准，采用4/8/16/32整数变换。由于矩阵本身的大小和矩阵元素的数值量级非常大，HEVC变换具有巨大的计算复杂度。为了解决这一问题，我们提出了一种快速的HEVC -8阶整数变换算法。该算法比直接法减少66%的乘法运算和46%的加法运算，节省60%的硬件实现面积。用信号流图表示，易于转换为硬件或软件实现。
{"title":"A fast 8×8 IDCT algorithm for HEVC","authors":"Tianlong Ma, Cong Liu, Yibo Fan, Xiaoyang Zeng","doi":"10.1109/ASICON.2013.6811848","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811848","url":null,"abstract":"As an approximation to the Discrete Cosine Transform (DCT), Integer Cosine Transform (ICT) is widely used in latest video coding standards, such as H.264/AVC, VC-1 and AVS. High Efficiency Video Coding (HEVC), the next generation of video compression standard, adopts 4/8/16/32 integer transform. Since the size of matrices themselves and the numerical magnitude of matrix elements are very large, HEVC transform suffers from huge computational complexity. To alleviate this problem, we proposed a fast algorithm for order-8 integer transform for HEVC. This algorithm has 66% less multiplications and 46% less additions than direct method and saves 60% area for hardware implementation. It is illustrated by signal-flow graph, which is easy to be translated to hardware or software implementation.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134570243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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