Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812015
Weijia Ma, Xiaole Cui, Chung Len Lee
With scaling down of device and increasing memory density, reliability of SRAM faces severe challenge from soft errors, for radiation particles may upset multiple adjacent memory cells, and this limits the efficacy of conventionally used error correcting codes. This paper, based on the double error correcting (DEC) BCH codes, presents a solution to find codes which can correct, in addition to double random errors, a burst error of length up to three bits for 16, 32-bit memories or a burst error of length up to four for 16, 32 and 64-bit memories. The codes have been implemented in parallel architecture with a 90nm CMOS technology, and the result shows that they incurs almost the same latency and area overhead as compared to the conventional DEC BCH code which only correct double random errors.
{"title":"Enhanced error correction against multiple-bit-upset based on BCH code for SRAM","authors":"Weijia Ma, Xiaole Cui, Chung Len Lee","doi":"10.1109/ASICON.2013.6812015","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812015","url":null,"abstract":"With scaling down of device and increasing memory density, reliability of SRAM faces severe challenge from soft errors, for radiation particles may upset multiple adjacent memory cells, and this limits the efficacy of conventionally used error correcting codes. This paper, based on the double error correcting (DEC) BCH codes, presents a solution to find codes which can correct, in addition to double random errors, a burst error of length up to three bits for 16, 32-bit memories or a burst error of length up to four for 16, 32 and 64-bit memories. The codes have been implemented in parallel architecture with a 90nm CMOS technology, and the result shows that they incurs almost the same latency and area overhead as compared to the conventional DEC BCH code which only correct double random errors.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"379 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114014780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a flexible piezoelectric energy harvester using the piezoelectric copolymer P(VDF-TrFE) films as active elements to convert mechanical inputs to electrical energy. The repeatedly spin-coated P(VDF-TrFE) films were thermally poled and then characterized by SEM, ferroelectric hysteresis and FTIR. The piezoelectric performance of the fabricated harvester was measured under periodical mechanical inputs at ultra-low frequencies. The electrical output of average Vpp was as high as 0.96 V at 0.65 Hz.
{"title":"Ultra-low frequency P(VDF-TrFE) piezoelectric energy harvester on flexible substrate","authors":"Zhaoyang Pi, Lun Zhu, Jingwei Zhang, Dongping Wu, David-Wei Zhang, Zhi-Bin Zhang, Shi-Li Zhang","doi":"10.1109/ASICON.2013.6811943","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811943","url":null,"abstract":"This paper proposes a flexible piezoelectric energy harvester using the piezoelectric copolymer P(VDF-TrFE) films as active elements to convert mechanical inputs to electrical energy. The repeatedly spin-coated P(VDF-TrFE) films were thermally poled and then characterized by SEM, ferroelectric hysteresis and FTIR. The piezoelectric performance of the fabricated harvester was measured under periodical mechanical inputs at ultra-low frequencies. The electrical output of average Vpp was as high as 0.96 V at 0.65 Hz.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127665671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811933
M. Miyake, K. Matsuura, A. Ueno
SPICE modeling of the diode reverse recovery effect is discussed. This effect is very important for the developments of power electronic circuit applications such as motor-drive inverters and power conditioners. With the dynamic carrier-distribution-based modeling approach, the reverse recovery behaviors are explained, where the nonquasi-static (NQS) behavior of carriers in the drift region is considered. Its reverse recovery modeling ability is verified with a two-dimensional (2D) device simulator, in comparison to the conventional lumped-charge modeling technique.
{"title":"Compact modeling of the diode reverse recovery effect for leading developments of power electronic applications","authors":"M. Miyake, K. Matsuura, A. Ueno","doi":"10.1109/ASICON.2013.6811933","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811933","url":null,"abstract":"SPICE modeling of the diode reverse recovery effect is discussed. This effect is very important for the developments of power electronic circuit applications such as motor-drive inverters and power conditioners. With the dynamic carrier-distribution-based modeling approach, the reverse recovery behaviors are explained, where the nonquasi-static (NQS) behavior of carriers in the drift region is considered. Its reverse recovery modeling ability is verified with a two-dimensional (2D) device simulator, in comparison to the conventional lumped-charge modeling technique.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122251416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811894
Fanzeng. Meng, Rui Guan, Dongpo Chen
An integrated dual control mode automatic gain control (AGC) circuit is designed for the wireless communication system in a 0.18-μm CMOS process. Utilizing both digital and analog control methods allows systems to achieve a wide gain range and high accuracy at the same time. Its custom gain range and setting time is appropriate for various communication systems.
{"title":"Dual control mode AGC for wireless communication system","authors":"Fanzeng. Meng, Rui Guan, Dongpo Chen","doi":"10.1109/ASICON.2013.6811894","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811894","url":null,"abstract":"An integrated dual control mode automatic gain control (AGC) circuit is designed for the wireless communication system in a 0.18-μm CMOS process. Utilizing both digital and analog control methods allows systems to achieve a wide gain range and high accuracy at the same time. Its custom gain range and setting time is appropriate for various communication systems.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132193401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812059
Wei Tai, Lele Jiang, Wang Lei, S. Wen, Lifu Chang, Yuhua Cheng
In this paper, we study the impact of stress effect on n-MOSFET characteristics, from neighborhood device active area (NDAA) and surrounding shallow trench isolation (SSTI), in addition to the stress from its own active area (AA) and shallow trench isolation (STI). With a group of test structures at a 40nm technology, measurement data are performed and analyzed to understand the impacts of the neighbor device active area width(NDAAW), located in the direction along the channel length, on the device parameters, such as saturation drain current (Idsat), threshold voltage (Vth), and leakage current (Ioff). It was found that the Idsat increases by ~13.6%, Vth decreases by ~15.7%,and Ioff increases by even five times, compared with the standard devices without these surrounding devices, due to the additional impacts from the NDAA and SSTI. It is suggested that some parameters such as STIW, NDAAW and SSTIW should be added to the existing SPICE models as new parameters to consider the surrounding devices effects for accurate modeling of n-MOSFET in 40nm process technology. Moreover, the impacts of stress effects from neighborhood devices to the n-MOSFET characteristics should be considered in designs of standard cells in 40nm and below processes.
{"title":"Characteristics of n-MOSFETs with stress effects from neighborhood devices","authors":"Wei Tai, Lele Jiang, Wang Lei, S. Wen, Lifu Chang, Yuhua Cheng","doi":"10.1109/ASICON.2013.6812059","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812059","url":null,"abstract":"In this paper, we study the impact of stress effect on n-MOSFET characteristics, from neighborhood device active area (NDAA) and surrounding shallow trench isolation (SSTI), in addition to the stress from its own active area (AA) and shallow trench isolation (STI). With a group of test structures at a 40nm technology, measurement data are performed and analyzed to understand the impacts of the neighbor device active area width(NDAAW), located in the direction along the channel length, on the device parameters, such as saturation drain current (Idsat), threshold voltage (Vth), and leakage current (Ioff). It was found that the Idsat increases by ~13.6%, Vth decreases by ~15.7%,and Ioff increases by even five times, compared with the standard devices without these surrounding devices, due to the additional impacts from the NDAA and SSTI. It is suggested that some parameters such as STIW, NDAAW and SSTIW should be added to the existing SPICE models as new parameters to consider the surrounding devices effects for accurate modeling of n-MOSFET in 40nm process technology. Moreover, the impacts of stress effects from neighborhood devices to the n-MOSFET characteristics should be considered in designs of standard cells in 40nm and below processes.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131589158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a 14-bit 100-kHz bandwidth incremental sigma-delta analog-to-digital converter suitable for CMOS image sensors with column-parallel ADCs. By using an inverter instead of an operational trans-conductance amplifier (OTA), the total assumption of modulator is dramatically reduced. To further decrease the power consumption, a body bias inverter is proposed in the inverter, enhancing the current efficiency gm/IDS. Since the decimating filter can be realized with a much simpler structure, a full custom circuit design is applied to the schematic design with a self-timing control cell. The proposed single-ended incremental ADC is designed in 0.18μm CMOS technology. The simulation result shows that for a 1.8V supply, 30MHz sampling frequency and 150 oversampling ratio, the power consumption is 122.2μW, dynamic range is 85dB and the ENOB is 13.26bit.
{"title":"A 1.8-V 14-bit inverter-based incremental ΣΔ ADC for CMOS image sensor","authors":"Biao Wang, Meng Zhang, Xu Cheng, Qi Feng, Xiaoyang Zeng","doi":"10.1109/ASICON.2013.6812046","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812046","url":null,"abstract":"This paper presents a 14-bit 100-kHz bandwidth incremental sigma-delta analog-to-digital converter suitable for CMOS image sensors with column-parallel ADCs. By using an inverter instead of an operational trans-conductance amplifier (OTA), the total assumption of modulator is dramatically reduced. To further decrease the power consumption, a body bias inverter is proposed in the inverter, enhancing the current efficiency gm/IDS. Since the decimating filter can be realized with a much simpler structure, a full custom circuit design is applied to the schematic design with a self-timing control cell. The proposed single-ended incremental ADC is designed in 0.18μm CMOS technology. The simulation result shows that for a 1.8V supply, 30MHz sampling frequency and 150 oversampling ratio, the power consumption is 122.2μW, dynamic range is 85dB and the ENOB is 13.26bit.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131704171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812068
Jieliang Lu, Qin Wang, Jing Xie, Zhigang Mao
3D integrated technique gives a promising method of overcoming the increasing problems of interconnect wire length and power consumption. In the design of the 3D-IC, the floorplanning algorithm decides the performance of the circuit. In this paper, we present a floorplanning algorithm considering both the critical wire length and the number of TSVs. Finally MCNC floorplan circuits are used as benchmarks. The result shows that the algorithm can reduce the critical wire length by average 40.1% and reduce the TSVs' number by 24.8% under the same critical length. The algorithm can be widely used in the design of 3D integrated circuits.
{"title":"TSVs-aware floorplanning for 3D integrated circuit","authors":"Jieliang Lu, Qin Wang, Jing Xie, Zhigang Mao","doi":"10.1109/ASICON.2013.6812068","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812068","url":null,"abstract":"3D integrated technique gives a promising method of overcoming the increasing problems of interconnect wire length and power consumption. In the design of the 3D-IC, the floorplanning algorithm decides the performance of the circuit. In this paper, we present a floorplanning algorithm considering both the critical wire length and the number of TSVs. Finally MCNC floorplan circuits are used as benchmarks. The result shows that the algorithm can reduce the critical wire length by average 40.1% and reduce the TSVs' number by 24.8% under the same critical length. The algorithm can be widely used in the design of 3D integrated circuits.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130803206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811953
Hong-Wun Gao, T. Chiang
A novel scaling theory for fully-depleted omega-gate (ΩG) MOSFETs including rectangular-shaped ΩG (RΩG) and cylindrical-shaped ΩG (CΩG) FETs is presented. The natural length for ΩG MOSFET is obtained by the equation of equivalent number of gates (ENG), where the ΩG device can be virtually broken into equivalent double-gate (DG) and single-gate (SG) transistors working in parallel based on perimeter-weighted-sum method. Numerical device simulation data for DIBL were compared to the model to validate the formula. Among RΩG devices, one with a square cross section and/or large oxide underlap coverage factor (OUCF) will show the worst immunity to DIBL due to the largest natural length. For equivalent short-channel control, the RΩG MOSFET with OUCF=0.3 illustrates an improvement of up to 25% in the minimum channel length when compared to the DG MOSFET.
{"title":"A novel scaling theory for fully-depleted omega-gate (ΩG) MOSFETs","authors":"Hong-Wun Gao, T. Chiang","doi":"10.1109/ASICON.2013.6811953","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811953","url":null,"abstract":"A novel scaling theory for fully-depleted omega-gate (ΩG) MOSFETs including rectangular-shaped ΩG (RΩG) and cylindrical-shaped ΩG (CΩG) FETs is presented. The natural length for ΩG MOSFET is obtained by the equation of equivalent number of gates (ENG), where the ΩG device can be virtually broken into equivalent double-gate (DG) and single-gate (SG) transistors working in parallel based on perimeter-weighted-sum method. Numerical device simulation data for DIBL were compared to the model to validate the formula. Among RΩG devices, one with a square cross section and/or large oxide underlap coverage factor (OUCF) will show the worst immunity to DIBL due to the largest natural length. For equivalent short-channel control, the RΩG MOSFET with OUCF=0.3 illustrates an improvement of up to 25% in the minimum channel length when compared to the DG MOSFET.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133017243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811883
Meng-Ting Hsu, Jie-An Huang, Yao-Yan Lee
In this paper, a low power and low phase noise of CMOS voltage controlled oscillator (VCO) is presented. The proposed VCO is adopted transformer feedback with drain-gate connection and body-biasing of the transistor. The bandwidth of the frequency range is from 4.97 GHz to 5.76 GHz with a 18.3%. The phase noise of the proposed VCO is -116.4dBc/Hz at 1MHz offset frequency. In a standard 0.18 μm COMS process with a 0.5-V power supply. The core power consumption of the VCO is 2.2 mW.
{"title":"Design of drain-gate transformer feedback VCO with body-biasing","authors":"Meng-Ting Hsu, Jie-An Huang, Yao-Yan Lee","doi":"10.1109/ASICON.2013.6811883","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811883","url":null,"abstract":"In this paper, a low power and low phase noise of CMOS voltage controlled oscillator (VCO) is presented. The proposed VCO is adopted transformer feedback with drain-gate connection and body-biasing of the transistor. The bandwidth of the frequency range is from 4.97 GHz to 5.76 GHz with a 18.3%. The phase noise of the proposed VCO is -116.4dBc/Hz at 1MHz offset frequency. In a standard 0.18 μm COMS process with a 0.5-V power supply. The core power consumption of the VCO is 2.2 mW.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132718371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811901
L. Du, N. Ning, Kejun Wu, Yang Liu, Qi Yu
A process variation insensitive bandgap reference with self-calibration is presented. The initial accuracy of the bandgap reference is improved with self-calibration. The offset voltage caused by components mismatch due to process variation is averaged with a 6-bit resistor trimming array and the code for trimming is generated by the circuit itself. The 3σ inaccuracy of the bandgap reference decreases from ±12.6% to ±1.0% with the self-calibration. The circuit consumes 43.5μW and occupies 0.025mm2 in a standard 65nm 1P6M CMOS technology.
{"title":"A process variation insensitive bandgap reference with self-calibration technique","authors":"L. Du, N. Ning, Kejun Wu, Yang Liu, Qi Yu","doi":"10.1109/ASICON.2013.6811901","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811901","url":null,"abstract":"A process variation insensitive bandgap reference with self-calibration is presented. The initial accuracy of the bandgap reference is improved with self-calibration. The offset voltage caused by components mismatch due to process variation is averaged with a 6-bit resistor trimming array and the code for trimming is generated by the circuit itself. The 3σ inaccuracy of the bandgap reference decreases from ±12.6% to ±1.0% with the self-calibration. The circuit consumes 43.5μW and occupies 0.025mm2 in a standard 65nm 1P6M CMOS technology.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133136584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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