Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811906
Peng Chen, Rui Guan, Dongpo Chen
An improved VCO for compass navigation system (CNS) application is presented. It has a linearized KVCO and is robust to varactor bias variations. A voltage limit circuit is proposed to ensure that the varactors work in the depletion region. To compensate for active loop filter's lack of driving ability, a rail to rail opamp is used. Post-simulation results show that a better KVCO performance is achieved compared to the conventional one with tuning voltage changing from 0.15V to 1.65V. Implemented in a 0.18um CMOS process, the proposed VCO operates at 3.2 GHz with power supply of 1.8V.
{"title":"AVCO with F-V linearization techniques for CNS application","authors":"Peng Chen, Rui Guan, Dongpo Chen","doi":"10.1109/ASICON.2013.6811906","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811906","url":null,"abstract":"An improved VCO for compass navigation system (CNS) application is presented. It has a linearized KVCO and is robust to varactor bias variations. A voltage limit circuit is proposed to ensure that the varactors work in the depletion region. To compensate for active loop filter's lack of driving ability, a rail to rail opamp is used. Post-simulation results show that a better KVCO performance is achieved compared to the conventional one with tuning voltage changing from 0.15V to 1.65V. Implemented in a 0.18um CMOS process, the proposed VCO operates at 3.2 GHz with power supply of 1.8V.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129320784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811876
Jinhai Zhang, Bo Wang, Yi Peng, T. Hu, Xin'an Wang
This paper reports on the design of a low-power high-accuracy oscillator intended to serve as a clock reference for passive RFID tag. For this purpose, we have proposed an RC oscillator scheme adopting the efficient and robust resistor calibration. This novel calibration technique allows to achieving a frequency variation of only ±2.5% in the worst case, according to our 405 corners (PVT variation) simulation. It also shows that the power consumption is only 800nW, and its overall figure-of-merit exceeds most of the state-of-art circuits.
{"title":"A 800nW high-accuracy RC oscillator with resistor calibration for RFID","authors":"Jinhai Zhang, Bo Wang, Yi Peng, T. Hu, Xin'an Wang","doi":"10.1109/ASICON.2013.6811876","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811876","url":null,"abstract":"This paper reports on the design of a low-power high-accuracy oscillator intended to serve as a clock reference for passive RFID tag. For this purpose, we have proposed an RC oscillator scheme adopting the efficient and robust resistor calibration. This novel calibration technique allows to achieving a frequency variation of only ±2.5% in the worst case, according to our 405 corners (PVT variation) simulation. It also shows that the power consumption is only 800nW, and its overall figure-of-merit exceeds most of the state-of-art circuits.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129779984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811964
Ting Li, D. Fu, Yong Zhang, Yan Wang, Lu-yu Liu, Xu Wang
In this paper, a high-speed front-end circuit used in a pipeline analog-to-digital (ADC) is described. Time constant matching of the sampling networks, feedback factor of the amplifier, implementation of double duty cycle DCS (duty cycle stabilizer), and using of the reference are discussed. The high-speed front-end circuit design technique is applied to a 16-bit 250MSPS pipeline ADC. Simulation confirms that the ADC shows more than 95dB of SFDR for a 25.39-MHz sinusoidal input at 2Vpp at full sampling rate from a 1.8V/3.3V supply of a 0.18um BiCMOS process.
{"title":"A high-speed front-end circuit used in a 16bit 250MSPS pipelined ADC","authors":"Ting Li, D. Fu, Yong Zhang, Yan Wang, Lu-yu Liu, Xu Wang","doi":"10.1109/ASICON.2013.6811964","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811964","url":null,"abstract":"In this paper, a high-speed front-end circuit used in a pipeline analog-to-digital (ADC) is described. Time constant matching of the sampling networks, feedback factor of the amplifier, implementation of double duty cycle DCS (duty cycle stabilizer), and using of the reference are discussed. The high-speed front-end circuit design technique is applied to a 16-bit 250MSPS pipeline ADC. Simulation confirms that the ADC shows more than 95dB of SFDR for a 25.39-MHz sinusoidal input at 2Vpp at full sampling rate from a 1.8V/3.3V supply of a 0.18um BiCMOS process.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124977897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811858
Yu-Chung Hsiao, L. Daniel
In this paper, we propose a black-box nonlinear dynamic modeling algorithm that automatically selects essential basis functions to overcome the overfitting problem. Our automatic modeling algorithm, which is formulated as a convex optimization problem, guarantees model stability in transient simulation. Furthermore, we incorporate our algorithm with a sparsity induction mechanism, which improves model robustness and generalization capabilities, as shown in our example.
{"title":"Sparse basis pursuit on automatic nonlinear circuit modeling","authors":"Yu-Chung Hsiao, L. Daniel","doi":"10.1109/ASICON.2013.6811858","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811858","url":null,"abstract":"In this paper, we propose a black-box nonlinear dynamic modeling algorithm that automatically selects essential basis functions to overcome the overfitting problem. Our automatic modeling algorithm, which is formulated as a convex optimization problem, guarantees model stability in transient simulation. Furthermore, we incorporate our algorithm with a sparsity induction mechanism, which improves model robustness and generalization capabilities, as shown in our example.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124991918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811881
Zhiqing Chen, Qi Zhang, Ning Wang, D. Yuan, Guohong Li, Hui Wang, Songlin Feng
A CMOS phase-locked loop (PLL) with low reference spur and wide tuning range implemented in 0.18μm CMOS technology is presented in this paper. The design is based on the programmable integer-N PLL structure and the center frequency is around 480MHz for CMOS Image Sensor applications. A pseudo-differential current-starved multi-band ring oscillator is proposed to widen the tuning range. Several circuit techniques are used to minimize the phase frequency detector (PFD) UP/DN timing mismatch and charge pump (CP) current glitches, which reduce the reference spur. Implemented in the 0.18μm CMOS technology, the simulation results show that the -52.6dBc reference spur and the 94.4% tuning range (covering from 30MHz to 1050MHz) can be achieved.
{"title":"A low spur CMOS phase-locked loop with wide tuning range for CMOS Image Sensor","authors":"Zhiqing Chen, Qi Zhang, Ning Wang, D. Yuan, Guohong Li, Hui Wang, Songlin Feng","doi":"10.1109/ASICON.2013.6811881","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811881","url":null,"abstract":"A CMOS phase-locked loop (PLL) with low reference spur and wide tuning range implemented in 0.18μm CMOS technology is presented in this paper. The design is based on the programmable integer-N PLL structure and the center frequency is around 480MHz for CMOS Image Sensor applications. A pseudo-differential current-starved multi-band ring oscillator is proposed to widen the tuning range. Several circuit techniques are used to minimize the phase frequency detector (PFD) UP/DN timing mismatch and charge pump (CP) current glitches, which reduce the reference spur. Implemented in the 0.18μm CMOS technology, the simulation results show that the -52.6dBc reference spur and the 94.4% tuning range (covering from 30MHz to 1050MHz) can be achieved.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116026965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, an integrated development environment (IDE), which is used to map application into a target reconfigurable operators (ReOps) array, is presented. Having as input APU RTL description of an application, the IDE produces the configuration bitstream. The proposed IDE supports a variety of ReOps array through revising the architecture file which including the definition of ReOps, interconnection segments and connection switches, as well as the scale of array and organization of ReOps. A set of benchmarks is given to verify the flow of proposed IDE.
{"title":"An integrated development environment for reconfigurable operators array","authors":"Shan-shan Yong, Xin'an Wang, Ying Cao, Yawei Lu, Zheng Xie","doi":"10.1109/ASICON.2013.6812061","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812061","url":null,"abstract":"In this paper, an integrated development environment (IDE), which is used to map application into a target reconfigurable operators (ReOps) array, is presented. Having as input APU RTL description of an application, the IDE produces the configuration bitstream. The proposed IDE supports a variety of ReOps array through revising the architecture file which including the definition of ReOps, interconnection segments and connection switches, as well as the scale of array and organization of ReOps. A set of benchmarks is given to verify the flow of proposed IDE.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128547908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812022
Long He, Zhihui Chen, A. Jiang
Local hysteretic diode currents depending on domain orientations have been observed in epitaxial BiFeO3 thin films. The mechanism behind the bilateral and unilateral current hysteresis as well as retention of the nanodomains has been discussed in the films with different thicknesses. Piezoelectric force microscopy investigations reveal principle of resistive property is the switchable polarization control of hysteretic diode currents other than the creation and rupture of the conductive paths in other resistive random access memories mediated by mobile charged defects. With the investigation of different leakage current models, it has been found that the space-charge limited current (SCLC) dominates the conduction.
{"title":"Piezoelectric force microscopy study of local bipolar diode current dependence of preferential domain orientation in BiFeO3 thin films with different thicknesses","authors":"Long He, Zhihui Chen, A. Jiang","doi":"10.1109/ASICON.2013.6812022","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812022","url":null,"abstract":"Local hysteretic diode currents depending on domain orientations have been observed in epitaxial BiFeO3 thin films. The mechanism behind the bilateral and unilateral current hysteresis as well as retention of the nanodomains has been discussed in the films with different thicknesses. Piezoelectric force microscopy investigations reveal principle of resistive property is the switchable polarization control of hysteretic diode currents other than the creation and rupture of the conductive paths in other resistive random access memories mediated by mobile charged defects. With the investigation of different leakage current models, it has been found that the space-charge limited current (SCLC) dominates the conduction.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133503756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812003
Zheng Tang, Jing Xie, Zhigang Mao
The processors' architecture design plays an important role in high performance DSP era, where how to balance the power consumption and the computing ability is always a great concern. In this paper we propose an architecture scheme with VLIW instruction driven adaptive pipeline coupling technique for a multi-core processor design to achieve the high computing performance with a low powered capability. Combined with the loop buffering design and implementation, the scheme is evaluated with the typical DSP application and the results show that the performance is improved about 43.4% while the power consumption is reduced by 48.7% in average.
{"title":"A novel architecture scheme with adaptive pipeline coupling technique for DSP processor design","authors":"Zheng Tang, Jing Xie, Zhigang Mao","doi":"10.1109/ASICON.2013.6812003","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812003","url":null,"abstract":"The processors' architecture design plays an important role in high performance DSP era, where how to balance the power consumption and the computing ability is always a great concern. In this paper we propose an architecture scheme with VLIW instruction driven adaptive pipeline coupling technique for a multi-core processor design to achieve the high computing performance with a low powered capability. Combined with the loop buffering design and implementation, the scheme is evaluated with the typical DSP application and the results show that the performance is improved about 43.4% while the power consumption is reduced by 48.7% in average.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133951736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811839
F. Fu, Liang Wang, Yu Lu, Jinxiang Wang
Task migration, an effective resource management approach, contributes to an increase of on-chip communication overhead. We propose an MMPI-based task migration mechanism to lower task migration overhead in NoC-based MPSoC. This task migration mechanism depends on MPSoC message passing interface (MMPI), which defines a parallel programming pattern that program is dependent of task mapping. In the migration mechanism, task state information is transferred to another PE. The migration overhead is lowered since the task migration is based on MMPI and task code is not transferred. Furthermore, the task migration mechanism does not require checkpoints to detect migration request. Experimental results show that the migration delay decreases around 28% without transferring task code.
{"title":"Low overhead task migration mechanism in NoC-based MPSoC","authors":"F. Fu, Liang Wang, Yu Lu, Jinxiang Wang","doi":"10.1109/ASICON.2013.6811839","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811839","url":null,"abstract":"Task migration, an effective resource management approach, contributes to an increase of on-chip communication overhead. We propose an MMPI-based task migration mechanism to lower task migration overhead in NoC-based MPSoC. This task migration mechanism depends on MPSoC message passing interface (MMPI), which defines a parallel programming pattern that program is dependent of task mapping. In the migration mechanism, task state information is transferred to another PE. The migration overhead is lowered since the task migration is based on MMPI and task code is not transferred. Furthermore, the task migration mechanism does not require checkpoints to detect migration request. Experimental results show that the migration delay decreases around 28% without transferring task code.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122406875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811865
R. He, Jianfei Xu, N. Yan, M. Hao
This paper presents a 20Gb/s Limiting Amplifier (LA) with the active interleaving feedback technique both to broaden the bandwidth and achieve flatness response. The LA includes an input match and DC offset cancellation (DCOC), a four-stage 3rd order amplifier core and an output buffer for test. Simulated in the 65nm CMOS technology, the LA exhibits a voltage gain of 38.5dB, a 3-dB bandwidth of 18GHz and an integrated input noise of 0.56mV with the area of only 0.45 × 0.25 mm2. The chip excluding buffer is supplied by 1.2V VDD and consumes DC power of 61mW.
{"title":"A 20 Gb/s Limiting Amplifier in 65nm CMOS technology","authors":"R. He, Jianfei Xu, N. Yan, M. Hao","doi":"10.1109/ASICON.2013.6811865","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811865","url":null,"abstract":"This paper presents a 20Gb/s Limiting Amplifier (LA) with the active interleaving feedback technique both to broaden the bandwidth and achieve flatness response. The LA includes an input match and DC offset cancellation (DCOC), a four-stage 3rd order amplifier core and an output buffer for test. Simulated in the 65nm CMOS technology, the LA exhibits a voltage gain of 38.5dB, a 3-dB bandwidth of 18GHz and an integrated input noise of 0.56mV with the area of only 0.45 × 0.25 mm2. The chip excluding buffer is supplied by 1.2V VDD and consumes DC power of 61mW.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129024689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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