Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811876
Jinhai Zhang, Bo Wang, Yi Peng, T. Hu, Xin'an Wang
This paper reports on the design of a low-power high-accuracy oscillator intended to serve as a clock reference for passive RFID tag. For this purpose, we have proposed an RC oscillator scheme adopting the efficient and robust resistor calibration. This novel calibration technique allows to achieving a frequency variation of only ±2.5% in the worst case, according to our 405 corners (PVT variation) simulation. It also shows that the power consumption is only 800nW, and its overall figure-of-merit exceeds most of the state-of-art circuits.
{"title":"A 800nW high-accuracy RC oscillator with resistor calibration for RFID","authors":"Jinhai Zhang, Bo Wang, Yi Peng, T. Hu, Xin'an Wang","doi":"10.1109/ASICON.2013.6811876","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811876","url":null,"abstract":"This paper reports on the design of a low-power high-accuracy oscillator intended to serve as a clock reference for passive RFID tag. For this purpose, we have proposed an RC oscillator scheme adopting the efficient and robust resistor calibration. This novel calibration technique allows to achieving a frequency variation of only ±2.5% in the worst case, according to our 405 corners (PVT variation) simulation. It also shows that the power consumption is only 800nW, and its overall figure-of-merit exceeds most of the state-of-art circuits.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129779984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811964
Ting Li, D. Fu, Yong Zhang, Yan Wang, Lu-yu Liu, Xu Wang
In this paper, a high-speed front-end circuit used in a pipeline analog-to-digital (ADC) is described. Time constant matching of the sampling networks, feedback factor of the amplifier, implementation of double duty cycle DCS (duty cycle stabilizer), and using of the reference are discussed. The high-speed front-end circuit design technique is applied to a 16-bit 250MSPS pipeline ADC. Simulation confirms that the ADC shows more than 95dB of SFDR for a 25.39-MHz sinusoidal input at 2Vpp at full sampling rate from a 1.8V/3.3V supply of a 0.18um BiCMOS process.
{"title":"A high-speed front-end circuit used in a 16bit 250MSPS pipelined ADC","authors":"Ting Li, D. Fu, Yong Zhang, Yan Wang, Lu-yu Liu, Xu Wang","doi":"10.1109/ASICON.2013.6811964","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811964","url":null,"abstract":"In this paper, a high-speed front-end circuit used in a pipeline analog-to-digital (ADC) is described. Time constant matching of the sampling networks, feedback factor of the amplifier, implementation of double duty cycle DCS (duty cycle stabilizer), and using of the reference are discussed. The high-speed front-end circuit design technique is applied to a 16-bit 250MSPS pipeline ADC. Simulation confirms that the ADC shows more than 95dB of SFDR for a 25.39-MHz sinusoidal input at 2Vpp at full sampling rate from a 1.8V/3.3V supply of a 0.18um BiCMOS process.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124977897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811858
Yu-Chung Hsiao, L. Daniel
In this paper, we propose a black-box nonlinear dynamic modeling algorithm that automatically selects essential basis functions to overcome the overfitting problem. Our automatic modeling algorithm, which is formulated as a convex optimization problem, guarantees model stability in transient simulation. Furthermore, we incorporate our algorithm with a sparsity induction mechanism, which improves model robustness and generalization capabilities, as shown in our example.
{"title":"Sparse basis pursuit on automatic nonlinear circuit modeling","authors":"Yu-Chung Hsiao, L. Daniel","doi":"10.1109/ASICON.2013.6811858","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811858","url":null,"abstract":"In this paper, we propose a black-box nonlinear dynamic modeling algorithm that automatically selects essential basis functions to overcome the overfitting problem. Our automatic modeling algorithm, which is formulated as a convex optimization problem, guarantees model stability in transient simulation. Furthermore, we incorporate our algorithm with a sparsity induction mechanism, which improves model robustness and generalization capabilities, as shown in our example.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124991918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811955
R. Wong, R. Fung, Shi-Jie Wen
Data rates in networking applications have increased as demand for more data increases. To achieve the high performance, the data rates in high speed IOs have continued to increase. These high data rates require the IO capacitances have to be very low. ESD protection structures have traditionally been large to handle the large transient currents. Recently, the high speed IO has limited the capacitance associated with ESD structures, making ESD protection design for high speed IOs extremely challenging. This paper will discuss the networking industry's trends in high speed IOs, the capacitance requirements and resulting challenges for ESD protection designs. To achieve the proper ESD protection, on chip ESD protection schemes will need to change and/or ESD protection specifications may need to lower targeted protection levels. This is a hotly argued topic in the high speed networking industry, which may change the next-generation ESD protection design dramatically. We will discuss the possible ESD design outcomes due to the high speed IOs scaling trends.
{"title":"Networking industry trends in ESD protection for high speed IOs","authors":"R. Wong, R. Fung, Shi-Jie Wen","doi":"10.1109/ASICON.2013.6811955","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811955","url":null,"abstract":"Data rates in networking applications have increased as demand for more data increases. To achieve the high performance, the data rates in high speed IOs have continued to increase. These high data rates require the IO capacitances have to be very low. ESD protection structures have traditionally been large to handle the large transient currents. Recently, the high speed IO has limited the capacitance associated with ESD structures, making ESD protection design for high speed IOs extremely challenging. This paper will discuss the networking industry's trends in high speed IOs, the capacitance requirements and resulting challenges for ESD protection designs. To achieve the proper ESD protection, on chip ESD protection schemes will need to change and/or ESD protection specifications may need to lower targeted protection levels. This is a hotly argued topic in the high speed networking industry, which may change the next-generation ESD protection design dramatically. We will discuss the possible ESD design outcomes due to the high speed IOs scaling trends.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114171777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811978
Gaowei Xu, Yao Zou, Jun Han, Xiaoyang Zeng
This paper compares three low power schemes for the multi-hierarchy pipeline design of fixed point finite impulse response (FIR) digital filters, and we adopt an optimal CSD encoding method, minimizing the number of adders/subtractions in the design. In addition, a 16-bit, 16 taps low-pass FIR filter is designed to investigate the performance of the three different algorithms. To evaluate the performance of them, the designs are synthesized in SMIC 65nm library. The evaluation shows that the optimal CSD scheme is better than the other two low-power methods at the same throughput.
{"title":"Low power design for FIR filter","authors":"Gaowei Xu, Yao Zou, Jun Han, Xiaoyang Zeng","doi":"10.1109/ASICON.2013.6811978","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811978","url":null,"abstract":"This paper compares three low power schemes for the multi-hierarchy pipeline design of fixed point finite impulse response (FIR) digital filters, and we adopt an optimal CSD encoding method, minimizing the number of adders/subtractions in the design. In addition, a 16-bit, 16 taps low-pass FIR filter is designed to investigate the performance of the three different algorithms. To evaluate the performance of them, the designs are synthesized in SMIC 65nm library. The evaluation shows that the optimal CSD scheme is better than the other two low-power methods at the same throughput.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"355 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125773315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811976
Y. Zhou, A. Righter, J. Hajjar
The impact of gate series resistor on CDM protection effectiveness is systematically evaluated using SPICE simulation and verified with a modified VF-TLP test method. It is shown that the effectiveness of the resistor to a MOS input device is highly dependent on the size of the protected MOS device as well as on the types of ESD protection circuits. Larger MOS devices require smaller resistance values than smaller devices.
{"title":"Investigation on effectiveness of series gate resistor in CDM ESD protection designs","authors":"Y. Zhou, A. Righter, J. Hajjar","doi":"10.1109/ASICON.2013.6811976","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811976","url":null,"abstract":"The impact of gate series resistor on CDM protection effectiveness is systematically evaluated using SPICE simulation and verified with a modified VF-TLP test method. It is shown that the effectiveness of the resistor to a MOS input device is highly dependent on the size of the protected MOS device as well as on the types of ESD protection circuits. Larger MOS devices require smaller resistance values than smaller devices.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122875501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tire Pressure Monitor System (TPMS) is rather important for safety of automobile drivers. It monitors the tire pressure and sends alerts to the driver when the pressure condition is abnormal in order to avoid traffic accidents. Mixed signal Sock is a key solution to lower the cost.
{"title":"A novel ESD device for Whole-Chip ESD protection network of TPMS mixed signal SoC","authors":"Ningyuan Yin, Liji Wu, Tengfei Zhai, Xiangmin Zhang, Rui Zhu","doi":"10.1109/ASICON.2013.6812019","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812019","url":null,"abstract":"Tire Pressure Monitor System (TPMS) is rather important for safety of automobile drivers. It monitors the tire pressure and sends alerts to the driver when the pressure condition is abnormal in order to avoid traffic accidents. Mixed signal Sock is a key solution to lower the cost.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123002751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811906
Peng Chen, Rui Guan, Dongpo Chen
An improved VCO for compass navigation system (CNS) application is presented. It has a linearized KVCO and is robust to varactor bias variations. A voltage limit circuit is proposed to ensure that the varactors work in the depletion region. To compensate for active loop filter's lack of driving ability, a rail to rail opamp is used. Post-simulation results show that a better KVCO performance is achieved compared to the conventional one with tuning voltage changing from 0.15V to 1.65V. Implemented in a 0.18um CMOS process, the proposed VCO operates at 3.2 GHz with power supply of 1.8V.
{"title":"AVCO with F-V linearization techniques for CNS application","authors":"Peng Chen, Rui Guan, Dongpo Chen","doi":"10.1109/ASICON.2013.6811906","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811906","url":null,"abstract":"An improved VCO for compass navigation system (CNS) application is presented. It has a linearized KVCO and is robust to varactor bias variations. A voltage limit circuit is proposed to ensure that the varactors work in the depletion region. To compensate for active loop filter's lack of driving ability, a rail to rail opamp is used. Post-simulation results show that a better KVCO performance is achieved compared to the conventional one with tuning voltage changing from 0.15V to 1.65V. Implemented in a 0.18um CMOS process, the proposed VCO operates at 3.2 GHz with power supply of 1.8V.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129320784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811839
F. Fu, Liang Wang, Yu Lu, Jinxiang Wang
Task migration, an effective resource management approach, contributes to an increase of on-chip communication overhead. We propose an MMPI-based task migration mechanism to lower task migration overhead in NoC-based MPSoC. This task migration mechanism depends on MPSoC message passing interface (MMPI), which defines a parallel programming pattern that program is dependent of task mapping. In the migration mechanism, task state information is transferred to another PE. The migration overhead is lowered since the task migration is based on MMPI and task code is not transferred. Furthermore, the task migration mechanism does not require checkpoints to detect migration request. Experimental results show that the migration delay decreases around 28% without transferring task code.
{"title":"Low overhead task migration mechanism in NoC-based MPSoC","authors":"F. Fu, Liang Wang, Yu Lu, Jinxiang Wang","doi":"10.1109/ASICON.2013.6811839","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811839","url":null,"abstract":"Task migration, an effective resource management approach, contributes to an increase of on-chip communication overhead. We propose an MMPI-based task migration mechanism to lower task migration overhead in NoC-based MPSoC. This task migration mechanism depends on MPSoC message passing interface (MMPI), which defines a parallel programming pattern that program is dependent of task mapping. In the migration mechanism, task state information is transferred to another PE. The migration overhead is lowered since the task migration is based on MMPI and task code is not transferred. Furthermore, the task migration mechanism does not require checkpoints to detect migration request. Experimental results show that the migration delay decreases around 28% without transferring task code.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122406875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811865
R. He, Jianfei Xu, N. Yan, M. Hao
This paper presents a 20Gb/s Limiting Amplifier (LA) with the active interleaving feedback technique both to broaden the bandwidth and achieve flatness response. The LA includes an input match and DC offset cancellation (DCOC), a four-stage 3rd order amplifier core and an output buffer for test. Simulated in the 65nm CMOS technology, the LA exhibits a voltage gain of 38.5dB, a 3-dB bandwidth of 18GHz and an integrated input noise of 0.56mV with the area of only 0.45 × 0.25 mm2. The chip excluding buffer is supplied by 1.2V VDD and consumes DC power of 61mW.
{"title":"A 20 Gb/s Limiting Amplifier in 65nm CMOS technology","authors":"R. He, Jianfei Xu, N. Yan, M. Hao","doi":"10.1109/ASICON.2013.6811865","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811865","url":null,"abstract":"This paper presents a 20Gb/s Limiting Amplifier (LA) with the active interleaving feedback technique both to broaden the bandwidth and achieve flatness response. The LA includes an input match and DC offset cancellation (DCOC), a four-stage 3rd order amplifier core and an output buffer for test. Simulated in the 65nm CMOS technology, the LA exhibits a voltage gain of 38.5dB, a 3-dB bandwidth of 18GHz and an integrated input noise of 0.56mV with the area of only 0.45 × 0.25 mm2. The chip excluding buffer is supplied by 1.2V VDD and consumes DC power of 61mW.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129024689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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