Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811965
Lu Sun, Yuxiao Lu, Tingting Mo
A 10bit 300MHz analog-to-digital converter is presented. It uses medium-resolution SAR ADC to replace low-resolution Flash ADC to solve the high power consumption problem. The structure of sharing the same residue amplifier in two channels can further reduce the power consumption and correct the gain error between different channels. The asynchronous clock generator for SAR comparator and the improved capacitor array structure help to decrease SAR ADC's decision time. Simulation results in 65nm shows that it could have ENOB of 9.1 bits at 300MHz sampling. And its power consumption is only about 15.4mW.
{"title":"A 300MHz 10b time-interleaved pipelined-SAR ADC","authors":"Lu Sun, Yuxiao Lu, Tingting Mo","doi":"10.1109/ASICON.2013.6811965","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811965","url":null,"abstract":"A 10bit 300MHz analog-to-digital converter is presented. It uses medium-resolution SAR ADC to replace low-resolution Flash ADC to solve the high power consumption problem. The structure of sharing the same residue amplifier in two channels can further reduce the power consumption and correct the gain error between different channels. The asynchronous clock generator for SAR comparator and the improved capacitor array structure help to decrease SAR ADC's decision time. Simulation results in 65nm shows that it could have ENOB of 9.1 bits at 300MHz sampling. And its power consumption is only about 15.4mW.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"97 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133719665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811903
Qiuli Li, Yao Qian, Danzhu Lu, Zhiliang Hong
A stable LDO (Low Drop-Out linear regulator) using VCCS (Voltage Control Current Source) is presented. The LDO is designed and implemented on GF 2P4M 0.35 μm CMOS technology. Compared with previous compensation scheme, VCCS can implement a real stable LDO with a small on-chip capacitor of 1 pF, whose stability is not affected by the variable ESR (Equivalent Series Resistor). The united gain frequency can achieve 1.5 MHz, improving the transient response. Test result shows that the LDO is stable over the full load current, with a maximum output current of 100 mA.
{"title":"VCCS controlled LDO with small on-chip capacitor","authors":"Qiuli Li, Yao Qian, Danzhu Lu, Zhiliang Hong","doi":"10.1109/ASICON.2013.6811903","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811903","url":null,"abstract":"A stable LDO (Low Drop-Out linear regulator) using VCCS (Voltage Control Current Source) is presented. The LDO is designed and implemented on GF 2P4M 0.35 μm CMOS technology. Compared with previous compensation scheme, VCCS can implement a real stable LDO with a small on-chip capacitor of 1 pF, whose stability is not affected by the variable ESR (Equivalent Series Resistor). The united gain frequency can achieve 1.5 MHz, improving the transient response. Test result shows that the LDO is stable over the full load current, with a maximum output current of 100 mA.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115750908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811940
Jong-Ho Lee, Kyu-Bong Choi, Jongmin Shin
Design of 14 nm bulk FinFET is discussed and some properties are analyzed physically. The source/drain junction depth is the most important parameter to reduce off-current, and a punchthrough barrier of a peak concentration higher than ~2×1018 cm-3 should be formed just underneath the junction depth at the same time. Uniform body doping concentration needs to be designed to have a doping in the range of 2~4×1017 cm-3. The source/drain contact resistance can be reduced by increasing metal contact area on the source/drain region. The drain current fluctuation with the capture and emission of an electron in a trap inside the gate oxide is less than 2% at a VGS-Vth of 0.1 V, and increases slightly due to the increase of coupling as fin width decreases.
{"title":"Design and analysis of nano-scale bulk FinFETs","authors":"Jong-Ho Lee, Kyu-Bong Choi, Jongmin Shin","doi":"10.1109/ASICON.2013.6811940","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811940","url":null,"abstract":"Design of 14 nm bulk FinFET is discussed and some properties are analyzed physically. The source/drain junction depth is the most important parameter to reduce off-current, and a punchthrough barrier of a peak concentration higher than ~2×1018 cm-3 should be formed just underneath the junction depth at the same time. Uniform body doping concentration needs to be designed to have a doping in the range of 2~4×1017 cm-3. The source/drain contact resistance can be reduced by increasing metal contact area on the source/drain region. The drain current fluctuation with the capture and emission of an electron in a trap inside the gate oxide is less than 2% at a VGS-Vth of 0.1 V, and increases slightly due to the increase of coupling as fin width decreases.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114402186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811918
Jinming Zhao, Hailong Yao, Yici Cai, Qiang Zhou
With the increasing need of the SoC (System on a Chip) design automation tools, analog routing is attracting more and more attention. An interactive analog router called SIAR based on splitting graph model was presented in [15]. Based on SIAR, this paper presents a new splitting graph construction (SGC) algorithm to speed up the graph construction process, and thus speed up the whole analog routing process. The presented SGC algorithm has the following features: (1) auxiliary points are added according to the obstacles' corner points, (2) there is no need to construct all the grids along the boundaries of the expanded obstacles, (3) a fast polygon-to-rectangle conversion algorithm is adopted to directly construct the splitting tiles needed by the splitting graph. Experimental results are promising and show 2× speedup on average.
{"title":"A new splitting graph construction algorithm for SIAR router","authors":"Jinming Zhao, Hailong Yao, Yici Cai, Qiang Zhou","doi":"10.1109/ASICON.2013.6811918","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811918","url":null,"abstract":"With the increasing need of the SoC (System on a Chip) design automation tools, analog routing is attracting more and more attention. An interactive analog router called SIAR based on splitting graph model was presented in [15]. Based on SIAR, this paper presents a new splitting graph construction (SGC) algorithm to speed up the graph construction process, and thus speed up the whole analog routing process. The presented SGC algorithm has the following features: (1) auxiliary points are added according to the obstacles' corner points, (2) there is no need to construct all the grids along the boundaries of the expanded obstacles, (3) a fast polygon-to-rectangle conversion algorithm is adopted to directly construct the splitting tiles needed by the splitting graph. Experimental results are promising and show 2× speedup on average.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114904588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812032
Dan Liu, Chuan Jin
The design and measurement of low noise 32-channel X-ray readout integrated circuit (ROIC) are proposed in this paper. This ROIC has 32 analog channels collecting weak current from detectors, then transfers them to voltage and output in differential mode. This ROIC adapts low noise preamplifier and S/H circuit. Measure results show a dynamic range of larger than 10000:1 with 6pF integration capacitor. This ROIC has a very close noise performance with a famous commercial IC.
{"title":"Low noise design and measurement of 32-channel X-ray ROIC","authors":"Dan Liu, Chuan Jin","doi":"10.1109/ASICON.2013.6812032","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812032","url":null,"abstract":"The design and measurement of low noise 32-channel X-ray readout integrated circuit (ROIC) are proposed in this paper. This ROIC has 32 analog channels collecting weak current from detectors, then transfers them to voltage and output in differential mode. This ROIC adapts low noise preamplifier and S/H circuit. Measure results show a dynamic range of larger than 10000:1 with 6pF integration capacitor. This ROIC has a very close noise performance with a famous commercial IC.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127133845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812049
Jixuan Xiang, Jian Mei, Hao-Hsuan Chang, Fan Ye
This paper presents an 8-b 400-MS/s 2-b-per-cycle SAR ADC with a preset capacitive DAC, which is simulated in 65-nm CMOS process. This SAR ADC achieves rapid conversion rate and low power, leading SNDR to 48.9dB, SFDR to 57.8dB, and ENOB to 7.83 bits at 400-MS/s sampling rate and in 186MHz input signal. The ADC consumes 0.766mW, and the FoM is 7.9fJ/conversion-step at 400-MS/s sampling rate from a 1.2-V supply voltage.
本文提出了一种8-b 400-MS/s的2-b /周期SAR ADC，并在65nm CMOS工艺中进行了仿真。该SAR ADC实现了快速转换速率和低功耗，在400 ms /s采样率和186MHz输入信号下，SNDR为48.9dB, SFDR为57.8dB, ENOB为7.83位。ADC功耗为0.766mW, FoM为7.9fJ/转换步长，采样率为400 ms /s，电源电压为1.2 v。
{"title":"A 7.9-fJ/conversion-step 8-b 400-MS/s 2-b-per-cycle SAR ADC with A preset capacitive DAC","authors":"Jixuan Xiang, Jian Mei, Hao-Hsuan Chang, Fan Ye","doi":"10.1109/ASICON.2013.6812049","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812049","url":null,"abstract":"This paper presents an 8-b 400-MS/s 2-b-per-cycle SAR ADC with a preset capacitive DAC, which is simulated in 65-nm CMOS process. This SAR ADC achieves rapid conversion rate and low power, leading SNDR to 48.9dB, SFDR to 57.8dB, and ENOB to 7.83 bits at 400-MS/s sampling rate and in 186MHz input signal. The ADC consumes 0.766mW, and the FoM is 7.9fJ/conversion-step at 400-MS/s sampling rate from a 1.2-V supply voltage.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127263834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In MLC NAND flash system, the hybrid hard-decision /soft-decision LDPC decoder prefers a high throughput bit-flipping decoder. Therefore, the high-efficiency silicon implementation of bit-flipping decoder becomes a practically relevant topic. This paper presents a so-called fuzzy-decision bit-flipping decoding algorithm to reduce the hardware consumption and average iteration numbers. Simulations and VLSI design show that the proposed design solution can improve upto 10% higher decoding throughput, and meanwhile reduce upto 40% less silicon cost, without performance reducing.
{"title":"VLSI design of fuzzy-decision bit-flipping QC-LDPC decoder","authors":"Wenzhe Zhao, Minjie Lv, Hongbin Sun, Nanning Zheng, Tong Zhang","doi":"10.1109/ASICON.2013.6811972","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811972","url":null,"abstract":"In MLC NAND flash system, the hybrid hard-decision /soft-decision LDPC decoder prefers a high throughput bit-flipping decoder. Therefore, the high-efficiency silicon implementation of bit-flipping decoder becomes a practically relevant topic. This paper presents a so-called fuzzy-decision bit-flipping decoding algorithm to reduce the hardware consumption and average iteration numbers. Simulations and VLSI design show that the proposed design solution can improve upto 10% higher decoding throughput, and meanwhile reduce upto 40% less silicon cost, without performance reducing.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122354055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811829
Meng-Ting Hsu, Yu-Chang Hsieh, An-Cheng Ou
This paper presents a 3.1-10.6GHz low power and low noise amplifier(LNA) band on the cascode configuration. The circuit design consists of RC-feedback and forward body bias technique. The measurement results show the proposed UWB CS LNA can achieve a maximum power gain (S21) of 10.8dB with the 3dB bandwidth from 3.1GHz to 10.6GHz. The input reflection coefficient S11 and output reflection coefficient S22 are lower than -8.1dB and -9.5dB, respectively. A minimum noise figure of 5.5 dB, and an input third-order intercept point IIP3 of -6.4dBm. The power dissipation is 6.4mW at 1.1V supply voltage. This LNA occupies an area of 1.1*0.88mm2.
{"title":"Design of low power UWB CMOS LNA using RC feedback and body-bias technology","authors":"Meng-Ting Hsu, Yu-Chang Hsieh, An-Cheng Ou","doi":"10.1109/ASICON.2013.6811829","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811829","url":null,"abstract":"This paper presents a 3.1-10.6GHz low power and low noise amplifier(LNA) band on the cascode configuration. The circuit design consists of RC-feedback and forward body bias technique. The measurement results show the proposed UWB CS LNA can achieve a maximum power gain (S21) of 10.8dB with the 3dB bandwidth from 3.1GHz to 10.6GHz. The input reflection coefficient S11 and output reflection coefficient S22 are lower than -8.1dB and -9.5dB, respectively. A minimum noise figure of 5.5 dB, and an input third-order intercept point IIP3 of -6.4dBm. The power dissipation is 6.4mW at 1.1V supply voltage. This LNA occupies an area of 1.1*0.88mm2.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"431 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132245495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Because of the widely used of mixed-signal SoC, substrate coupling noise has become an important problem. A reasonable substrate model is necessary for estimating the impact of substrate noise. Compared with previous work, the proposed 3D hybrid model includes 3D RC substrate network for the aggressor and victim and macro model for the noise coupling path. Developed model of commonly used for isolating noise such as guard ring is also proposed. The efficiency of different regions of guard ring and single and double guard ring are compared and analyzed to draw a general conclusion.
{"title":"3D hybrid modeling of substrate coupling noise in lightly doped mixed-signal ICs","authors":"Yongsheng Wang, Fang Li, Hualing Yang, Yonglai Zhang, Yanhui Ren","doi":"10.1109/ASICON.2013.6811905","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811905","url":null,"abstract":"Because of the widely used of mixed-signal SoC, substrate coupling noise has become an important problem. A reasonable substrate model is necessary for estimating the impact of substrate noise. Compared with previous work, the proposed 3D hybrid model includes 3D RC substrate network for the aggressor and victim and macro model for the noise coupling path. Developed model of commonly used for isolating noise such as guard ring is also proposed. The efficiency of different regions of guard ring and single and double guard ring are compared and analyzed to draw a general conclusion.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130604833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811859
Wenjian Yu
In this paper, we present the techniques in RWCap2, which is a fast capacitance field solver for VLSI interconnects. The solver is based on the floating random walk (FRW) algorithm for capacitance extraction. Hence, it has the advantages of less memory usage, better parallelism and tunable accuracy over the conventional methods for capacitance field solver. To improve the computational speed of the FRW algorithm, and equip it for the extraction task with chip-scale large structures, several techniques are proposed and integrated into RWCap2. We will introduce the usage of the solver and demonstrate its efficiency for capacitance extraction.
{"title":"RWCap2: Advanced floating random walk solver for the capacitance extraction of VLSI interconnects","authors":"Wenjian Yu","doi":"10.1109/ASICON.2013.6811859","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811859","url":null,"abstract":"In this paper, we present the techniques in RWCap2, which is a fast capacitance field solver for VLSI interconnects. The solver is based on the floating random walk (FRW) algorithm for capacitance extraction. Hence, it has the advantages of less memory usage, better parallelism and tunable accuracy over the conventional methods for capacitance field solver. To improve the computational speed of the FRW algorithm, and equip it for the extraction task with chip-scale large structures, several techniques are proposed and integrated into RWCap2. We will introduce the usage of the solver and demonstrate its efficiency for capacitance extraction.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126641520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：