Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811980
Xiang Wang, Su Zhang, Wei Ni, Y. Song, Yanhui Yang, Jichun Bu
Reconfigurable processors are noticeable for their flexibility and high computation performance. Combining a general purpose processor with a reconfigurable coprocessor can improve the overall system performance. As wide range of algorithms have appeared due to the increasing complexity of applications, the general purpose processors undertake more serial computing tasks, which also leads to more time consumption during the task switching. Meanwhile, higher bandwidth demand comes with the increasing of computation efficiency. A hybrid reconfigurable coprocessor has been proposed here, which reduces its dependence on the general purpose processor. Optimized L2-cache has been designed to enhance the data locality and reusability. The proposed coprocessor based on an FPGA has been implemented which can operate at 100MHz. Experimental results show that much better performance has been achieved with this proposed coprocessor.
{"title":"Design of a hybrid reconfigurable coprocessor","authors":"Xiang Wang, Su Zhang, Wei Ni, Y. Song, Yanhui Yang, Jichun Bu","doi":"10.1109/ASICON.2013.6811980","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811980","url":null,"abstract":"Reconfigurable processors are noticeable for their flexibility and high computation performance. Combining a general purpose processor with a reconfigurable coprocessor can improve the overall system performance. As wide range of algorithms have appeared due to the increasing complexity of applications, the general purpose processors undertake more serial computing tasks, which also leads to more time consumption during the task switching. Meanwhile, higher bandwidth demand comes with the increasing of computation efficiency. A hybrid reconfigurable coprocessor has been proposed here, which reduces its dependence on the general purpose processor. Optimized L2-cache has been designed to enhance the data locality and reusability. The proposed coprocessor based on an FPGA has been implemented which can operate at 100MHz. Experimental results show that much better performance has been achieved with this proposed coprocessor.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129285811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811884
Bo Wang, Jinhai Zhang, E. Ngoya
The reference spur level is one of the big challenges during the PLL design. Caused by many reasons such as the timing/current mismatch and the leakage current from the PFD/CP and loop filter (LF), the reference spur is hard to be predicted. Using the novel open-loop algorithm instead of the traditional close-loop method, the proposed method allows for the quick prediction of the spur level during the design of the PLL building blocks, i.e., before the end of full PLL. In this paper, the spur transfer function is derived, and the method is implemented in Verilog-A. The prediction results match well with the close-loop transistor-level simulation.
{"title":"A reference spur estimation method for integer-N PLLs","authors":"Bo Wang, Jinhai Zhang, E. Ngoya","doi":"10.1109/ASICON.2013.6811884","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811884","url":null,"abstract":"The reference spur level is one of the big challenges during the PLL design. Caused by many reasons such as the timing/current mismatch and the leakage current from the PFD/CP and loop filter (LF), the reference spur is hard to be predicted. Using the novel open-loop algorithm instead of the traditional close-loop method, the proposed method allows for the quick prediction of the spur level during the design of the PLL building blocks, i.e., before the end of full PLL. In this paper, the spur transfer function is derived, and the method is implemented in Verilog-A. The prediction results match well with the close-loop transistor-level simulation.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128814773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812045
Yunpu Hu, Songping Mai, Yixin Zhao, Chun Zhang
Analog switch is a basic component in neural stimulators as it plays an important role in the control process of opening or closing stimulation, switching electrode polarity or power supply. In implantable stimulator circuit, the switch is usually required to work under a wide-range changing voltage and keep a fairly low on-resistance and low charge injection. In this paper, a switch and its driving system are proposed. The driving system can provide a stable high voltage to drive the NMOS transistor switch, thus solving conflicts between high voltage output and low voltage supply. According to the result from transistor-level simulation based on 0.35um CMOS high-voltage technology, the analog switch can achieve fast speed (ton=70ns, toff=280ns), low and flat resistance (4.5Ohm on average), low charge injection (20pC), extremely low current leak(36pA), and wide working voltage range from 1.8V to 12V, which completely meets the application requirement of neural stimulators.
{"title":"Low-resistance wide-voltage-range analog switch for implantable neural stimulators","authors":"Yunpu Hu, Songping Mai, Yixin Zhao, Chun Zhang","doi":"10.1109/ASICON.2013.6812045","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812045","url":null,"abstract":"Analog switch is a basic component in neural stimulators as it plays an important role in the control process of opening or closing stimulation, switching electrode polarity or power supply. In implantable stimulator circuit, the switch is usually required to work under a wide-range changing voltage and keep a fairly low on-resistance and low charge injection. In this paper, a switch and its driving system are proposed. The driving system can provide a stable high voltage to drive the NMOS transistor switch, thus solving conflicts between high voltage output and low voltage supply. According to the result from transistor-level simulation based on 0.35um CMOS high-voltage technology, the analog switch can achieve fast speed (ton=70ns, toff=280ns), low and flat resistance (4.5Ohm on average), low charge injection (20pC), extremely low current leak(36pA), and wide working voltage range from 1.8V to 12V, which completely meets the application requirement of neural stimulators.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129046094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811904
Weijie Chen, Hailong Yao, Yici Cai, Qiang Zhou
With the advancement of analog and mixed-signal (AMS) circuits, analog routing is attracting more and more concern. This paper presents a new analog gridless routing method fully considering different design rule constraints, including wire and via width/spacing constraints, especially the minimum area constraint. A modified A* searching algorithm is presented to search the multi-layer routing path that satisfies the minimum area constraint for each routing layer. Experimental results are promising and show that the presented analog router successfully finds valid routing paths for all the testcases without any min-area design rule violations.
{"title":"Analog routing considering min-area constraint","authors":"Weijie Chen, Hailong Yao, Yici Cai, Qiang Zhou","doi":"10.1109/ASICON.2013.6811904","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811904","url":null,"abstract":"With the advancement of analog and mixed-signal (AMS) circuits, analog routing is attracting more and more concern. This paper presents a new analog gridless routing method fully considering different design rule constraints, including wire and via width/spacing constraints, especially the minimum area constraint. A modified A* searching algorithm is presented to search the multi-layer routing path that satisfies the minimum area constraint for each routing layer. Experimental results are promising and show that the presented analog router successfully finds valid routing paths for all the testcases without any min-area design rule violations.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115930685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811958
Xuan Yang, Xiaole Cui, Chao Wang, Chung-Len Lee
State transition of nodes in the circuit generates heat which usually needs to be minimized for reliability consideration. In this work, instead, the heat generated is used to burn-in the CUT. A burn-in test pattern selection technique based on the ATPG approach for maximizing the dynamic power of the CUT is proposed. Experimental results show that the technique is effective in selecting the patterns which offer maximal power. It can be applied into the burn-in of logic circuits and SoCs in an energy saving manner.
{"title":"A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique","authors":"Xuan Yang, Xiaole Cui, Chao Wang, Chung-Len Lee","doi":"10.1109/ASICON.2013.6811958","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811958","url":null,"abstract":"State transition of nodes in the circuit generates heat which usually needs to be minimized for reliability consideration. In this work, instead, the heat generated is used to burn-in the CUT. A burn-in test pattern selection technique based on the ATPG approach for maximizing the dynamic power of the CUT is proposed. Experimental results show that the technique is effective in selecting the patterns which offer maximal power. It can be applied into the burn-in of logic circuits and SoCs in an energy saving manner.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"744 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116112417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811896
Chaojiang Li, Dawn Wang, Myra Boenke, T. Letavic, J. Cohn
A System-On-Chip (SOC) demonstrator integrating a low-noise IEEE 802.15.4 Transmitter and a DC-DC converter on a 0.18um High Voltage (HV) and RF CMOS process is presented in this paper. Noise isolation performance is critical to success of this type of SOC. A complete direct conversion transmitter was designed and various Quadrature VCO topologies were analyzed and compared based on the phase noise performance, device reliability, design robustness and image rejection. The final QVCO used in the transmitter has a FOM of 187dB, leading to an overall phase noise of -123dBc/Hz at 1MHz offset. The deep Nwell from HVCMOS process can be effectively used to provide isolation between the circuit blocks with measured results showing a sufficient noise isolation between the sensitive RF circuit and the switching 10MHz DC-DC converter.
{"title":"An integrated zigbee transmitter and DC-DC converter on 0.18μm HV RF CMOS technology","authors":"Chaojiang Li, Dawn Wang, Myra Boenke, T. Letavic, J. Cohn","doi":"10.1109/ASICON.2013.6811896","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811896","url":null,"abstract":"A System-On-Chip (SOC) demonstrator integrating a low-noise IEEE 802.15.4 Transmitter and a DC-DC converter on a 0.18um High Voltage (HV) and RF CMOS process is presented in this paper. Noise isolation performance is critical to success of this type of SOC. A complete direct conversion transmitter was designed and various Quadrature VCO topologies were analyzed and compared based on the phase noise performance, device reliability, design robustness and image rejection. The final QVCO used in the transmitter has a FOM of 187dB, leading to an overall phase noise of -123dBc/Hz at 1MHz offset. The deep Nwell from HVCMOS process can be effectively used to provide isolation between the circuit blocks with measured results showing a sufficient noise isolation between the sensitive RF circuit and the switching 10MHz DC-DC converter.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116709808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811895
Chu-Hsiang Chia, Pui-Sun Lei, R. Chang, Wei-Chi Wang
This paper presents a mix-signal, nonlinear weighted PID control DC-DC converter using TSMC 0.25 μm process and the input and output voltages are 12 V and 1 V. The maximum output power is 3 W. The digital control circuit is powered by the LDO when start-up. The output voltages 1 V and 2.5 V are produced by the series buck converter. The first buck stage provides 2.5 V output for powering the digital circuit only after start-up. The second buck stage provides output 1 V as the final output for the converter. The nonlinear weighted PID control improves 80% of the transient response time than the traditional PID control method.
{"title":"A nonlinear weighted PID controlled 12V to 1V DC-DC converter with transient suppression","authors":"Chu-Hsiang Chia, Pui-Sun Lei, R. Chang, Wei-Chi Wang","doi":"10.1109/ASICON.2013.6811895","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811895","url":null,"abstract":"This paper presents a mix-signal, nonlinear weighted PID control DC-DC converter using TSMC 0.25 μm process and the input and output voltages are 12 V and 1 V. The maximum output power is 3 W. The digital control circuit is powered by the LDO when start-up. The output voltages 1 V and 2.5 V are produced by the series buck converter. The first buck stage provides 2.5 V output for powering the digital circuit only after start-up. The second buck stage provides output 1 V as the final output for the converter. The nonlinear weighted PID control improves 80% of the transient response time than the traditional PID control method.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116660209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812029
Longcheng Que, Yiying Du, Jian Lv, Yadong Jiang
Based on dynamic element matching (DEM) and pseudorandom noise (PN), a digital background calibration scheme, applicable to mu ltistage pipelined analog-to-digital converters (PADCs), to correct the linearity errors resulting from capacitance mismatches is presented. This calibration technique scheme takes advantage of the PN sequence to extract linearity errors and DEM to make sure the errors of all the capacitances can be extracted. In the proposed method, capacitance mismatches are corrected, while the SNR is not degraded for the pseudorandom noise sequence injected into the system. Experimental results show that ENOB is 10.96 bits and SFDR achieves 85.1230 dB.
{"title":"Background calibration techniques for multistage pipelined ADCs with dynamic element matching and pseudorandom noise","authors":"Longcheng Que, Yiying Du, Jian Lv, Yadong Jiang","doi":"10.1109/ASICON.2013.6812029","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812029","url":null,"abstract":"Based on dynamic element matching (DEM) and pseudorandom noise (PN), a digital background calibration scheme, applicable to mu ltistage pipelined analog-to-digital converters (PADCs), to correct the linearity errors resulting from capacitance mismatches is presented. This calibration technique scheme takes advantage of the PN sequence to extract linearity errors and DEM to make sure the errors of all the capacitances can be extracted. In the proposed method, capacitance mismatches are corrected, while the SNR is not degraded for the pseudorandom noise sequence injected into the system. Experimental results show that ENOB is 10.96 bits and SFDR achieves 85.1230 dB.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116052042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811862
Bing Jing, Hao Chen, Fan Ye, Ning Li, Junyan Ren
This paper proposes a novel synchronizer consisting of timing synchronization module, automatic gain control, CFO and IQ mismatch compensation. Correlation with threshold search algorithm is used in the timing synchronization module. A double close-loop algorithm is used in the automatic gain control module to improve adjustable range and convergence. What is more, the carrier frequency offset and IQ mismatch is estimated and compensated in the digital compensation module. According to the results of synthesis using 0.13um CMOS process, the proposed synchronizer could achieve the same frequency of 132MHz with only about 50% gate count and power consumption of the traditional synchronizer.
{"title":"Low-complexity synchronizer used in DC-OFDM UWB system","authors":"Bing Jing, Hao Chen, Fan Ye, Ning Li, Junyan Ren","doi":"10.1109/ASICON.2013.6811862","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811862","url":null,"abstract":"This paper proposes a novel synchronizer consisting of timing synchronization module, automatic gain control, CFO and IQ mismatch compensation. Correlation with threshold search algorithm is used in the timing synchronization module. A double close-loop algorithm is used in the automatic gain control module to improve adjustable range and convergence. What is more, the carrier frequency offset and IQ mismatch is estimated and compensated in the digital compensation module. According to the results of synthesis using 0.13um CMOS process, the proposed synchronizer could achieve the same frequency of 132MHz with only about 50% gate count and power consumption of the traditional synchronizer.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127205531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812067
Wenjian Yu, Siyu Yang, Qingqing Zhang
An accurate yet fast approach is developed to calculate the 2D coupling capacitance between the through silicon via (TSV) and horizontal interconnect wire in 3D IC. We consider the realistic cylinder shape of TSV, and derive the analytical formulas utilizing the idea of field-based analysis. To improve the accuracy, theoretical and numerical results are used to calibrate the formulas. The proposed approach is compared with the commercial field solver Raphael using advanced finite difference method. For the TSV with diameter between 5μm and 10μm and wire with length within 20μm, the error of proposed approach is within 8%. While comparing the computational time, the latter is over 5000X faster than the former.
{"title":"Analytical model of the coupling capacitance between cylindrical through silicon via and horizontal interconnect in 3D IC","authors":"Wenjian Yu, Siyu Yang, Qingqing Zhang","doi":"10.1109/ASICON.2013.6812067","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812067","url":null,"abstract":"An accurate yet fast approach is developed to calculate the 2D coupling capacitance between the through silicon via (TSV) and horizontal interconnect wire in 3D IC. We consider the realistic cylinder shape of TSV, and derive the analytical formulas utilizing the idea of field-based analysis. To improve the accuracy, theoretical and numerical results are used to calibrate the formulas. The proposed approach is compared with the commercial field solver Raphael using advanced finite difference method. For the TSV with diameter between 5μm and 10μm and wire with length within 20μm, the error of proposed approach is within 8%. While comparing the computational time, the latter is over 5000X faster than the former.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126839630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：