Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811955
R. Wong, R. Fung, Shi-Jie Wen
Data rates in networking applications have increased as demand for more data increases. To achieve the high performance, the data rates in high speed IOs have continued to increase. These high data rates require the IO capacitances have to be very low. ESD protection structures have traditionally been large to handle the large transient currents. Recently, the high speed IO has limited the capacitance associated with ESD structures, making ESD protection design for high speed IOs extremely challenging. This paper will discuss the networking industry's trends in high speed IOs, the capacitance requirements and resulting challenges for ESD protection designs. To achieve the proper ESD protection, on chip ESD protection schemes will need to change and/or ESD protection specifications may need to lower targeted protection levels. This is a hotly argued topic in the high speed networking industry, which may change the next-generation ESD protection design dramatically. We will discuss the possible ESD design outcomes due to the high speed IOs scaling trends.
{"title":"Networking industry trends in ESD protection for high speed IOs","authors":"R. Wong, R. Fung, Shi-Jie Wen","doi":"10.1109/ASICON.2013.6811955","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811955","url":null,"abstract":"Data rates in networking applications have increased as demand for more data increases. To achieve the high performance, the data rates in high speed IOs have continued to increase. These high data rates require the IO capacitances have to be very low. ESD protection structures have traditionally been large to handle the large transient currents. Recently, the high speed IO has limited the capacitance associated with ESD structures, making ESD protection design for high speed IOs extremely challenging. This paper will discuss the networking industry's trends in high speed IOs, the capacitance requirements and resulting challenges for ESD protection designs. To achieve the proper ESD protection, on chip ESD protection schemes will need to change and/or ESD protection specifications may need to lower targeted protection levels. This is a hotly argued topic in the high speed networking industry, which may change the next-generation ESD protection design dramatically. We will discuss the possible ESD design outcomes due to the high speed IOs scaling trends.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114171777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811898
Baoguang Liu, Yuan Wang, Guangliang Guo, S. Jia, Xing Zhang
A novel dynamic element match (DEM) named Segmented Thermo Data Weighted Average (STDWA) for the Nyquist-rate current-steering digital to analog converter (DAC) has been presented in this paper. In this method, when the input code changes, it only increase or decrease the chosen unit current source in order to reduce the signal glitch. Compared with full random DEM technique, this approach can reach a better static performance. Meanwhile, it can eliminate signal dependent distortions to achieve good linearity at high sampling frequencies as well as other DEM implementations.
{"title":"A novel dynamic element match technique in current-steering DAC","authors":"Baoguang Liu, Yuan Wang, Guangliang Guo, S. Jia, Xing Zhang","doi":"10.1109/ASICON.2013.6811898","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811898","url":null,"abstract":"A novel dynamic element match (DEM) named Segmented Thermo Data Weighted Average (STDWA) for the Nyquist-rate current-steering digital to analog converter (DAC) has been presented in this paper. In this method, when the input code changes, it only increase or decrease the chosen unit current source in order to reduce the signal glitch. Compared with full random DEM technique, this approach can reach a better static performance. Meanwhile, it can eliminate signal dependent distortions to achieve good linearity at high sampling frequencies as well as other DEM implementations.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114871628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811868
Yang Zhao, B. Liu, Zhiliang Hong
A new time-interleaved band-pass ΣΔ modulator architecture targeted for Class-S power amplifier is presented. To demonstrate the feasibility a 10th order 60MHz bandwidth modulator based on this architecture is designed in a standard 65nm CMOS process. 54dB of signal noise ratio (SNR) is gotten at a sample rate of 1.92GHz through simulation.
{"title":"Design of a time-interleaved band-pass ΣΔ modulator for Class-S power amplifier","authors":"Yang Zhao, B. Liu, Zhiliang Hong","doi":"10.1109/ASICON.2013.6811868","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811868","url":null,"abstract":"A new time-interleaved band-pass ΣΔ modulator architecture targeted for Class-S power amplifier is presented. To demonstrate the feasibility a 10th order 60MHz bandwidth modulator based on this architecture is designed in a standard 65nm CMOS process. 54dB of signal noise ratio (SNR) is gotten at a sample rate of 1.92GHz through simulation.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116064089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811921
Quan Pan, Zhengxiong Hou, Yipeng Wang, C. Yue
A silicon avalanche P-well/Deep N-well photodetectors is fabricated in standard 65-nm CMOS technology without any process modification. By adopting the lightly doped P-well as the P-terminal, a wider depletion region is achieved in a deeper position from the silicon surface. This photodetector achieves a -3-dB bandwidth of 1.1 GHz and a responsivity of 160 mA/W at 12.3 V with 850 nm light input. An integrated receiver using the proposed APD is able to operate at 4 Gbps.
{"title":"A 65-nm CMOS P-well/Deep N-well avalanche photodetector for integrated 850-nm optical","authors":"Quan Pan, Zhengxiong Hou, Yipeng Wang, C. Yue","doi":"10.1109/ASICON.2013.6811921","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811921","url":null,"abstract":"A silicon avalanche P-well/Deep N-well photodetectors is fabricated in standard 65-nm CMOS technology without any process modification. By adopting the lightly doped P-well as the P-terminal, a wider depletion region is achieved in a deeper position from the silicon surface. This photodetector achieves a -3-dB bandwidth of 1.1 GHz and a responsivity of 160 mA/W at 12.3 V with 850 nm light input. An integrated receiver using the proposed APD is able to operate at 4 Gbps.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116138801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811893
You Li, Feng Zhang, Yumei Zhou
The paper presents a small area and low power equalizer for the high-loss serial backplane built in 65 nm CMOS technology. To mitigate the effects of channel loss and other impairments, a programmable continuous time linear equalizer (CTLE) and a programmable 5-tap decision feedback equalizer (DFE) are used in the receiver. In which DFE employs a loop-unrolling structure to meet timing constraints. Furthermore power and area savings are achieved by using two kinds of D-flip-flop (DFF) in proposed DFE and CMOS-style rail-to-rail clocking. The whole equalizer occupies 0.0091 mm2 and consumes 11-mW under a 1.2 V supply when equalizing 6.25 Gb/s data passed over a FR4 PCB channel with 10~28 dB of loss at Nyquist frequency.
{"title":"A novel equalizer for the high-loss backplane at Nyquist frequency","authors":"You Li, Feng Zhang, Yumei Zhou","doi":"10.1109/ASICON.2013.6811893","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811893","url":null,"abstract":"The paper presents a small area and low power equalizer for the high-loss serial backplane built in 65 nm CMOS technology. To mitigate the effects of channel loss and other impairments, a programmable continuous time linear equalizer (CTLE) and a programmable 5-tap decision feedback equalizer (DFE) are used in the receiver. In which DFE employs a loop-unrolling structure to meet timing constraints. Furthermore power and area savings are achieved by using two kinds of D-flip-flop (DFF) in proposed DFE and CMOS-style rail-to-rail clocking. The whole equalizer occupies 0.0091 mm2 and consumes 11-mW under a 1.2 V supply when equalizing 6.25 Gb/s data passed over a FR4 PCB channel with 10~28 dB of loss at Nyquist frequency.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123254357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tire Pressure Monitor System (TPMS) is rather important for safety of automobile drivers. It monitors the tire pressure and sends alerts to the driver when the pressure condition is abnormal in order to avoid traffic accidents. Mixed signal Sock is a key solution to lower the cost.
{"title":"A novel ESD device for Whole-Chip ESD protection network of TPMS mixed signal SoC","authors":"Ningyuan Yin, Liji Wu, Tengfei Zhai, Xiangmin Zhang, Rui Zhu","doi":"10.1109/ASICON.2013.6812019","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812019","url":null,"abstract":"Tire Pressure Monitor System (TPMS) is rather important for safety of automobile drivers. It monitors the tire pressure and sends alerts to the driver when the pressure condition is abnormal in order to avoid traffic accidents. Mixed signal Sock is a key solution to lower the cost.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123002751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812006
Tianyi Hu
3D video makes it possible for audience to enjoy stereo perception by means of multi-view rendering. Revealing a more realistic and vivid world that conventional 2D video can never achieve, this innovation becomes an important direction of the development of multimedia in the future, thus converting existed 2D video into 3D ones has its great significance. This paper presents a semi-auto 2D-to-3D video conversion method, which segments a video flow into key frames and non-key frames, then utilizes an interactive algorithm as well as an efficient edge detection technique to acquire depth map for a single key frame. Depth map for non-key frame is derived by motion tracking and compensation automatically. The final 3D video flow can be rendered based on the depth map calculated above.
{"title":"A semi-auto interactive 2D-to-3D video conversion technique based on edge detection","authors":"Tianyi Hu","doi":"10.1109/ASICON.2013.6812006","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812006","url":null,"abstract":"3D video makes it possible for audience to enjoy stereo perception by means of multi-view rendering. Revealing a more realistic and vivid world that conventional 2D video can never achieve, this innovation becomes an important direction of the development of multimedia in the future, thus converting existed 2D video into 3D ones has its great significance. This paper presents a semi-auto 2D-to-3D video conversion method, which segments a video flow into key frames and non-key frames, then utilizes an interactive algorithm as well as an efficient edge detection technique to acquire depth map for a single key frame. Depth map for non-key frame is derived by motion tracking and compensation automatically. The final 3D video flow can be rendered based on the depth map calculated above.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123415770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812048
Jian Mei, Jixuan Xiang, Huabin Chen, Fan Ye, Junyan Ren
A 4-mW 8-b 600-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is simulated in a standard 65-nm CMOS. By adopting reference capacitive DAC, four-input comparator and the data calibration unit, the proposed ADC could achieve higher speed. As simulated at sampling rate of 600 MS/s, the proposed ADC could achieve a peak SNR of 52.7 dB and maintain ENOB higher than 7.5 bits up to 302-MHz input signal frequency. The FoM of proposed ADC is 34.5 fJ/conversion-step at a 600-MS/s sampling rate and a 1.2-V supply.
在标准65nm CMOS中模拟了一个4 mw 8 b 600 ms /s 2 b/ cycle (2 b/C)逐次逼近寄存器(SAR)模数转换器(ADC)。通过采用基准电容式DAC、四输入比较器和数据校准单元，可以实现更高的速度。在采样率为600 MS/s的情况下，该ADC的峰值信噪比为52.7 dB，在输入频率为302 mhz的情况下，ENOB保持在7.5位以上。该ADC的FoM为34.5 fJ/转换步长，采样率为600 ms /s，电源为1.2 v。
{"title":"A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC","authors":"Jian Mei, Jixuan Xiang, Huabin Chen, Fan Ye, Junyan Ren","doi":"10.1109/ASICON.2013.6812048","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812048","url":null,"abstract":"A 4-mW 8-b 600-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is simulated in a standard 65-nm CMOS. By adopting reference capacitive DAC, four-input comparator and the data calibration unit, the proposed ADC could achieve higher speed. As simulated at sampling rate of 600 MS/s, the proposed ADC could achieve a peak SNR of 52.7 dB and maintain ENOB higher than 7.5 bits up to 302-MHz input signal frequency. The FoM of proposed ADC is 34.5 fJ/conversion-step at a 600-MS/s sampling rate and a 1.2-V supply.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123431397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811976
Y. Zhou, A. Righter, J. Hajjar
The impact of gate series resistor on CDM protection effectiveness is systematically evaluated using SPICE simulation and verified with a modified VF-TLP test method. It is shown that the effectiveness of the resistor to a MOS input device is highly dependent on the size of the protected MOS device as well as on the types of ESD protection circuits. Larger MOS devices require smaller resistance values than smaller devices.
{"title":"Investigation on effectiveness of series gate resistor in CDM ESD protection designs","authors":"Y. Zhou, A. Righter, J. Hajjar","doi":"10.1109/ASICON.2013.6811976","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811976","url":null,"abstract":"The impact of gate series resistor on CDM protection effectiveness is systematically evaluated using SPICE simulation and verified with a modified VF-TLP test method. It is shown that the effectiveness of the resistor to a MOS input device is highly dependent on the size of the protected MOS device as well as on the types of ESD protection circuits. Larger MOS devices require smaller resistance values than smaller devices.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122875501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811978
Gaowei Xu, Yao Zou, Jun Han, Xiaoyang Zeng
This paper compares three low power schemes for the multi-hierarchy pipeline design of fixed point finite impulse response (FIR) digital filters, and we adopt an optimal CSD encoding method, minimizing the number of adders/subtractions in the design. In addition, a 16-bit, 16 taps low-pass FIR filter is designed to investigate the performance of the three different algorithms. To evaluate the performance of them, the designs are synthesized in SMIC 65nm library. The evaluation shows that the optimal CSD scheme is better than the other two low-power methods at the same throughput.
{"title":"Low power design for FIR filter","authors":"Gaowei Xu, Yao Zou, Jun Han, Xiaoyang Zeng","doi":"10.1109/ASICON.2013.6811978","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811978","url":null,"abstract":"This paper compares three low power schemes for the multi-hierarchy pipeline design of fixed point finite impulse response (FIR) digital filters, and we adopt an optimal CSD encoding method, minimizing the number of adders/subtractions in the design. In addition, a 16-bit, 16 taps low-pass FIR filter is designed to investigate the performance of the three different algorithms. To evaluate the performance of them, the designs are synthesized in SMIC 65nm library. The evaluation shows that the optimal CSD scheme is better than the other two low-power methods at the same throughput.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"355 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125773315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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