Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812022
Long He, Zhihui Chen, A. Jiang
Local hysteretic diode currents depending on domain orientations have been observed in epitaxial BiFeO3 thin films. The mechanism behind the bilateral and unilateral current hysteresis as well as retention of the nanodomains has been discussed in the films with different thicknesses. Piezoelectric force microscopy investigations reveal principle of resistive property is the switchable polarization control of hysteretic diode currents other than the creation and rupture of the conductive paths in other resistive random access memories mediated by mobile charged defects. With the investigation of different leakage current models, it has been found that the space-charge limited current (SCLC) dominates the conduction.
{"title":"Piezoelectric force microscopy study of local bipolar diode current dependence of preferential domain orientation in BiFeO3 thin films with different thicknesses","authors":"Long He, Zhihui Chen, A. Jiang","doi":"10.1109/ASICON.2013.6812022","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812022","url":null,"abstract":"Local hysteretic diode currents depending on domain orientations have been observed in epitaxial BiFeO3 thin films. The mechanism behind the bilateral and unilateral current hysteresis as well as retention of the nanodomains has been discussed in the films with different thicknesses. Piezoelectric force microscopy investigations reveal principle of resistive property is the switchable polarization control of hysteretic diode currents other than the creation and rupture of the conductive paths in other resistive random access memories mediated by mobile charged defects. With the investigation of different leakage current models, it has been found that the space-charge limited current (SCLC) dominates the conduction.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133503756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812003
Zheng Tang, Jing Xie, Zhigang Mao
The processors' architecture design plays an important role in high performance DSP era, where how to balance the power consumption and the computing ability is always a great concern. In this paper we propose an architecture scheme with VLIW instruction driven adaptive pipeline coupling technique for a multi-core processor design to achieve the high computing performance with a low powered capability. Combined with the loop buffering design and implementation, the scheme is evaluated with the typical DSP application and the results show that the performance is improved about 43.4% while the power consumption is reduced by 48.7% in average.
{"title":"A novel architecture scheme with adaptive pipeline coupling technique for DSP processor design","authors":"Zheng Tang, Jing Xie, Zhigang Mao","doi":"10.1109/ASICON.2013.6812003","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812003","url":null,"abstract":"The processors' architecture design plays an important role in high performance DSP era, where how to balance the power consumption and the computing ability is always a great concern. In this paper we propose an architecture scheme with VLIW instruction driven adaptive pipeline coupling technique for a multi-core processor design to achieve the high computing performance with a low powered capability. Combined with the loop buffering design and implementation, the scheme is evaluated with the typical DSP application and the results show that the performance is improved about 43.4% while the power consumption is reduced by 48.7% in average.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133951736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811921
Quan Pan, Zhengxiong Hou, Yipeng Wang, C. Yue
A silicon avalanche P-well/Deep N-well photodetectors is fabricated in standard 65-nm CMOS technology without any process modification. By adopting the lightly doped P-well as the P-terminal, a wider depletion region is achieved in a deeper position from the silicon surface. This photodetector achieves a -3-dB bandwidth of 1.1 GHz and a responsivity of 160 mA/W at 12.3 V with 850 nm light input. An integrated receiver using the proposed APD is able to operate at 4 Gbps.
{"title":"A 65-nm CMOS P-well/Deep N-well avalanche photodetector for integrated 850-nm optical","authors":"Quan Pan, Zhengxiong Hou, Yipeng Wang, C. Yue","doi":"10.1109/ASICON.2013.6811921","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811921","url":null,"abstract":"A silicon avalanche P-well/Deep N-well photodetectors is fabricated in standard 65-nm CMOS technology without any process modification. By adopting the lightly doped P-well as the P-terminal, a wider depletion region is achieved in a deeper position from the silicon surface. This photodetector achieves a -3-dB bandwidth of 1.1 GHz and a responsivity of 160 mA/W at 12.3 V with 850 nm light input. An integrated receiver using the proposed APD is able to operate at 4 Gbps.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116138801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811868
Yang Zhao, B. Liu, Zhiliang Hong
A new time-interleaved band-pass ΣΔ modulator architecture targeted for Class-S power amplifier is presented. To demonstrate the feasibility a 10th order 60MHz bandwidth modulator based on this architecture is designed in a standard 65nm CMOS process. 54dB of signal noise ratio (SNR) is gotten at a sample rate of 1.92GHz through simulation.
{"title":"Design of a time-interleaved band-pass ΣΔ modulator for Class-S power amplifier","authors":"Yang Zhao, B. Liu, Zhiliang Hong","doi":"10.1109/ASICON.2013.6811868","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811868","url":null,"abstract":"A new time-interleaved band-pass ΣΔ modulator architecture targeted for Class-S power amplifier is presented. To demonstrate the feasibility a 10th order 60MHz bandwidth modulator based on this architecture is designed in a standard 65nm CMOS process. 54dB of signal noise ratio (SNR) is gotten at a sample rate of 1.92GHz through simulation.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116064089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811881
Zhiqing Chen, Qi Zhang, Ning Wang, D. Yuan, Guohong Li, Hui Wang, Songlin Feng
A CMOS phase-locked loop (PLL) with low reference spur and wide tuning range implemented in 0.18μm CMOS technology is presented in this paper. The design is based on the programmable integer-N PLL structure and the center frequency is around 480MHz for CMOS Image Sensor applications. A pseudo-differential current-starved multi-band ring oscillator is proposed to widen the tuning range. Several circuit techniques are used to minimize the phase frequency detector (PFD) UP/DN timing mismatch and charge pump (CP) current glitches, which reduce the reference spur. Implemented in the 0.18μm CMOS technology, the simulation results show that the -52.6dBc reference spur and the 94.4% tuning range (covering from 30MHz to 1050MHz) can be achieved.
{"title":"A low spur CMOS phase-locked loop with wide tuning range for CMOS Image Sensor","authors":"Zhiqing Chen, Qi Zhang, Ning Wang, D. Yuan, Guohong Li, Hui Wang, Songlin Feng","doi":"10.1109/ASICON.2013.6811881","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811881","url":null,"abstract":"A CMOS phase-locked loop (PLL) with low reference spur and wide tuning range implemented in 0.18μm CMOS technology is presented in this paper. The design is based on the programmable integer-N PLL structure and the center frequency is around 480MHz for CMOS Image Sensor applications. A pseudo-differential current-starved multi-band ring oscillator is proposed to widen the tuning range. Several circuit techniques are used to minimize the phase frequency detector (PFD) UP/DN timing mismatch and charge pump (CP) current glitches, which reduce the reference spur. Implemented in the 0.18μm CMOS technology, the simulation results show that the -52.6dBc reference spur and the 94.4% tuning range (covering from 30MHz to 1050MHz) can be achieved.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116026965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811898
Baoguang Liu, Yuan Wang, Guangliang Guo, S. Jia, Xing Zhang
A novel dynamic element match (DEM) named Segmented Thermo Data Weighted Average (STDWA) for the Nyquist-rate current-steering digital to analog converter (DAC) has been presented in this paper. In this method, when the input code changes, it only increase or decrease the chosen unit current source in order to reduce the signal glitch. Compared with full random DEM technique, this approach can reach a better static performance. Meanwhile, it can eliminate signal dependent distortions to achieve good linearity at high sampling frequencies as well as other DEM implementations.
{"title":"A novel dynamic element match technique in current-steering DAC","authors":"Baoguang Liu, Yuan Wang, Guangliang Guo, S. Jia, Xing Zhang","doi":"10.1109/ASICON.2013.6811898","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811898","url":null,"abstract":"A novel dynamic element match (DEM) named Segmented Thermo Data Weighted Average (STDWA) for the Nyquist-rate current-steering digital to analog converter (DAC) has been presented in this paper. In this method, when the input code changes, it only increase or decrease the chosen unit current source in order to reduce the signal glitch. Compared with full random DEM technique, this approach can reach a better static performance. Meanwhile, it can eliminate signal dependent distortions to achieve good linearity at high sampling frequencies as well as other DEM implementations.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114871628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812048
Jian Mei, Jixuan Xiang, Huabin Chen, Fan Ye, Junyan Ren
A 4-mW 8-b 600-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is simulated in a standard 65-nm CMOS. By adopting reference capacitive DAC, four-input comparator and the data calibration unit, the proposed ADC could achieve higher speed. As simulated at sampling rate of 600 MS/s, the proposed ADC could achieve a peak SNR of 52.7 dB and maintain ENOB higher than 7.5 bits up to 302-MHz input signal frequency. The FoM of proposed ADC is 34.5 fJ/conversion-step at a 600-MS/s sampling rate and a 1.2-V supply.
在标准65nm CMOS中模拟了一个4 mw 8 b 600 ms /s 2 b/ cycle (2 b/C)逐次逼近寄存器(SAR)模数转换器(ADC)。通过采用基准电容式DAC、四输入比较器和数据校准单元，可以实现更高的速度。在采样率为600 MS/s的情况下，该ADC的峰值信噪比为52.7 dB，在输入频率为302 mhz的情况下，ENOB保持在7.5位以上。该ADC的FoM为34.5 fJ/转换步长，采样率为600 ms /s，电源为1.2 v。
{"title":"A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC","authors":"Jian Mei, Jixuan Xiang, Huabin Chen, Fan Ye, Junyan Ren","doi":"10.1109/ASICON.2013.6812048","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812048","url":null,"abstract":"A 4-mW 8-b 600-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is simulated in a standard 65-nm CMOS. By adopting reference capacitive DAC, four-input comparator and the data calibration unit, the proposed ADC could achieve higher speed. As simulated at sampling rate of 600 MS/s, the proposed ADC could achieve a peak SNR of 52.7 dB and maintain ENOB higher than 7.5 bits up to 302-MHz input signal frequency. The FoM of proposed ADC is 34.5 fJ/conversion-step at a 600-MS/s sampling rate and a 1.2-V supply.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123431397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6811893
You Li, Feng Zhang, Yumei Zhou
The paper presents a small area and low power equalizer for the high-loss serial backplane built in 65 nm CMOS technology. To mitigate the effects of channel loss and other impairments, a programmable continuous time linear equalizer (CTLE) and a programmable 5-tap decision feedback equalizer (DFE) are used in the receiver. In which DFE employs a loop-unrolling structure to meet timing constraints. Furthermore power and area savings are achieved by using two kinds of D-flip-flop (DFF) in proposed DFE and CMOS-style rail-to-rail clocking. The whole equalizer occupies 0.0091 mm2 and consumes 11-mW under a 1.2 V supply when equalizing 6.25 Gb/s data passed over a FR4 PCB channel with 10~28 dB of loss at Nyquist frequency.
{"title":"A novel equalizer for the high-loss backplane at Nyquist frequency","authors":"You Li, Feng Zhang, Yumei Zhou","doi":"10.1109/ASICON.2013.6811893","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6811893","url":null,"abstract":"The paper presents a small area and low power equalizer for the high-loss serial backplane built in 65 nm CMOS technology. To mitigate the effects of channel loss and other impairments, a programmable continuous time linear equalizer (CTLE) and a programmable 5-tap decision feedback equalizer (DFE) are used in the receiver. In which DFE employs a loop-unrolling structure to meet timing constraints. Furthermore power and area savings are achieved by using two kinds of D-flip-flop (DFF) in proposed DFE and CMOS-style rail-to-rail clocking. The whole equalizer occupies 0.0091 mm2 and consumes 11-mW under a 1.2 V supply when equalizing 6.25 Gb/s data passed over a FR4 PCB channel with 10~28 dB of loss at Nyquist frequency.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123254357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/ASICON.2013.6812006
Tianyi Hu
3D video makes it possible for audience to enjoy stereo perception by means of multi-view rendering. Revealing a more realistic and vivid world that conventional 2D video can never achieve, this innovation becomes an important direction of the development of multimedia in the future, thus converting existed 2D video into 3D ones has its great significance. This paper presents a semi-auto 2D-to-3D video conversion method, which segments a video flow into key frames and non-key frames, then utilizes an interactive algorithm as well as an efficient edge detection technique to acquire depth map for a single key frame. Depth map for non-key frame is derived by motion tracking and compensation automatically. The final 3D video flow can be rendered based on the depth map calculated above.
{"title":"A semi-auto interactive 2D-to-3D video conversion technique based on edge detection","authors":"Tianyi Hu","doi":"10.1109/ASICON.2013.6812006","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812006","url":null,"abstract":"3D video makes it possible for audience to enjoy stereo perception by means of multi-view rendering. Revealing a more realistic and vivid world that conventional 2D video can never achieve, this innovation becomes an important direction of the development of multimedia in the future, thus converting existed 2D video into 3D ones has its great significance. This paper presents a semi-auto 2D-to-3D video conversion method, which segments a video flow into key frames and non-key frames, then utilizes an interactive algorithm as well as an efficient edge detection technique to acquire depth map for a single key frame. Depth map for non-key frame is derived by motion tracking and compensation automatically. The final 3D video flow can be rendered based on the depth map calculated above.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123415770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, an integrated development environment (IDE), which is used to map application into a target reconfigurable operators (ReOps) array, is presented. Having as input APU RTL description of an application, the IDE produces the configuration bitstream. The proposed IDE supports a variety of ReOps array through revising the architecture file which including the definition of ReOps, interconnection segments and connection switches, as well as the scale of array and organization of ReOps. A set of benchmarks is given to verify the flow of proposed IDE.
{"title":"An integrated development environment for reconfigurable operators array","authors":"Shan-shan Yong, Xin'an Wang, Ying Cao, Yawei Lu, Zheng Xie","doi":"10.1109/ASICON.2013.6812061","DOIUrl":"https://doi.org/10.1109/ASICON.2013.6812061","url":null,"abstract":"In this paper, an integrated development environment (IDE), which is used to map application into a target reconfigurable operators (ReOps) array, is presented. Having as input APU RTL description of an application, the IDE produces the configuration bitstream. The proposed IDE supports a variety of ReOps array through revising the architecture file which including the definition of ReOps, interconnection segments and connection switches, as well as the scale of array and organization of ReOps. A set of benchmarks is given to verify the flow of proposed IDE.","PeriodicalId":150654,"journal":{"name":"2013 IEEE 10th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128547908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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