Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145957
B. Ray, Matchima Buddhanoy, Mondol Anik Kumar
In this paper we present characterization results of total ionizing dose (TID) effects on commercial 3-D NAND memory. We show the TID induced threshold voltage shift and bit error rate of the memory array. Based on the characterization results we present four system-level techniques that can mitigate TID effects of the commercial 3-D NAND memory.
{"title":"Towards Improving Ionizing Radiation Tolerance of 3-D NAND Flash Memory","authors":"B. Ray, Matchima Buddhanoy, Mondol Anik Kumar","doi":"10.1109/IMW56887.2023.10145957","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145957","url":null,"abstract":"In this paper we present characterization results of total ionizing dose (TID) effects on commercial 3-D NAND memory. We show the TID induced threshold voltage shift and bit error rate of the memory array. Based on the characterization results we present four system-level techniques that can mitigate TID effects of the commercial 3-D NAND memory.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114635852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145991
Siddharth Rao, K. Cai, G. Talmelli, Nathali Franchina-Vergel, Ward Janssens, H. Hody, F. Yasin, K. Wostyn, S. Couet
Spin-orbit torque (SOT) magnetic random-access memory (MRAM) is a 3-terminal non-volatile memory technology promising high speed up to multi-GHz, high endurance and non-volatility. Here we show how SOT-MRAM stack can be optimized to reach performance towards an embedded last level cache memory replacing SRAM. Moreover, we show how the stack and device geometry can be optimized to increase density and how the stack properties can be optimized to perform analog in-memory computing (AiMC) functions using high resistance devices.
{"title":"Spin-orbit torque MRAM for ultrafast cache and neuromorphic computing applications","authors":"Siddharth Rao, K. Cai, G. Talmelli, Nathali Franchina-Vergel, Ward Janssens, H. Hody, F. Yasin, K. Wostyn, S. Couet","doi":"10.1109/IMW56887.2023.10145991","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145991","url":null,"abstract":"Spin-orbit torque (SOT) magnetic random-access memory (MRAM) is a 3-terminal non-volatile memory technology promising high speed up to multi-GHz, high endurance and non-volatility. Here we show how SOT-MRAM stack can be optimized to reach performance towards an embedded last level cache memory replacing SRAM. Moreover, we show how the stack and device geometry can be optimized to increase density and how the stack properties can be optimized to perform analog in-memory computing (AiMC) functions using high resistance devices.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117016592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145947
Tobias Ziegler, Leon Brackmann, T. Hennen, C. Bengel, S. Menzel, D. Wouters
Shifting computations from the central processing unit to the memory is a promising approach to lower the stress on the Von-Neumann bottleneck and to reduce the total energy consumption spend on data transfer. One promising concept for in-memory computations is the associative capacitive network introduced by Kavehei et al.. The digital information is stored in complementary resistive switches which can be read using a non-destructive read out scheme. Simulation results based on the JART VCM vlb model demonstrate the working principle of the original input encoding and the existence of capacitive sneak path currents is identified. A new input encoding is proposed in this work which not only prevents capacitive sneak paths but also improves the voltage difference between Hamming Distances (HD).
{"title":"Eliminating Capacitive Sneak Paths in Associative Capacitive Networks based on Complementary Resistive Switches for In-Memory Computing","authors":"Tobias Ziegler, Leon Brackmann, T. Hennen, C. Bengel, S. Menzel, D. Wouters","doi":"10.1109/IMW56887.2023.10145947","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145947","url":null,"abstract":"Shifting computations from the central processing unit to the memory is a promising approach to lower the stress on the Von-Neumann bottleneck and to reduce the total energy consumption spend on data transfer. One promising concept for in-memory computations is the associative capacitive network introduced by Kavehei et al.. The digital information is stored in complementary resistive switches which can be read using a non-destructive read out scheme. Simulation results based on the JART VCM vlb model demonstrate the working principle of the original input encoding and the existence of capacitive sneak path currents is identified. A new input encoding is proposed in this work which not only prevents capacitive sneak paths but also improves the voltage difference between Hamming Distances (HD).","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129258264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145980
N. Shibata, H. Uchikawa, Taira Shibuya, Kenri Nakai, K. Yanagidaira, H. Inoue
In this work, a 3. 5bit/cell (X3.5) flash memory is introduced to achieve a lower giga-byte cost with high reliability and performance. Accordingly, 7-bit data are stored in two memory cells with 12-level Vth distributions. The X3.5 Programming method does not require the complex approach used in QLC and can easily be handled by NAND controller. QLC needs a more powerful ECC than TLC; hence, increasing the size of the ECC parity for QLC enlarges the die size. However, the same ECC parity size as TLC can be applicable to X3.5. An X3.5 die size with a TLC ECC is only 6.3% bigger than QLC. By contrast, X3.5 Program performance is 2.3 times faster than QLC with the QLC reliability criteria, which is relaxed from the TLC reliability criteria. If the size of the ECC parity is reduced to that of 32nmMLC, X3.5 die size will be close to that of QLC, while X3.5 Program performance will be 1.6 times faster than that of QLC. Moreover, X3.5 will meet the TLC reliability criteria. In addition to expanding X3.5 technologies, 4.5 bit/cell (X4.5) with a 24-level Vth distributions is also possible, which is suitable for cold storage applications.
{"title":"7-Bit/2Cell (X3.5), 9-Bit/2Cell (X4.5) NAND Flash Memory: Half Bit technology","authors":"N. Shibata, H. Uchikawa, Taira Shibuya, Kenri Nakai, K. Yanagidaira, H. Inoue","doi":"10.1109/IMW56887.2023.10145980","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145980","url":null,"abstract":"In this work, a 3. 5bit/cell (X3.5) flash memory is introduced to achieve a lower giga-byte cost with high reliability and performance. Accordingly, 7-bit data are stored in two memory cells with 12-level Vth distributions. The X3.5 Programming method does not require the complex approach used in QLC and can easily be handled by NAND controller. QLC needs a more powerful ECC than TLC; hence, increasing the size of the ECC parity for QLC enlarges the die size. However, the same ECC parity size as TLC can be applicable to X3.5. An X3.5 die size with a TLC ECC is only 6.3% bigger than QLC. By contrast, X3.5 Program performance is 2.3 times faster than QLC with the QLC reliability criteria, which is relaxed from the TLC reliability criteria. If the size of the ECC parity is reduced to that of 32nmMLC, X3.5 die size will be close to that of QLC, while X3.5 Program performance will be 1.6 times faster than that of QLC. Moreover, X3.5 will meet the TLC reliability criteria. In addition to expanding X3.5 technologies, 4.5 bit/cell (X4.5) with a 24-level Vth distributions is also possible, which is suitable for cold storage applications.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115018840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145976
Zhijun Chen, Fred Fishburn, Chang Seok Kang, Sony Varghese, Bala Haran
Both DRAM and NAND evolution over the last decade have come less and less from cell design changes and more from material changes to address higher aspect ratios with reduced feature size variation. We review key processes that have enabled density shrink for both core memory array and the peri transistor. The current shortcomings in scaling DRAM are highlighted and we outline new architectures powered by novel materials and process that overcome these.
{"title":"Materials Enabled Memory Scaling and New Architectures","authors":"Zhijun Chen, Fred Fishburn, Chang Seok Kang, Sony Varghese, Bala Haran","doi":"10.1109/IMW56887.2023.10145976","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145976","url":null,"abstract":"Both DRAM and NAND evolution over the last decade have come less and less from cell design changes and more from material changes to address higher aspect ratios with reduced feature size variation. We review key processes that have enabled density shrink for both core memory array and the peri transistor. The current shortcomings in scaling DRAM are highlighted and we outline new architectures powered by novel materials and process that overcome these.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132832446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145930
Zhuo Chen, N. Ronchi, A. Walke, K. Banerjee, M. Popovici, K. Katcko, G. V. D. Bosch, M. Rosmeulen, V. Afanas’ev, J. V. Houdt
We fabricated and characterized IGZO-channel back-gated FeFET. It has been found that a Memory Window (MW) reading scheme based on reverse $I_{d}-V_{g}$ sweep can strongly attenuate the significant read disturb which affects the low- Vt state. This instability of low- $mathrm{V}_{mathrm{t}}$ state origins from the asymmetric PV loop and small negative coercive voltage. With this optimized reading scheme, we proved that interfacial engineering, by inserting a $mathrm{NbO}_{mathrm{x}}$ layer between La HZO and IGZO, can significantly improve $2 P_{r}$, MW (to $0.7 mathrm{~V}$), and endurance (to 107 cycles). This makes the $mathrm{La}: mathrm{HZO} / mathrm{NbO}_{mathrm{x}} / mathrm{IGZO}$ FeFET a promising structure for high-endurance and low-latency NVM.
{"title":"Improved MW of IGZO-channel FeFET by Reading Scheme Optimization and Interfacial Engineering","authors":"Zhuo Chen, N. Ronchi, A. Walke, K. Banerjee, M. Popovici, K. Katcko, G. V. D. Bosch, M. Rosmeulen, V. Afanas’ev, J. V. Houdt","doi":"10.1109/IMW56887.2023.10145930","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145930","url":null,"abstract":"We fabricated and characterized IGZO-channel back-gated FeFET. It has been found that a Memory Window (MW) reading scheme based on reverse $I_{d}-V_{g}$ sweep can strongly attenuate the significant read disturb which affects the low- Vt state. This instability of low- $mathrm{V}_{mathrm{t}}$ state origins from the asymmetric PV loop and small negative coercive voltage. With this optimized reading scheme, we proved that interfacial engineering, by inserting a $mathrm{NbO}_{mathrm{x}}$ layer between La HZO and IGZO, can significantly improve $2 P_{r}$, MW (to $0.7 mathrm{~V}$), and endurance (to 107 cycles). This makes the $mathrm{La}: mathrm{HZO} / mathrm{NbO}_{mathrm{x}} / mathrm{IGZO}$ FeFET a promising structure for high-endurance and low-latency NVM.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126463276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145983
A. Conte, Francesco Tomaiuolo, Marco Ruta, A. Redaelli, F. Arnaud, T. Jouanneau, C. Boccaccio, O. Weber
In this paper, the competitive advantage of Phase Change Memory (PCM) with BJT selector in 18nm FDSOI technology is explained. Starting from Microcontrollers requirements and architectures, the impact of technology features and device flavor in high performance and low-cost Microcontrollers is analyzed in section I, while the peculiarities of ePCM cell with BJT selector and its high-density advantages vs other NVM Back End solutions are illustrated in section II. The ePCM NVM IP Architecture constraints are presented in section III with particular emphasis on the need to split the arrays in Tiles. In section IV the impact of BJT selector in Reading Architecture is discussed showing the limits of classical solution and introducing a reading technique using multiple voltage domains sensing for Low Power Micros. Experimental results on a dedicated Test Vehicle are illustrated in section V.
{"title":"An 18nm ePCM with BJT selector NVM design for advanced microcontroller applications","authors":"A. Conte, Francesco Tomaiuolo, Marco Ruta, A. Redaelli, F. Arnaud, T. Jouanneau, C. Boccaccio, O. Weber","doi":"10.1109/IMW56887.2023.10145983","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145983","url":null,"abstract":"In this paper, the competitive advantage of Phase Change Memory (PCM) with BJT selector in 18nm FDSOI technology is explained. Starting from Microcontrollers requirements and architectures, the impact of technology features and device flavor in high performance and low-cost Microcontrollers is analyzed in section I, while the peculiarities of ePCM cell with BJT selector and its high-density advantages vs other NVM Back End solutions are illustrated in section II. The ePCM NVM IP Architecture constraints are presented in section III with particular emphasis on the need to split the arrays in Tiles. In section IV the impact of BJT selector in Reading Architecture is discussed showing the limits of classical solution and introducing a reading technique using multiple voltage domains sensing for Low Power Micros. Experimental results on a dedicated Test Vehicle are illustrated in section V.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124041335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145982
Takuto Nishimura, Yuya Ichikawa, Akira Goda, Naoko Misawa, C. Matsui, Ken Takeuchi
A Stochastic Computing-based Computation-inMemory architecture (SC CiM) with non-volatile memory (NVM) stochastic weights has been proposed. Both of the input and weight values are converted into stochastic bit streams. The multiply-and-accumulate (MAC) operation of the SC multiplication is performed in memory. The computational accuracy is characterized for Resnet-56 and CIFAR-10, with the bit error rate (BER) range from 1$0^{-4}$ to 1$0^{-2}$ representing the actual NVM characteristics. The effects of NVM BER are analyzed hierarchically at all computational layers (bit streams, MAC calculation and DNN inference) and compared both qualitatively and quantitatively with the conventional CiM. The results show the excellent robustness of the proposed SC CiM architecture in the wide range of BER. The tolerance to the manufacturing defects is even better than that of the conventional CiM. Furthermore, the desired weight distributions are discussed by exploiting the unique behaviors against NVM BER in the SC CiM.
{"title":"Stochastic Computing-based Computation-in-Memory (SC CiM) Architecture for DNNs and Hierarchical Evaluations of Non-volatile Memory Error and Defect Tolerance","authors":"Takuto Nishimura, Yuya Ichikawa, Akira Goda, Naoko Misawa, C. Matsui, Ken Takeuchi","doi":"10.1109/IMW56887.2023.10145982","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145982","url":null,"abstract":"A Stochastic Computing-based Computation-inMemory architecture (SC CiM) with non-volatile memory (NVM) stochastic weights has been proposed. Both of the input and weight values are converted into stochastic bit streams. The multiply-and-accumulate (MAC) operation of the SC multiplication is performed in memory. The computational accuracy is characterized for Resnet-56 and CIFAR-10, with the bit error rate (BER) range from 1$0^{-4}$ to 1$0^{-2}$ representing the actual NVM characteristics. The effects of NVM BER are analyzed hierarchically at all computational layers (bit streams, MAC calculation and DNN inference) and compared both qualitatively and quantitatively with the conventional CiM. The results show the excellent robustness of the proposed SC CiM architecture in the wide range of BER. The tolerance to the manufacturing defects is even better than that of the conventional CiM. Furthermore, the desired weight distributions are discussed by exploiting the unique behaviors against NVM BER in the SC CiM.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128034778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145931
Meng Huang, Shufang Si, Zheng He, Ying Zhou, Sijia Li, Hong Wang, Jinying Liu, Dongsheng Xie, Mengmeng Yang, K. You, Chris Choi, Yi Tang, Xiaojie Li, Shibing Qian, Xiaodong Yang, Long Hou, Weiping Bai, Zhongming Liu, Yanzhe Tang, Qiong Wu, Yanqin Wang, Tao Dou, Jake Kim, Guilei Wang, Jie Baisp, Adachi Takao, Chao Zhao, A. Yoo
Continuous shrinking of dynamic random access memory $langle$DRAM) feature size will inevitably hit unsurmountable barriers, such as sub-10 nm patterning issues, ultra-high aspect ratio (HAR) capacitor and narrow sensing margin, etc. One candidate of promising solutions is the innovation in architecture with three-dimensional (3D) horizontally stacked transistors with capacitors, similar with a 3D NAND-like architecture. However, the process integration scheme and circuit simulation on the 3D Stackable DRAM architecture have been barely reported. In this paper, we systematically introduced a 3D DRAM architecture, integration scheme for the first time. Then we further performed circuit simulation studies on the 3D DRAM, which in return confirm the feasibility of our proposed architecture and show great prospect in DRAM core timing optimization.
动态随机存取存储器（DRAM）特征尺寸的不断缩小不可避免地会遇到难以逾越的障碍，例如 10 纳米以下的图案化问题、超高纵横比（HAR）电容器和狭窄的传感裕度等。一个有前景的解决方案是采用三维（3D）水平堆叠晶体管和电容器的创新架构，类似于三维 NAND 架构。然而，有关三维可堆叠 DRAM 架构的工艺集成方案和电路仿真却鲜有报道。在本文中，我们首次系统地介绍了 3D DRAM 架构和集成方案。随后，我们进一步对 3D DRAM 进行了电路仿真研究，结果证实了我们提出的架构的可行性，并展示了在 DRAM 内核时序优化方面的巨大前景。
{"title":"A 3D Stackable 1T1C DRAM: Architecture, Process Integration and Circuit Simulation","authors":"Meng Huang, Shufang Si, Zheng He, Ying Zhou, Sijia Li, Hong Wang, Jinying Liu, Dongsheng Xie, Mengmeng Yang, K. You, Chris Choi, Yi Tang, Xiaojie Li, Shibing Qian, Xiaodong Yang, Long Hou, Weiping Bai, Zhongming Liu, Yanzhe Tang, Qiong Wu, Yanqin Wang, Tao Dou, Jake Kim, Guilei Wang, Jie Baisp, Adachi Takao, Chao Zhao, A. Yoo","doi":"10.1109/IMW56887.2023.10145931","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145931","url":null,"abstract":"Continuous shrinking of dynamic random access memory $langle$DRAM) feature size will inevitably hit unsurmountable barriers, such as sub-10 nm patterning issues, ultra-high aspect ratio (HAR) capacitor and narrow sensing margin, etc. One candidate of promising solutions is the innovation in architecture with three-dimensional (3D) horizontally stacked transistors with capacitors, similar with a 3D NAND-like architecture. However, the process integration scheme and circuit simulation on the 3D Stackable DRAM architecture have been barely reported. In this paper, we systematically introduced a 3D DRAM architecture, integration scheme for the first time. Then we further performed circuit simulation studies on the 3D DRAM, which in return confirm the feasibility of our proposed architecture and show great prospect in DRAM core timing optimization.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128387838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145986
L. Breuil, M. Popovici, J. Stiers, A. Arreghini, S. Ramesh, G. V. D. Bosch, J. V. Houdt, M. Rosmeulen
In this paper, we optimize the retention in gate stacks including ferroelectric materials for program / erase boosting. The improved program performance by exploiting ferroelectricity in a material used for charge storage medium has been confirmed. However, the retention properties of such materials still need to be improved. As an alternative, we propose a dual charge trapping layer made of thin Si3N4 / ferroelectric high-K material that can keep the retention to the level of a conventional ONO gate stack, while benefiting from the boosting effect. For application as blocking oxide, the improvement in program / erase due to capacitance boosting could also be observed, but the use of a thick high-K material at this position causes retention issues that are difficult to solve. Alternatively, placing a thin high-K below a SiO2 blocking layer can improve programming without penalty in retention. This calls for developing ultra-thin high-K materials with ferroelectric properties for further improvement.
{"title":"Optimization of Retention in Ferroelectricity Boosted Gate Stacks for 3D NAND","authors":"L. Breuil, M. Popovici, J. Stiers, A. Arreghini, S. Ramesh, G. V. D. Bosch, J. V. Houdt, M. Rosmeulen","doi":"10.1109/IMW56887.2023.10145986","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145986","url":null,"abstract":"In this paper, we optimize the retention in gate stacks including ferroelectric materials for program / erase boosting. The improved program performance by exploiting ferroelectricity in a material used for charge storage medium has been confirmed. However, the retention properties of such materials still need to be improved. As an alternative, we propose a dual charge trapping layer made of thin Si3N4 / ferroelectric high-K material that can keep the retention to the level of a conventional ONO gate stack, while benefiting from the boosting effect. For application as blocking oxide, the improvement in program / erase due to capacitance boosting could also be observed, but the use of a thick high-K material at this position causes retention issues that are difficult to solve. Alternatively, placing a thin high-K below a SiO2 blocking layer can improve programming without penalty in retention. This calls for developing ultra-thin high-K materials with ferroelectric properties for further improvement.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124354908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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