Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145949
N. Lepri, P. Gibertini, P. Mannocci, A. Pirovano, I. Tortorelli, P. Fantini, D. Ielmini
In-memory computing (IMC) shows a disruptive potential for accelerating artificial intelligence (AI) in both inference and training tasks. Scalable IMC, however, requires novel memory technologies with extremely low current. Here we demonstrate ultra-low current matrix-vector multiplication (MVM) in a crosspoint array of phase change memory (PCM) and ovonic threshold switch (OTS) with one-selector/one-resistor (181R) structure operated in the subthreshold regime. Thanks to highly-uniform sub-$mu$A currents, the 181R PCM crosspoint array rejects parasitic IR drop across wires, enabling excellent scaling compared to other memory devices. Our simulation of a fullyconnected neural network (FCNN) with ternary weights indicates an accuracy of 98% for MNIST classification with an array size of 512x512, which strongly supports subthreshold-operated 181R crosspoint arrays for neural network inference accelerators.
{"title":"In-memory neural network accelerator based on phase change memory (PCM) with one-selector/one-resistor (1S1R) structure operated in the subthreshold regime","authors":"N. Lepri, P. Gibertini, P. Mannocci, A. Pirovano, I. Tortorelli, P. Fantini, D. Ielmini","doi":"10.1109/IMW56887.2023.10145949","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145949","url":null,"abstract":"In-memory computing (IMC) shows a disruptive potential for accelerating artificial intelligence (AI) in both inference and training tasks. Scalable IMC, however, requires novel memory technologies with extremely low current. Here we demonstrate ultra-low current matrix-vector multiplication (MVM) in a crosspoint array of phase change memory (PCM) and ovonic threshold switch (OTS) with one-selector/one-resistor (181R) structure operated in the subthreshold regime. Thanks to highly-uniform sub-$mu$A currents, the 181R PCM crosspoint array rejects parasitic IR drop across wires, enabling excellent scaling compared to other memory devices. Our simulation of a fullyconnected neural network (FCNN) with ternary weights indicates an accuracy of 98% for MNIST classification with an array size of 512x512, which strongly supports subthreshold-operated 181R crosspoint arrays for neural network inference accelerators.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122350721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145972
J. Laguerre, M. Bocquet, O. Billoint, S. Martin, J. Coignus, C. Carabasse, T. Magis, T. Dewolf, F. Andrieu, L. Grenouillet
The Memory Window (MW) of BEOL-integrated Si:HfO2-based 16kbit ITIC FeRAM arrays is shown to be significantly improved (×3) by etching the ferroelectric (FE) film of the Ferroelectric CAPacitor (FeCAP). To estimate the MW evolution in larger arrays at advanced technology nodes, a Preisach current-based compact model is developed, calibrated on measured FeCAP electrical characteristics and validated at various operating voltages. Electrical simulations of an elementary ITIC 16kbit FeRAM array-like structure using Siemens Eldo show that scaling the transistor (1T) at advanced technology nodes can be beneficial for the MW. FE film thickness reduction below 10nm will also be requested for low voltage applications.
{"title":"Memory Window in Si:HfO2 FeRAM arrays: Performance Improvement and Extrapolation at Advanced Nodes","authors":"J. Laguerre, M. Bocquet, O. Billoint, S. Martin, J. Coignus, C. Carabasse, T. Magis, T. Dewolf, F. Andrieu, L. Grenouillet","doi":"10.1109/IMW56887.2023.10145972","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145972","url":null,"abstract":"The Memory Window (MW) of BEOL-integrated Si:HfO2-based 16kbit ITIC FeRAM arrays is shown to be significantly improved (×3) by etching the ferroelectric (FE) film of the Ferroelectric CAPacitor (FeCAP). To estimate the MW evolution in larger arrays at advanced technology nodes, a Preisach current-based compact model is developed, calibrated on measured FeCAP electrical characteristics and validated at various operating voltages. Electrical simulations of an elementary ITIC 16kbit FeRAM array-like structure using Siemens Eldo show that scaling the transistor (1T) at advanced technology nodes can be beneficial for the MW. FE film thickness reduction below 10nm will also be requested for low voltage applications.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115233467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145977
Daohuan Feng, Yi Jiang, Yunsong Qiu, Yuhong Zheng, Harry Kim, Jaewoo Kim, Jian Chu, Guangsu Shao, Yucheng Liao, Cheng-Jer Yang, Minrui Hu, Wenli Zhao, Linjiang Xia, Jianfeng Xiao, Di Ma, Yuan Cheng, Xiangbo Kong, Chao Lin, Tianming Li, Yongjie Li, Jingheng Meng, K. Shao, Yan Wang, Xiaoan Yang, Xiang Liu, Qinghua Han, Huiming Li, Yanzhe Tang, Mingde Liu, Eric Wu, Xiaopeng Li, Renrui Huang, Mingtang Zhang, Long Hou, Xuan Pan, Xinwen Jin, Shuiping Zhao, D. Han, Ted C. Park, Deyuan Xiao, Chao Zhao, A. Yoo
In this work, a novel 4F2 VCT (vertical channel transistor) targeting for next generation of DRAM is proposed. We approached process feasibility and device performance of $mathbf{4 F}^{2}$ VCT by TCAD simulation. Detailed processes such as BL (bit line) and WL (word line) loop have also been discussed to achieve lx node VCT DRAM. For the first time, silicon demonstration for $8mathrm{~Gb}$ full array VCT with density as high as $198 mathrm{Mbit}/mathrm{mm}^{2}$ is successfully realized. Besides, we also demonstrated standard switching behavior of VCT access transistor with reasonable device performance.
{"title":"Vertical Channel Transistor (VCT) as Access Transistor for Future 4F2 DRAM Architecture","authors":"Daohuan Feng, Yi Jiang, Yunsong Qiu, Yuhong Zheng, Harry Kim, Jaewoo Kim, Jian Chu, Guangsu Shao, Yucheng Liao, Cheng-Jer Yang, Minrui Hu, Wenli Zhao, Linjiang Xia, Jianfeng Xiao, Di Ma, Yuan Cheng, Xiangbo Kong, Chao Lin, Tianming Li, Yongjie Li, Jingheng Meng, K. Shao, Yan Wang, Xiaoan Yang, Xiang Liu, Qinghua Han, Huiming Li, Yanzhe Tang, Mingde Liu, Eric Wu, Xiaopeng Li, Renrui Huang, Mingtang Zhang, Long Hou, Xuan Pan, Xinwen Jin, Shuiping Zhao, D. Han, Ted C. Park, Deyuan Xiao, Chao Zhao, A. Yoo","doi":"10.1109/IMW56887.2023.10145977","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145977","url":null,"abstract":"In this work, a novel 4F2 VCT (vertical channel transistor) targeting for next generation of DRAM is proposed. We approached process feasibility and device performance of $mathbf{4 F}^{2}$ VCT by TCAD simulation. Detailed processes such as BL (bit line) and WL (word line) loop have also been discussed to achieve lx node VCT DRAM. For the first time, silicon demonstration for $8mathrm{~Gb}$ full array VCT with density as high as $198 mathrm{Mbit}/mathrm{mm}^{2}$ is successfully realized. Besides, we also demonstrated standard switching behavior of VCT access transistor with reasonable device performance.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126637414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145969
G. Nicosia, Niccolò Righetti, Yingda Dong
In this work, we present the first electrical characterization and modeling of the impact on long-term data retention of distributed cycling in charge trap (CT) 3D NAND arrays. Dependence on Program/Erase cycling conditions of trapassisted tunneling (TAT), charge detrapping, and lateral charge migration (LCM) are experimentally evaluated and modeled. It is demonstrated that post-cycling TAT degradation depends only on the overall cycling dose and not on cycling temperature nor on the delays in-between each Program/Erase operation. On the other hand, charge detrapping follows the same time and temperature dynamics as the ones observed in floating-gate NAND arrays. Finally, LCM is observed to improve with increasing cycling dose and cycling temperature but to be negligibly dependent on the cycling duration. Results are a cornerstone in designing accelerated cycling tests for CT 3D NAND arrays qualification.
在这项工作中，我们首次提出了电荷阱(CT) 3D NAND阵列中分布式循环对长期数据保留影响的电学表征和建模。对陷阱辅助隧道(TAT)、电荷脱陷和侧向电荷迁移(LCM)的依赖程序/擦除循环条件进行了实验评估和建模。结果表明，循环后的TAT降解仅取决于总循环剂量，而不取决于循环温度，也不取决于每次Program/Erase操作之间的延迟。另一方面，电荷脱陷遵循与在浮动门NAND阵列中观察到的相同的时间和温度动力学。最后，观察到LCM随循环剂量和循环温度的增加而改善，但与循环时间的相关性可以忽略不计。结果是设计CT 3D NAND阵列认证加速循环测试的基石。
{"title":"Distributed Cycling in Charge Trap-Based 3D NAND Arrays: Model and Qualification Tests Implications","authors":"G. Nicosia, Niccolò Righetti, Yingda Dong","doi":"10.1109/IMW56887.2023.10145969","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145969","url":null,"abstract":"In this work, we present the first electrical characterization and modeling of the impact on long-term data retention of distributed cycling in charge trap (CT) 3D NAND arrays. Dependence on Program/Erase cycling conditions of trapassisted tunneling (TAT), charge detrapping, and lateral charge migration (LCM) are experimentally evaluated and modeled. It is demonstrated that post-cycling TAT degradation depends only on the overall cycling dose and not on cycling temperature nor on the delays in-between each Program/Erase operation. On the other hand, charge detrapping follows the same time and temperature dynamics as the ones observed in floating-gate NAND arrays. Finally, LCM is observed to improve with increasing cycling dose and cycling temperature but to be negligibly dependent on the cycling duration. Results are a cornerstone in designing accelerated cycling tests for CT 3D NAND arrays qualification.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128386746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145950
V. Markov, G. Festes, L. Schneider, S. Lemke, S. Jourba, A. Kotov
The impact of high-temperature (HT) bake on random telegraph noise (RTN) statistics in floating gate (FG) flash memory arrays was studied. It was found that HT bake of the memory array set in erase state can effectively suppress RTN previously induced by HT bake of the memory array set in program state. Since program and erase states are characterized by negatively and positively charged FG respectively, the FG potential plays a crucial role in the direction of the RTN intensification or alleviation. The effect of HT bake on RTN was extensively analyzed as a function of the FG potential, bake temperature, and bake duration. By alternating HT bakes of the memory arrays in program and erase states, we observed a reversible switching of the RTN traps between active and inactive modes. This behavior suggests that the RTN traps in our biastemperature stress experiments were not newly generated but rather originated ones from the pre-existed defect precursors in FG oxide.
{"title":"Effect of High-Temperature Bake on RTN Statistics in Floating Gate Flash Memory Arrays","authors":"V. Markov, G. Festes, L. Schneider, S. Lemke, S. Jourba, A. Kotov","doi":"10.1109/IMW56887.2023.10145950","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145950","url":null,"abstract":"The impact of high-temperature (HT) bake on random telegraph noise (RTN) statistics in floating gate (FG) flash memory arrays was studied. It was found that HT bake of the memory array set in erase state can effectively suppress RTN previously induced by HT bake of the memory array set in program state. Since program and erase states are characterized by negatively and positively charged FG respectively, the FG potential plays a crucial role in the direction of the RTN intensification or alleviation. The effect of HT bake on RTN was extensively analyzed as a function of the FG potential, bake temperature, and bake duration. By alternating HT bakes of the memory arrays in program and erase states, we observed a reversible switching of the RTN traps between active and inactive modes. This behavior suggests that the RTN traps in our biastemperature stress experiments were not newly generated but rather originated ones from the pre-existed defect precursors in FG oxide.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116634378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145823
Wei-Chen Chen, H. Lue, T. Hsu, Keh-Chung Wang, Chih-Yuan Lu
Planar 1T1C DRAM has encountered numerous challenges as it reaches beyond $1 mathrm{z}-mathrm{nm}$ node. The daunting task of manufacturing a low-leakage access transistor and high aspectratio capacitor necessitates a disruptive technology to continue the relentless scaling path similar to the migration of $2 D$ to $3 D$ NAND. In this work, we will touch up on the scaling difficulties associated with 2D 1T1C DRAM and then examine the possible options of 3D DRAM, including flipped 1T1C DRAM, 2T0C gain-cell DRAM, and 3D stackable gate-controlled-thyristor (GCT) DRAM. We will show that the capacitor-less GCT DRAM, which shares the architectural features of CMOS nanosheet and 3D NAND, possesses good potential of realizing a truly 3D stackable structure. Furthermore, the scaling capability toward $10 mathrm{~nm}$ of such GCT device is verified by TCAD simulation when the channel length and width are downscaled simultaneously. Meanwhile, the gate oxide thickness thinning is unnecessary because the thyristor operation principles are different from the MOSFET. The simulated $mathrm{Lch} / mathrm{Wch}=10 mathrm{~nm}$ GCT device can well preserve $gt 2 mathrm{~V}$ hysteresis memory window, large read current ON/OFF ratio of $gt 1 E 8$, and $110 mu mathrm{A}$ sensing current window, paving a way for aggressive $X / Y$ pitch scaling for the $3 D$ stackable DRAM device.
{"title":"A Simulation Study of Scaling Capability toward 10nm for the 3D Stackable Gate-Controlled Thyristor (GCT) DRAM Device","authors":"Wei-Chen Chen, H. Lue, T. Hsu, Keh-Chung Wang, Chih-Yuan Lu","doi":"10.1109/IMW56887.2023.10145823","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145823","url":null,"abstract":"Planar 1T1C DRAM has encountered numerous challenges as it reaches beyond $1 mathrm{z}-mathrm{nm}$ node. The daunting task of manufacturing a low-leakage access transistor and high aspectratio capacitor necessitates a disruptive technology to continue the relentless scaling path similar to the migration of $2 D$ to $3 D$ NAND. In this work, we will touch up on the scaling difficulties associated with 2D 1T1C DRAM and then examine the possible options of 3D DRAM, including flipped 1T1C DRAM, 2T0C gain-cell DRAM, and 3D stackable gate-controlled-thyristor (GCT) DRAM. We will show that the capacitor-less GCT DRAM, which shares the architectural features of CMOS nanosheet and 3D NAND, possesses good potential of realizing a truly 3D stackable structure. Furthermore, the scaling capability toward $10 mathrm{~nm}$ of such GCT device is verified by TCAD simulation when the channel length and width are downscaled simultaneously. Meanwhile, the gate oxide thickness thinning is unnecessary because the thyristor operation principles are different from the MOSFET. The simulated $mathrm{Lch} / mathrm{Wch}=10 mathrm{~nm}$ GCT device can well preserve $gt 2 mathrm{~V}$ hysteresis memory window, large read current ON/OFF ratio of $gt 1 E 8$, and $110 mu mathrm{A}$ sensing current window, paving a way for aggressive $X / Y$ pitch scaling for the $3 D$ stackable DRAM device.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124791963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145993
V. Parmar, Sandeep Kaur Kingra, Deepak Verma, Digamber Pandey, G. Piccolboni, A. Bricalli, A. Regev, G. Pares, L. Grenouillet, J. Nodin, M. Suri
We demonstrate 16kB RRAM PUF (Physically Un-clonable Function) arrays with excellent immunity to hightemperature SMT (surface mount technology) -reflow process and resilience against modern Machine-Learning (ML) based sidechannel attacks (SCA). Robust PUF operation is experimentally demonstrated on two optimized 2T-2R CMOS-RRAM designs (28 nm and 130 nm). We exploit forming voltage variability coupled with a dedicated novel programming scheme to extract unique PUF signatures. Fabricated arrays exhibit excellent performance in terms of speed, data retention and memory window. Extracted PUF signatures satisfy NIST (800-90B) tests showing extremely narrow distribution for hamming weight across multiple dies. Resilience against modern ML-SCA is achieved by introducing a secondary low energy HRS (high-resistance state) programming step and RRAM device stack-engineering. Proposed work is one of the first demonstrations for SMT-reflow immunity in context of PUF designs highlighting the high tolerance of the PUF signature to temperatures as high as 200 °C.
{"title":"Demonstration of SMT-reflow Immune and SCA-resilient PUF on 28nm RRAM device array","authors":"V. Parmar, Sandeep Kaur Kingra, Deepak Verma, Digamber Pandey, G. Piccolboni, A. Bricalli, A. Regev, G. Pares, L. Grenouillet, J. Nodin, M. Suri","doi":"10.1109/IMW56887.2023.10145993","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145993","url":null,"abstract":"We demonstrate 16kB RRAM PUF (Physically Un-clonable Function) arrays with excellent immunity to hightemperature SMT (surface mount technology) -reflow process and resilience against modern Machine-Learning (ML) based sidechannel attacks (SCA). Robust PUF operation is experimentally demonstrated on two optimized 2T-2R CMOS-RRAM designs (28 nm and 130 nm). We exploit forming voltage variability coupled with a dedicated novel programming scheme to extract unique PUF signatures. Fabricated arrays exhibit excellent performance in terms of speed, data retention and memory window. Extracted PUF signatures satisfy NIST (800-90B) tests showing extremely narrow distribution for hamming weight across multiple dies. Resilience against modern ML-SCA is achieved by introducing a secondary low energy HRS (high-resistance state) programming step and RRAM device stack-engineering. Proposed work is one of the first demonstrations for SMT-reflow immunity in context of PUF designs highlighting the high tolerance of the PUF signature to temperatures as high as 200 °C.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125262810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145984
B. Giraud, S. Ricavy, Yasser Moursy, C. Laffond, I. Sever, V. Gherman, M. Pezzin, F. Lepin, M. Diallo, K. Zenati, S. Dumas, M. Vershkov, A. Bricalli, G. Piccolboni, J. Noël, A. Samir, G. Pillonnet, Y. Thonnart, G. Molas
This paper presents different design assist techniques and demonstrates their impact on enhancing the intrinsic RRAM performance. We show that the read-beforewrite, current-limitation and write-termination techniques reduce by -47%, -56% and-13% the power consumption during the writing process, respectively. Combined with write verification and error correction code, the overall improvements are 87% in energy saving and -55% on access time. Based on representative RRAM macro (130nm CMOS), statistic (128kb) and endurance (1M cycles) characterizations, this works contributes to accelerate RRAM industrial adoption by highlighting the design-technology co-optimization contribution.
{"title":"Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro","authors":"B. Giraud, S. Ricavy, Yasser Moursy, C. Laffond, I. Sever, V. Gherman, M. Pezzin, F. Lepin, M. Diallo, K. Zenati, S. Dumas, M. Vershkov, A. Bricalli, G. Piccolboni, J. Noël, A. Samir, G. Pillonnet, Y. Thonnart, G. Molas","doi":"10.1109/IMW56887.2023.10145984","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145984","url":null,"abstract":"This paper presents different design assist techniques and demonstrates their impact on enhancing the intrinsic RRAM performance. We show that the read-beforewrite, current-limitation and write-termination techniques reduce by -47%, -56% and-13% the power consumption during the writing process, respectively. Combined with write verification and error correction code, the overall improvements are 87% in energy saving and -55% on access time. Based on representative RRAM macro (130nm CMOS), statistic (128kb) and endurance (1M cycles) characterizations, this works contributes to accelerate RRAM industrial adoption by highlighting the design-technology co-optimization contribution.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115898415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145953
P. Subrahmanyan, Wonjae Lee, Jeffrey D Lischer, Ram Karur, Olga Kucher, S. Todorov, A. Osonkie
In a continuous effort to reduce bit cost, industry has been scaling in the Z direction thus leading to high aspect ratio (HAR) devices. This has been prevalent in the 3DNAND device segment and is forecast to extend to the DRAM device segment with 3DDRAM architectures. The growth in the Z direction has led to the deposition of stacks of multi-layer thin films followed by patterning and etching of HAR features. Etching these HAR features requires the development of hard masks with excellent selectivity to the underlying stack. However, such high selectivity hard masks invariably impart a high level of stress to the wafer. With subsequent etching and patterning of these wafers, the stress is relieved selectively and can lead to either global or local isotropic and anisotropic behavior of the wafer strain. This strain manifests itself as an Out of Plane Distortion (OPD) and is accompanied by an In Plane Distortion (IPD). This resulting IPD affects the overlay of the patterning layers and affects yield, especially at the edge of the wafer. Industry has been using backside-deposited films to control global wafer warp but has not found a way to actively control local stresses that lead to IPD related alignment and overlay error. A novel approach to compensate for both the global and local stress induced IPD by co-optimizing the deposition of a backside stress compensation layer and ion implantation into this layer by scanning a Gaussian profiled ion beam over it is presented in this paper. This can potentially reduce burden at the wafer alignment correction in the lithography steps. In addition, this can also reduce the number of alignment points and enable low order wafer alignment schemes that meet the target overlay error specifications.
{"title":"Overlay Control in HAR device integration","authors":"P. Subrahmanyan, Wonjae Lee, Jeffrey D Lischer, Ram Karur, Olga Kucher, S. Todorov, A. Osonkie","doi":"10.1109/IMW56887.2023.10145953","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145953","url":null,"abstract":"In a continuous effort to reduce bit cost, industry has been scaling in the Z direction thus leading to high aspect ratio (HAR) devices. This has been prevalent in the 3DNAND device segment and is forecast to extend to the DRAM device segment with 3DDRAM architectures. The growth in the Z direction has led to the deposition of stacks of multi-layer thin films followed by patterning and etching of HAR features. Etching these HAR features requires the development of hard masks with excellent selectivity to the underlying stack. However, such high selectivity hard masks invariably impart a high level of stress to the wafer. With subsequent etching and patterning of these wafers, the stress is relieved selectively and can lead to either global or local isotropic and anisotropic behavior of the wafer strain. This strain manifests itself as an Out of Plane Distortion (OPD) and is accompanied by an In Plane Distortion (IPD). This resulting IPD affects the overlay of the patterning layers and affects yield, especially at the edge of the wafer. Industry has been using backside-deposited films to control global wafer warp but has not found a way to actively control local stresses that lead to IPD related alignment and overlay error. A novel approach to compensate for both the global and local stress induced IPD by co-optimizing the deposition of a backside stress compensation layer and ion implantation into this layer by scanning a Gaussian profiled ion beam over it is presented in this paper. This can potentially reduce burden at the wafer alignment correction in the lithography steps. In addition, this can also reduce the number of alignment points and enable low order wafer alignment schemes that meet the target overlay error specifications.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117129689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145971
Kazuma Hasegawa, Yuta Aiba, Xu Li, Hitomi Tanaka, T. Miyazaki, Hideko Mukaida, M. Koyanagi, Masayuki Miura, T. Sanuki
Power consumption and thermal throttling of the 3D flash memory have become a prevalent issue owing to the requirement for higher performance in SSDs. One of the main causes is the on-die charge pump circuit, which has a low conversion efficiency and induces high heat generation. The heat generation becomes a critical issue due to the high-density mounting of components, especially in mobile products. In this work, we fabricated a 3D flash memory with an in-package boost converter to replace the on-die charge pump circuit. The boost converter consists of three types of discrete components: a DC-DC converter, an inductor, and capacitors. Using the in package boost converter, we show that the power consumption can be reduced by up to 39% while the temperature rise can be reduced by 50%. Furthermore, when the number of word line (WL) layers reaches 1000, a significantly large power reduction up to 43% can be achieved, resulting in 9% smaller power consumption compared to the conventional 1xx layers. The proposed in-package boost converter is an effective scheme to suppress the power consumption and heat generation and can realize the development of a thermal throttling-less SSD.
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