Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145971
Kazuma Hasegawa, Yuta Aiba, Xu Li, Hitomi Tanaka, T. Miyazaki, Hideko Mukaida, M. Koyanagi, Masayuki Miura, T. Sanuki
Power consumption and thermal throttling of the 3D flash memory have become a prevalent issue owing to the requirement for higher performance in SSDs. One of the main causes is the on-die charge pump circuit, which has a low conversion efficiency and induces high heat generation. The heat generation becomes a critical issue due to the high-density mounting of components, especially in mobile products. In this work, we fabricated a 3D flash memory with an in-package boost converter to replace the on-die charge pump circuit. The boost converter consists of three types of discrete components: a DC-DC converter, an inductor, and capacitors. Using the in package boost converter, we show that the power consumption can be reduced by up to 39% while the temperature rise can be reduced by 50%. Furthermore, when the number of word line (WL) layers reaches 1000, a significantly large power reduction up to 43% can be achieved, resulting in 9% smaller power consumption compared to the conventional 1xx layers. The proposed in-package boost converter is an effective scheme to suppress the power consumption and heat generation and can realize the development of a thermal throttling-less SSD.
{"title":"Low Power and Thermal Throttling-less SSD with In-Package Boost Converter for 1000-WL Layer 3D Flash Memory","authors":"Kazuma Hasegawa, Yuta Aiba, Xu Li, Hitomi Tanaka, T. Miyazaki, Hideko Mukaida, M. Koyanagi, Masayuki Miura, T. Sanuki","doi":"10.1109/IMW56887.2023.10145971","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145971","url":null,"abstract":"Power consumption and thermal throttling of the 3D flash memory have become a prevalent issue owing to the requirement for higher performance in SSDs. One of the main causes is the on-die charge pump circuit, which has a low conversion efficiency and induces high heat generation. The heat generation becomes a critical issue due to the high-density mounting of components, especially in mobile products. In this work, we fabricated a 3D flash memory with an in-package boost converter to replace the on-die charge pump circuit. The boost converter consists of three types of discrete components: a DC-DC converter, an inductor, and capacitors. Using the in package boost converter, we show that the power consumption can be reduced by up to 39% while the temperature rise can be reduced by 50%. Furthermore, when the number of word line (WL) layers reaches 1000, a significantly large power reduction up to 43% can be achieved, resulting in 9% smaller power consumption compared to the conventional 1xx layers. The proposed in-package boost converter is an effective scheme to suppress the power consumption and heat generation and can realize the development of a thermal throttling-less SSD.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"399 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122776491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145816
W. Chien, E. Lai, L. Buzi, C. Cheng, C. Yeh, A. Ray, L. Gignac, N. Gong, H. Cheng, A. Grun, D. Y. Lee, W. Kim, A. Majumdar, Douglas M. Bishop, R. Bruce, D. Daudelin, H. Ho, M. BrightSky, H. Lung
We present a scaling study on phase change memory (PCM)-ovonic threshold switches (OTS) memory cells for storage class memory (SCM) applications. For the first time, the device size effect on the electrical characteristics of OTS-PCM cells is experimentally characterized with simulation support. It is found that the SET threshold voltage (VtS) of OTS-PCM cells increases as the device area scales down because of processinduced defects, as observed from experimental measurements and demonstrated with simulations. An optimized process is proposed and experimentally verified to minimize the VtS shift issue based on wafer level characterization. More importantly, combining the measurements and simulation, the device scaling trends down to sub-10 nanometers are provided for future high density cross-point PCM (XPCM) chips.
{"title":"A Comprehensive Study on the Pillar Size of OTS-PCM Memory with an Optimized Process and Scaling Trends Down to Sub-10 nm for SCM Applications","authors":"W. Chien, E. Lai, L. Buzi, C. Cheng, C. Yeh, A. Ray, L. Gignac, N. Gong, H. Cheng, A. Grun, D. Y. Lee, W. Kim, A. Majumdar, Douglas M. Bishop, R. Bruce, D. Daudelin, H. Ho, M. BrightSky, H. Lung","doi":"10.1109/IMW56887.2023.10145816","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145816","url":null,"abstract":"We present a scaling study on phase change memory (PCM)-ovonic threshold switches (OTS) memory cells for storage class memory (SCM) applications. For the first time, the device size effect on the electrical characteristics of OTS-PCM cells is experimentally characterized with simulation support. It is found that the SET threshold voltage (VtS) of OTS-PCM cells increases as the device area scales down because of processinduced defects, as observed from experimental measurements and demonstrated with simulations. An optimized process is proposed and experimentally verified to minimize the VtS shift issue based on wafer level characterization. More importantly, combining the measurements and simulation, the device scaling trends down to sub-10 nanometers are provided for future high density cross-point PCM (XPCM) chips.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127135279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145953
P. Subrahmanyan, Wonjae Lee, Jeffrey D Lischer, Ram Karur, Olga Kucher, S. Todorov, A. Osonkie
In a continuous effort to reduce bit cost, industry has been scaling in the Z direction thus leading to high aspect ratio (HAR) devices. This has been prevalent in the 3DNAND device segment and is forecast to extend to the DRAM device segment with 3DDRAM architectures. The growth in the Z direction has led to the deposition of stacks of multi-layer thin films followed by patterning and etching of HAR features. Etching these HAR features requires the development of hard masks with excellent selectivity to the underlying stack. However, such high selectivity hard masks invariably impart a high level of stress to the wafer. With subsequent etching and patterning of these wafers, the stress is relieved selectively and can lead to either global or local isotropic and anisotropic behavior of the wafer strain. This strain manifests itself as an Out of Plane Distortion (OPD) and is accompanied by an In Plane Distortion (IPD). This resulting IPD affects the overlay of the patterning layers and affects yield, especially at the edge of the wafer. Industry has been using backside-deposited films to control global wafer warp but has not found a way to actively control local stresses that lead to IPD related alignment and overlay error. A novel approach to compensate for both the global and local stress induced IPD by co-optimizing the deposition of a backside stress compensation layer and ion implantation into this layer by scanning a Gaussian profiled ion beam over it is presented in this paper. This can potentially reduce burden at the wafer alignment correction in the lithography steps. In addition, this can also reduce the number of alignment points and enable low order wafer alignment schemes that meet the target overlay error specifications.
{"title":"Overlay Control in HAR device integration","authors":"P. Subrahmanyan, Wonjae Lee, Jeffrey D Lischer, Ram Karur, Olga Kucher, S. Todorov, A. Osonkie","doi":"10.1109/IMW56887.2023.10145953","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145953","url":null,"abstract":"In a continuous effort to reduce bit cost, industry has been scaling in the Z direction thus leading to high aspect ratio (HAR) devices. This has been prevalent in the 3DNAND device segment and is forecast to extend to the DRAM device segment with 3DDRAM architectures. The growth in the Z direction has led to the deposition of stacks of multi-layer thin films followed by patterning and etching of HAR features. Etching these HAR features requires the development of hard masks with excellent selectivity to the underlying stack. However, such high selectivity hard masks invariably impart a high level of stress to the wafer. With subsequent etching and patterning of these wafers, the stress is relieved selectively and can lead to either global or local isotropic and anisotropic behavior of the wafer strain. This strain manifests itself as an Out of Plane Distortion (OPD) and is accompanied by an In Plane Distortion (IPD). This resulting IPD affects the overlay of the patterning layers and affects yield, especially at the edge of the wafer. Industry has been using backside-deposited films to control global wafer warp but has not found a way to actively control local stresses that lead to IPD related alignment and overlay error. A novel approach to compensate for both the global and local stress induced IPD by co-optimizing the deposition of a backside stress compensation layer and ion implantation into this layer by scanning a Gaussian profiled ion beam over it is presented in this paper. This can potentially reduce burden at the wafer alignment correction in the lithography steps. In addition, this can also reduce the number of alignment points and enable low order wafer alignment schemes that meet the target overlay error specifications.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117129689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145945
K. Seidel, D. Lehninger, F. Müller, Y. Raffel, A. Sünbül, Ricardo Revello, R. Hoffmann, S. De, T. Kämpfe, M. Lederer
In this paper we discuss the current research status of ferroelectric memory solutions and reflect it with application requirements. In focus are mainly three promising emerging memory device technologies based on ferroelectric (FE) hafnium oxide: front-end of line (FEoL) implemented FeFET, and the two FE-capacitor based solutions FeRAM and ITIC FeFET. These device technologies are discussed with respect to aspects like scaling opportunity, reliability, and maturity level, reflecting with current and future application requirements as well as conventional memory solutions.
{"title":"Hafnium oxide-based Ferroelectric Memories: Are we ready for Application?","authors":"K. Seidel, D. Lehninger, F. Müller, Y. Raffel, A. Sünbül, Ricardo Revello, R. Hoffmann, S. De, T. Kämpfe, M. Lederer","doi":"10.1109/IMW56887.2023.10145945","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145945","url":null,"abstract":"In this paper we discuss the current research status of ferroelectric memory solutions and reflect it with application requirements. In focus are mainly three promising emerging memory device technologies based on ferroelectric (FE) hafnium oxide: front-end of line (FEoL) implemented FeFET, and the two FE-capacitor based solutions FeRAM and ITIC FeFET. These device technologies are discussed with respect to aspects like scaling opportunity, reliability, and maturity level, reflecting with current and future application requirements as well as conventional memory solutions.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"46 6 Pt 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125706304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145951
Alessandro Grossi, M. Coppetta, S. Aresu, A. Kux, T. Kern, R. Strenz
We present features adding extra reliability margin for emerging Non-Volatile Memories adoption in automotive microcontrollers, and discuss experimental data of embedded 28nm RRAM Data Memory on high statistics from a microcontroller demonstrator. The results reported show that 28nm embedded RRAM reached an adequate maturity and is ready for replacement of embedded Flash in automotive applications.
{"title":"28nm Data Memory with Embedded RRAM Technology in Automotive Microcontrollers","authors":"Alessandro Grossi, M. Coppetta, S. Aresu, A. Kux, T. Kern, R. Strenz","doi":"10.1109/IMW56887.2023.10145951","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145951","url":null,"abstract":"We present features adding extra reliability margin for emerging Non-Volatile Memories adoption in automotive microcontrollers, and discuss experimental data of embedded 28nm RRAM Data Memory on high statistics from a microcontroller demonstrator. The results reported show that 28nm embedded RRAM reached an adequate maturity and is ready for replacement of embedded Flash in automotive applications.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130125284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145927
D. Lehninger, A. Sünbül, R. Olivo, T. Kämpfe, K. Seidel, M. Lederer
Abstract-Many modern applications require fast, reliable, and energy-efficient non-volatile memories. Ferroelectric memories like the ferroelectric field effect transistor (FeFET) and the ferroelectric random access memory (FeRAM) are promising to meet these requirements. In particular, the automotive sector places additional high demands in terms of reliability at high operation temperatures up to 150°C. Ferroelectric superlattices consisting of a periodic arrangement of HfO2 and ZrO2 sublayers are promising to meet these requirements. Herein, such superlattices of various sublayer thicknesses and a constant total thickness of $10 mathrm{~nm}$ were embedded into metal-ferroelectricmetal (MFM) capacitors and electrically characterized regarding compliance with the desired ambient temperature specifications of the automotive market. It is shown that superlattices with relatively thick sublayers ($geq 1 mathrm{~nm}$) significantly outperform standard $10 mathrm{~nm}(mathrm{Hf}, mathrm{Zr}) mathrm{O}_{2}$ reference films in terms of leakage resistance at demanding bias and temperature stress conditions.
{"title":"Ferroelectric HfO2/ZrO2 Superlattices with Improved Leakage at Bias and Temperature Stress","authors":"D. Lehninger, A. Sünbül, R. Olivo, T. Kämpfe, K. Seidel, M. Lederer","doi":"10.1109/IMW56887.2023.10145927","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145927","url":null,"abstract":"Abstract-Many modern applications require fast, reliable, and energy-efficient non-volatile memories. Ferroelectric memories like the ferroelectric field effect transistor (FeFET) and the ferroelectric random access memory (FeRAM) are promising to meet these requirements. In particular, the automotive sector places additional high demands in terms of reliability at high operation temperatures up to 150°C. Ferroelectric superlattices consisting of a periodic arrangement of HfO2 and ZrO2 sublayers are promising to meet these requirements. Herein, such superlattices of various sublayer thicknesses and a constant total thickness of $10 mathrm{~nm}$ were embedded into metal-ferroelectricmetal (MFM) capacitors and electrically characterized regarding compliance with the desired ambient temperature specifications of the automotive market. It is shown that superlattices with relatively thick sublayers ($geq 1 mathrm{~nm}$) significantly outperform standard $10 mathrm{~nm}(mathrm{Hf}, mathrm{Zr}) mathrm{O}_{2}$ reference films in terms of leakage resistance at demanding bias and temperature stress conditions.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134382142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145937
Soochan Chung, Dong-Hyeon Ko, Joonsung Lim, Kyung-Hee Kim, Sejie Takaki, Y. Seo, Byoungil Lee, Sejun Park, Jaeduk Lee, K. Noh, Sungjin Ahn, Sunghoi Hur
Over the past few decades, a greater need for 3D Vertical NAND (V-NAND) flash memory storage capacity has emerged. Compared to its prevailing technical predecessor, a quad-level cell (QLC) NAND flash memory can be a perfect replacement to meet the needs for the higher density and lower cost non-volatile memory market. However, despite these benefits, QLC’s market share has not been growing significantly because of its worse device reliability and slower performance. In this Paper, a new highly mass-producible and highly reliable 1Tb QLC 3D NAND flash memory with 176-word-line (WL) and Cell-Over-Peripheral (COP) architecture along with a number of significant process advancements will be presented.
在过去的几十年里，出现了对3D垂直NAND (V-NAND)闪存存储容量的更大需求。与现有的技术相比，四电平单元(QLC) NAND闪存可以完美地满足高密度和低成本非易失性存储器市场的需求。然而，尽管有这些好处，由于其较差的设备可靠性和较慢的性能，QLC的市场份额并没有显著增长。本文将介绍一种具有176字行(WL)和Cell-Over-Peripheral (COP)架构的新型高量产和高可靠性的1Tb QLC 3D NAND闪存，以及一些重要的工艺进步。
{"title":"Process Improvements for 7th Generation 1Tb Quad-Level Cell 3D NAND Flash Memory in Mass Production","authors":"Soochan Chung, Dong-Hyeon Ko, Joonsung Lim, Kyung-Hee Kim, Sejie Takaki, Y. Seo, Byoungil Lee, Sejun Park, Jaeduk Lee, K. Noh, Sungjin Ahn, Sunghoi Hur","doi":"10.1109/IMW56887.2023.10145937","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145937","url":null,"abstract":"Over the past few decades, a greater need for 3D Vertical NAND (V-NAND) flash memory storage capacity has emerged. Compared to its prevailing technical predecessor, a quad-level cell (QLC) NAND flash memory can be a perfect replacement to meet the needs for the higher density and lower cost non-volatile memory market. However, despite these benefits, QLC’s market share has not been growing significantly because of its worse device reliability and slower performance. In this Paper, a new highly mass-producible and highly reliable 1Tb QLC 3D NAND flash memory with 176-word-line (WL) and Cell-Over-Peripheral (COP) architecture along with a number of significant process advancements will be presented.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134285025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145964
P. Tseng, Tian-Cig Bo, Yu-Hsuan Lin, Yu-Chao Lin, Jhe-Yi Liao, F. Lee, Yu-Yu Lin, Ming-Hsiu Lee, K. Hsieh, Keh-Chung Wang, Chih-Yuan Lu
We proposed a novel in-memory-approximate-search (IMAS) method from single-level cell (SLC) to multi-level cell (MLC) based on our commercial 48-layer (48L) and 96-layer (96L) 3D-NAND flash technology. The method with word-line input as search word provides ultra-high parallel searching capability with the database stored in high-density 3D NAND-flash IMAS chip(s). The input search word can be compared with $128mathrm{~K}$ data words in just one read cycle, where the Hamming distance (HD) computation (for SLC approach) or similarity computation (for MLC approach) can be carried out within the memory array. Latest 96L 3D-NAND IMAS chip with CMOS under array (CuA) technology provides small chip size, long search/data word, excellent output resolution, and wide matching criteria for the tolerance on sensing current variation. Application on Memory-Augmented Neural Network (MANN) was demonstrated on VGGface2 dataset, with the comparisons between the 48L and 96L SLC 3D-NAND IMAS technologies.
{"title":"SLC and MLC In-Memory-Approximate-Search Solutions in Commercial 48-layer and 96-layer 3D-NAND Flash Memories","authors":"P. Tseng, Tian-Cig Bo, Yu-Hsuan Lin, Yu-Chao Lin, Jhe-Yi Liao, F. Lee, Yu-Yu Lin, Ming-Hsiu Lee, K. Hsieh, Keh-Chung Wang, Chih-Yuan Lu","doi":"10.1109/IMW56887.2023.10145964","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145964","url":null,"abstract":"We proposed a novel in-memory-approximate-search (IMAS) method from single-level cell (SLC) to multi-level cell (MLC) based on our commercial 48-layer (48L) and 96-layer (96L) 3D-NAND flash technology. The method with word-line input as search word provides ultra-high parallel searching capability with the database stored in high-density 3D NAND-flash IMAS chip(s). The input search word can be compared with $128mathrm{~K}$ data words in just one read cycle, where the Hamming distance (HD) computation (for SLC approach) or similarity computation (for MLC approach) can be carried out within the memory array. Latest 96L 3D-NAND IMAS chip with CMOS under array (CuA) technology provides small chip size, long search/data word, excellent output resolution, and wide matching criteria for the tolerance on sensing current variation. Application on Memory-Augmented Neural Network (MANN) was demonstrated on VGGface2 dataset, with the comparisons between the 48L and 96L SLC 3D-NAND IMAS technologies.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129532629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145928
Z. A. Bai, Yixian Wang, Lixue Liu, Xi Zhang, Feng Yuan, Junsheng Meng, Zhongming Liu, Js Jeon, James Cho, Blacksmith Wu, Huihui Li, Guilei Wang, Chao Zhao, Kanyu Cao
Dielectric relaxation in high-κ storage capacitors can lead to significant degradation of capacitance values and hence deteriorate read bit-error rates of DRAMs. However, the mechanism of the dielectric relaxation phenomenon in high-κ dielectric oxides and multilayer stacks is still controversial. Moreover, previous work studied the dielectric relaxation phenomenon only at high-κ film level, which lacks the necessary insights into DRAM-specific complexities and performance improvement strategies. In this work, we first set up modeling and electric testing methodologies that can reliably collect and model dielectric relaxation signal in modern DRAM high-κ capacitors at both single-cell and chip levels. Experiment and simulation evidences based on these methodologies were then presented to identify and validate charge trapping-detrapping as the physical origin of dielectric relaxation in the frequency realm of DRAM operations. Dielectric relaxation performance improvement strategies were further provided, in particular for the latest storage capacitors with HfO2 being implemented.
{"title":"Dielectric Relaxation Performance of DRAM Storage Capacitors and Ways of Improvement","authors":"Z. A. Bai, Yixian Wang, Lixue Liu, Xi Zhang, Feng Yuan, Junsheng Meng, Zhongming Liu, Js Jeon, James Cho, Blacksmith Wu, Huihui Li, Guilei Wang, Chao Zhao, Kanyu Cao","doi":"10.1109/IMW56887.2023.10145928","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145928","url":null,"abstract":"Dielectric relaxation in high-κ storage capacitors can lead to significant degradation of capacitance values and hence deteriorate read bit-error rates of DRAMs. However, the mechanism of the dielectric relaxation phenomenon in high-κ dielectric oxides and multilayer stacks is still controversial. Moreover, previous work studied the dielectric relaxation phenomenon only at high-κ film level, which lacks the necessary insights into DRAM-specific complexities and performance improvement strategies. In this work, we first set up modeling and electric testing methodologies that can reliably collect and model dielectric relaxation signal in modern DRAM high-κ capacitors at both single-cell and chip levels. Experiment and simulation evidences based on these methodologies were then presented to identify and validate charge trapping-detrapping as the physical origin of dielectric relaxation in the frequency realm of DRAM operations. Dielectric relaxation performance improvement strategies were further provided, in particular for the latest storage capacitors with HfO2 being implemented.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116803598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145822
Jeong-Hun Choe
Emerging memory products such as STT-MRAM, PCRAM, ReRAM, FeRAM, and XPoint Memory have been successfully commercialized on market for more than a decade, especially for DDR, SCM (storage-class memory), and embedded cache applications. Among them, STT-MRAM technology is now popular for cache memory replacing eSRAM, eFLASH, and eDRAM. Semiconductor foundries and IDMs are focusing more on MRAM with stand-alone type or embedded devices. They’re developing, producing, and scaling down the MRAM cell design to 22 nm and beyond. Further, the MTJ structure is quite complicated and complex due to multilayers such as synthetic antiferro-magnetics, ferromagnetic, and even they use a dual tunnel barrier structure, and multi-layered diffusion barriers, spacers, and coupling layers added into the structure for high performance and structural stability. We review and discuss the structure, materials, design, and process technology of STTMRAM products up to date, and challenges as well.
{"title":"Recent Technology Insights on STT-MRAM: Structure, Materials, and Process Integration","authors":"Jeong-Hun Choe","doi":"10.1109/IMW56887.2023.10145822","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145822","url":null,"abstract":"Emerging memory products such as STT-MRAM, PCRAM, ReRAM, FeRAM, and XPoint Memory have been successfully commercialized on market for more than a decade, especially for DDR, SCM (storage-class memory), and embedded cache applications. Among them, STT-MRAM technology is now popular for cache memory replacing eSRAM, eFLASH, and eDRAM. Semiconductor foundries and IDMs are focusing more on MRAM with stand-alone type or embedded devices. They’re developing, producing, and scaling down the MRAM cell design to 22 nm and beyond. Further, the MTJ structure is quite complicated and complex due to multilayers such as synthetic antiferro-magnetics, ferromagnetic, and even they use a dual tunnel barrier structure, and multi-layered diffusion barriers, spacers, and coupling layers added into the structure for high performance and structural stability. We review and discuss the structure, materials, design, and process technology of STTMRAM products up to date, and challenges as well.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115538597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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