Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145946
S. Subhechha, S. Cosemans, A. Belmonte, N. Rassoul, S. H. Sharifi, P. Debacker, D. Verkest, R. Delhougne, G. Kar
We report on the first demonstration of multilevel multiply accumulation operations in 2TlC cell arrays based on amorphous IGZO TFTs for efficient analog in memory compute (AiMC) implementation. Device designs for the read and write transistors to meet the target specifications are discussed and implemented. Multilevel operations are realized thanks to the long retention time enabled by the ultra-low offcurrent (<1.5× 1$0^{-19}$A/$mu$m) of the a-IGZO TFTs.
{"title":"Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays","authors":"S. Subhechha, S. Cosemans, A. Belmonte, N. Rassoul, S. H. Sharifi, P. Debacker, D. Verkest, R. Delhougne, G. Kar","doi":"10.1109/IMW56887.2023.10145946","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145946","url":null,"abstract":"We report on the first demonstration of multilevel multiply accumulation operations in 2TlC cell arrays based on amorphous IGZO TFTs for efficient analog in memory compute (AiMC) implementation. Device designs for the read and write transistors to meet the target specifications are discussed and implemented. Multilevel operations are realized thanks to the long retention time enabled by the ultra-low offcurrent (<1.5× 1$0^{-19}$A/$mu$m) of the a-IGZO TFTs.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115641695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145945
K. Seidel, D. Lehninger, F. Müller, Y. Raffel, A. Sünbül, Ricardo Revello, R. Hoffmann, S. De, T. Kämpfe, M. Lederer
In this paper we discuss the current research status of ferroelectric memory solutions and reflect it with application requirements. In focus are mainly three promising emerging memory device technologies based on ferroelectric (FE) hafnium oxide: front-end of line (FEoL) implemented FeFET, and the two FE-capacitor based solutions FeRAM and ITIC FeFET. These device technologies are discussed with respect to aspects like scaling opportunity, reliability, and maturity level, reflecting with current and future application requirements as well as conventional memory solutions.
{"title":"Hafnium oxide-based Ferroelectric Memories: Are we ready for Application?","authors":"K. Seidel, D. Lehninger, F. Müller, Y. Raffel, A. Sünbül, Ricardo Revello, R. Hoffmann, S. De, T. Kämpfe, M. Lederer","doi":"10.1109/IMW56887.2023.10145945","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145945","url":null,"abstract":"In this paper we discuss the current research status of ferroelectric memory solutions and reflect it with application requirements. In focus are mainly three promising emerging memory device technologies based on ferroelectric (FE) hafnium oxide: front-end of line (FEoL) implemented FeFET, and the two FE-capacitor based solutions FeRAM and ITIC FeFET. These device technologies are discussed with respect to aspects like scaling opportunity, reliability, and maturity level, reflecting with current and future application requirements as well as conventional memory solutions.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"46 6 Pt 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125706304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145992
S. Rachidi, S. Ramesh, L. Breuil, Z. Tao, D. Verreck, G. Donadio, A. Arreghini, G. V. D. Bosch, M. Rosmeulen
3D Trench cells with a vertical flat channel have been proposed to increase the cell density over 3D NAND gate-all-around (GAA). In this work, we investigate the device characteristics of Trench cells. In absence of curvature, Trench cells exhibit inferior program and erase in comparison to a GAA reference. However, the memory window of Trench cells is significantly improved with channel width scaling, gate stack engineering and metal gate integration. This study also provides a basis for design and fabrication of future ultradense 3D NAND memories based on the Trench architecture.
{"title":"Enabling 3D NAND Trench Cells for Scaled Flash Memories","authors":"S. Rachidi, S. Ramesh, L. Breuil, Z. Tao, D. Verreck, G. Donadio, A. Arreghini, G. V. D. Bosch, M. Rosmeulen","doi":"10.1109/IMW56887.2023.10145992","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145992","url":null,"abstract":"3D Trench cells with a vertical flat channel have been proposed to increase the cell density over 3D NAND gate-all-around (GAA). In this work, we investigate the device characteristics of Trench cells. In absence of curvature, Trench cells exhibit inferior program and erase in comparison to a GAA reference. However, the memory window of Trench cells is significantly improved with channel width scaling, gate stack engineering and metal gate integration. This study also provides a basis for design and fabrication of future ultradense 3D NAND memories based on the Trench architecture.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122611420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145937
Soochan Chung, Dong-Hyeon Ko, Joonsung Lim, Kyung-Hee Kim, Sejie Takaki, Y. Seo, Byoungil Lee, Sejun Park, Jaeduk Lee, K. Noh, Sungjin Ahn, Sunghoi Hur
Over the past few decades, a greater need for 3D Vertical NAND (V-NAND) flash memory storage capacity has emerged. Compared to its prevailing technical predecessor, a quad-level cell (QLC) NAND flash memory can be a perfect replacement to meet the needs for the higher density and lower cost non-volatile memory market. However, despite these benefits, QLC’s market share has not been growing significantly because of its worse device reliability and slower performance. In this Paper, a new highly mass-producible and highly reliable 1Tb QLC 3D NAND flash memory with 176-word-line (WL) and Cell-Over-Peripheral (COP) architecture along with a number of significant process advancements will be presented.
在过去的几十年里，出现了对3D垂直NAND (V-NAND)闪存存储容量的更大需求。与现有的技术相比，四电平单元(QLC) NAND闪存可以完美地满足高密度和低成本非易失性存储器市场的需求。然而，尽管有这些好处，由于其较差的设备可靠性和较慢的性能，QLC的市场份额并没有显著增长。本文将介绍一种具有176字行(WL)和Cell-Over-Peripheral (COP)架构的新型高量产和高可靠性的1Tb QLC 3D NAND闪存，以及一些重要的工艺进步。
{"title":"Process Improvements for 7th Generation 1Tb Quad-Level Cell 3D NAND Flash Memory in Mass Production","authors":"Soochan Chung, Dong-Hyeon Ko, Joonsung Lim, Kyung-Hee Kim, Sejie Takaki, Y. Seo, Byoungil Lee, Sejun Park, Jaeduk Lee, K. Noh, Sungjin Ahn, Sunghoi Hur","doi":"10.1109/IMW56887.2023.10145937","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145937","url":null,"abstract":"Over the past few decades, a greater need for 3D Vertical NAND (V-NAND) flash memory storage capacity has emerged. Compared to its prevailing technical predecessor, a quad-level cell (QLC) NAND flash memory can be a perfect replacement to meet the needs for the higher density and lower cost non-volatile memory market. However, despite these benefits, QLC’s market share has not been growing significantly because of its worse device reliability and slower performance. In this Paper, a new highly mass-producible and highly reliable 1Tb QLC 3D NAND flash memory with 176-word-line (WL) and Cell-Over-Peripheral (COP) architecture along with a number of significant process advancements will be presented.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134285025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145951
Alessandro Grossi, M. Coppetta, S. Aresu, A. Kux, T. Kern, R. Strenz
We present features adding extra reliability margin for emerging Non-Volatile Memories adoption in automotive microcontrollers, and discuss experimental data of embedded 28nm RRAM Data Memory on high statistics from a microcontroller demonstrator. The results reported show that 28nm embedded RRAM reached an adequate maturity and is ready for replacement of embedded Flash in automotive applications.
{"title":"28nm Data Memory with Embedded RRAM Technology in Automotive Microcontrollers","authors":"Alessandro Grossi, M. Coppetta, S. Aresu, A. Kux, T. Kern, R. Strenz","doi":"10.1109/IMW56887.2023.10145951","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145951","url":null,"abstract":"We present features adding extra reliability margin for emerging Non-Volatile Memories adoption in automotive microcontrollers, and discuss experimental data of embedded 28nm RRAM Data Memory on high statistics from a microcontroller demonstrator. The results reported show that 28nm embedded RRAM reached an adequate maturity and is ready for replacement of embedded Flash in automotive applications.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130125284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145816
W. Chien, E. Lai, L. Buzi, C. Cheng, C. Yeh, A. Ray, L. Gignac, N. Gong, H. Cheng, A. Grun, D. Y. Lee, W. Kim, A. Majumdar, Douglas M. Bishop, R. Bruce, D. Daudelin, H. Ho, M. BrightSky, H. Lung
We present a scaling study on phase change memory (PCM)-ovonic threshold switches (OTS) memory cells for storage class memory (SCM) applications. For the first time, the device size effect on the electrical characteristics of OTS-PCM cells is experimentally characterized with simulation support. It is found that the SET threshold voltage (VtS) of OTS-PCM cells increases as the device area scales down because of processinduced defects, as observed from experimental measurements and demonstrated with simulations. An optimized process is proposed and experimentally verified to minimize the VtS shift issue based on wafer level characterization. More importantly, combining the measurements and simulation, the device scaling trends down to sub-10 nanometers are provided for future high density cross-point PCM (XPCM) chips.
{"title":"A Comprehensive Study on the Pillar Size of OTS-PCM Memory with an Optimized Process and Scaling Trends Down to Sub-10 nm for SCM Applications","authors":"W. Chien, E. Lai, L. Buzi, C. Cheng, C. Yeh, A. Ray, L. Gignac, N. Gong, H. Cheng, A. Grun, D. Y. Lee, W. Kim, A. Majumdar, Douglas M. Bishop, R. Bruce, D. Daudelin, H. Ho, M. BrightSky, H. Lung","doi":"10.1109/IMW56887.2023.10145816","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145816","url":null,"abstract":"We present a scaling study on phase change memory (PCM)-ovonic threshold switches (OTS) memory cells for storage class memory (SCM) applications. For the first time, the device size effect on the electrical characteristics of OTS-PCM cells is experimentally characterized with simulation support. It is found that the SET threshold voltage (VtS) of OTS-PCM cells increases as the device area scales down because of processinduced defects, as observed from experimental measurements and demonstrated with simulations. An optimized process is proposed and experimentally verified to minimize the VtS shift issue based on wafer level characterization. More importantly, combining the measurements and simulation, the device scaling trends down to sub-10 nanometers are provided for future high density cross-point PCM (XPCM) chips.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127135279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145927
D. Lehninger, A. Sünbül, R. Olivo, T. Kämpfe, K. Seidel, M. Lederer
Abstract-Many modern applications require fast, reliable, and energy-efficient non-volatile memories. Ferroelectric memories like the ferroelectric field effect transistor (FeFET) and the ferroelectric random access memory (FeRAM) are promising to meet these requirements. In particular, the automotive sector places additional high demands in terms of reliability at high operation temperatures up to 150°C. Ferroelectric superlattices consisting of a periodic arrangement of HfO2 and ZrO2 sublayers are promising to meet these requirements. Herein, such superlattices of various sublayer thicknesses and a constant total thickness of $10 mathrm{~nm}$ were embedded into metal-ferroelectricmetal (MFM) capacitors and electrically characterized regarding compliance with the desired ambient temperature specifications of the automotive market. It is shown that superlattices with relatively thick sublayers ($geq 1 mathrm{~nm}$) significantly outperform standard $10 mathrm{~nm}(mathrm{Hf}, mathrm{Zr}) mathrm{O}_{2}$ reference films in terms of leakage resistance at demanding bias and temperature stress conditions.
{"title":"Ferroelectric HfO2/ZrO2 Superlattices with Improved Leakage at Bias and Temperature Stress","authors":"D. Lehninger, A. Sünbül, R. Olivo, T. Kämpfe, K. Seidel, M. Lederer","doi":"10.1109/IMW56887.2023.10145927","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145927","url":null,"abstract":"Abstract-Many modern applications require fast, reliable, and energy-efficient non-volatile memories. Ferroelectric memories like the ferroelectric field effect transistor (FeFET) and the ferroelectric random access memory (FeRAM) are promising to meet these requirements. In particular, the automotive sector places additional high demands in terms of reliability at high operation temperatures up to 150°C. Ferroelectric superlattices consisting of a periodic arrangement of HfO2 and ZrO2 sublayers are promising to meet these requirements. Herein, such superlattices of various sublayer thicknesses and a constant total thickness of $10 mathrm{~nm}$ were embedded into metal-ferroelectricmetal (MFM) capacitors and electrically characterized regarding compliance with the desired ambient temperature specifications of the automotive market. It is shown that superlattices with relatively thick sublayers ($geq 1 mathrm{~nm}$) significantly outperform standard $10 mathrm{~nm}(mathrm{Hf}, mathrm{Zr}) mathrm{O}_{2}$ reference films in terms of leakage resistance at demanding bias and temperature stress conditions.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134382142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145964
P. Tseng, Tian-Cig Bo, Yu-Hsuan Lin, Yu-Chao Lin, Jhe-Yi Liao, F. Lee, Yu-Yu Lin, Ming-Hsiu Lee, K. Hsieh, Keh-Chung Wang, Chih-Yuan Lu
We proposed a novel in-memory-approximate-search (IMAS) method from single-level cell (SLC) to multi-level cell (MLC) based on our commercial 48-layer (48L) and 96-layer (96L) 3D-NAND flash technology. The method with word-line input as search word provides ultra-high parallel searching capability with the database stored in high-density 3D NAND-flash IMAS chip(s). The input search word can be compared with $128mathrm{~K}$ data words in just one read cycle, where the Hamming distance (HD) computation (for SLC approach) or similarity computation (for MLC approach) can be carried out within the memory array. Latest 96L 3D-NAND IMAS chip with CMOS under array (CuA) technology provides small chip size, long search/data word, excellent output resolution, and wide matching criteria for the tolerance on sensing current variation. Application on Memory-Augmented Neural Network (MANN) was demonstrated on VGGface2 dataset, with the comparisons between the 48L and 96L SLC 3D-NAND IMAS technologies.
{"title":"SLC and MLC In-Memory-Approximate-Search Solutions in Commercial 48-layer and 96-layer 3D-NAND Flash Memories","authors":"P. Tseng, Tian-Cig Bo, Yu-Hsuan Lin, Yu-Chao Lin, Jhe-Yi Liao, F. Lee, Yu-Yu Lin, Ming-Hsiu Lee, K. Hsieh, Keh-Chung Wang, Chih-Yuan Lu","doi":"10.1109/IMW56887.2023.10145964","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145964","url":null,"abstract":"We proposed a novel in-memory-approximate-search (IMAS) method from single-level cell (SLC) to multi-level cell (MLC) based on our commercial 48-layer (48L) and 96-layer (96L) 3D-NAND flash technology. The method with word-line input as search word provides ultra-high parallel searching capability with the database stored in high-density 3D NAND-flash IMAS chip(s). The input search word can be compared with $128mathrm{~K}$ data words in just one read cycle, where the Hamming distance (HD) computation (for SLC approach) or similarity computation (for MLC approach) can be carried out within the memory array. Latest 96L 3D-NAND IMAS chip with CMOS under array (CuA) technology provides small chip size, long search/data word, excellent output resolution, and wide matching criteria for the tolerance on sensing current variation. Application on Memory-Augmented Neural Network (MANN) was demonstrated on VGGface2 dataset, with the comparisons between the 48L and 96L SLC 3D-NAND IMAS technologies.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129532629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145947
Tobias Ziegler, Leon Brackmann, T. Hennen, C. Bengel, S. Menzel, D. Wouters
Shifting computations from the central processing unit to the memory is a promising approach to lower the stress on the Von-Neumann bottleneck and to reduce the total energy consumption spend on data transfer. One promising concept for in-memory computations is the associative capacitive network introduced by Kavehei et al.. The digital information is stored in complementary resistive switches which can be read using a non-destructive read out scheme. Simulation results based on the JART VCM vlb model demonstrate the working principle of the original input encoding and the existence of capacitive sneak path currents is identified. A new input encoding is proposed in this work which not only prevents capacitive sneak paths but also improves the voltage difference between Hamming Distances (HD).
{"title":"Eliminating Capacitive Sneak Paths in Associative Capacitive Networks based on Complementary Resistive Switches for In-Memory Computing","authors":"Tobias Ziegler, Leon Brackmann, T. Hennen, C. Bengel, S. Menzel, D. Wouters","doi":"10.1109/IMW56887.2023.10145947","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145947","url":null,"abstract":"Shifting computations from the central processing unit to the memory is a promising approach to lower the stress on the Von-Neumann bottleneck and to reduce the total energy consumption spend on data transfer. One promising concept for in-memory computations is the associative capacitive network introduced by Kavehei et al.. The digital information is stored in complementary resistive switches which can be read using a non-destructive read out scheme. Simulation results based on the JART VCM vlb model demonstrate the working principle of the original input encoding and the existence of capacitive sneak path currents is identified. A new input encoding is proposed in this work which not only prevents capacitive sneak paths but also improves the voltage difference between Hamming Distances (HD).","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129258264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-05-01DOI: 10.1109/IMW56887.2023.10145957
B. Ray, Matchima Buddhanoy, Mondol Anik Kumar
In this paper we present characterization results of total ionizing dose (TID) effects on commercial 3-D NAND memory. We show the TID induced threshold voltage shift and bit error rate of the memory array. Based on the characterization results we present four system-level techniques that can mitigate TID effects of the commercial 3-D NAND memory.
{"title":"Towards Improving Ionizing Radiation Tolerance of 3-D NAND Flash Memory","authors":"B. Ray, Matchima Buddhanoy, Mondol Anik Kumar","doi":"10.1109/IMW56887.2023.10145957","DOIUrl":"https://doi.org/10.1109/IMW56887.2023.10145957","url":null,"abstract":"In this paper we present characterization results of total ionizing dose (TID) effects on commercial 3-D NAND memory. We show the TID induced threshold voltage shift and bit error rate of the memory array. Based on the characterization results we present four system-level techniques that can mitigate TID effects of the commercial 3-D NAND memory.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114635852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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