Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499940
S. Ogawa, F. Shoji, T. Ohdaira, I. Suzuki, M. Shimada, R. Suzuki
The behavior of vacancies in electroplated-Cu films has been characterized by a positron-annihilation lifetime spectroscopy (PALS) method correlated with stress-induced voiding (SIV) phenomena. Positron lifetime showed inverse correlation with sheet resistance, and Cu films plated with lower plating currents showed less lifetime (/spl tau/) and intensity (I) of long-lifetime components than those plated with higher currents with less SIV failures.
{"title":"Behavior of vacancies in EP-Cu films by positron-annihilation lifetime spectroscopy and its impact on SIV phenomena","authors":"S. Ogawa, F. Shoji, T. Ohdaira, I. Suzuki, M. Shimada, R. Suzuki","doi":"10.1109/IITC.2005.1499940","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499940","url":null,"abstract":"The behavior of vacancies in electroplated-Cu films has been characterized by a positron-annihilation lifetime spectroscopy (PALS) method correlated with stress-induced voiding (SIV) phenomena. Positron lifetime showed inverse correlation with sheet resistance, and Cu films plated with lower plating currents showed less lifetime (/spl tau/) and intensity (I) of long-lifetime components than those plated with higher currents with less SIV failures.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131345543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499969
S. Uno, J. Noguchi, H. Ashihara, T. Oshima, K. Sato, N. Konishi, T. Saito, K. Hara
A dual damascene Cu air-gap interconnect was investigated. To solve issues such as cost and electrical shorts from CMP scratches, a conventional CVD film was used as a sacrificial layer instead of the SOD film that we reported previously. The process integration, electrical characteristics and the TDDB reliability were discussed. The TDDB lifetime was drastically improved, and 4 levels of dual damascene Cu interconnects were successfully fabricated.
{"title":"Dual damascene process for air-gap Cu interconnects using conventional CVD films as sacrificial layers","authors":"S. Uno, J. Noguchi, H. Ashihara, T. Oshima, K. Sato, N. Konishi, T. Saito, K. Hara","doi":"10.1109/IITC.2005.1499969","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499969","url":null,"abstract":"A dual damascene Cu air-gap interconnect was investigated. To solve issues such as cost and electrical shorts from CMP scratches, a conventional CVD film was used as a sacrificial layer instead of the SOD film that we reported previously. The process integration, electrical characteristics and the TDDB reliability were discussed. The TDDB lifetime was drastically improved, and 4 levels of dual damascene Cu interconnects were successfully fabricated.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133344678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499996
H. Chen, M. Haurylau, S. Weiss, J. Ruan, J. Zhang, H. Ouyang, P. Fauchet
An all silicon-based on-chip optical interconnect is a promising candidate to overcome the electrical interconnect bottleneck. In this study, we focus on two missing optical building blocks: light sources and modulators. One- and two-dimensional photonic bandgap modulators are demonstrated. Light amplification is achieved in silicon nanocrystals and a distributed Bragg reflector is fabricated and tested to explore the possibility of a silicon laser.
{"title":"Silicon-based building blocks for VLSI on-chip optical interconnects","authors":"H. Chen, M. Haurylau, S. Weiss, J. Ruan, J. Zhang, H. Ouyang, P. Fauchet","doi":"10.1109/IITC.2005.1499996","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499996","url":null,"abstract":"An all silicon-based on-chip optical interconnect is a promising candidate to overcome the electrical interconnect bottleneck. In this study, we focus on two missing optical building blocks: light sources and modulators. One- and two-dimensional photonic bandgap modulators are demonstrated. Light amplification is achieved in silicon nanocrystals and a distributed Bragg reflector is fabricated and tested to explore the possibility of a silicon laser.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123049633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499922
C. Guedj, V. Arnal, J. Guillaumond, L. Arnaud, J. Barnes, A. Toffoli, V. Jousseaume, A. Roule, S. Maitrejean, L. Chapelon, G. Reimbold, J. Torres, G. Passemard
With the scaling down of copper interconnects, the importance of interface engineering becomes more and more crucial. In this paper, we have studied the influence of the diffusion barriers on the electrical performance and dielectric reliability of porous ULK/Cu interconnects, in comparison with a reference dense SiCOH dielectric. The best reliability for the porous ULK is obtained with the thicker barrier, consisting of CVD TiN. With this barrier; the porous ULK can even outperform the dense dielectric in terms of time to failures and dielectric breakdown in certain cases. For the TaN barrier, an H/sub 2/ plasma after etch improves the breakdown voltage up to 34%. A voiding at the top Cu comers after storage in the 110/spl deg/C-150/spl deg/C range under N/sub 2/ has been identified as a possible contribution to the fracture of the SiCN top capping layer. Therefore the Cu itself is critical for the dielectric reliability.
{"title":"Influence of the diffusion barriers on the dielectric reliability of ULK/Cu advanced interconnects","authors":"C. Guedj, V. Arnal, J. Guillaumond, L. Arnaud, J. Barnes, A. Toffoli, V. Jousseaume, A. Roule, S. Maitrejean, L. Chapelon, G. Reimbold, J. Torres, G. Passemard","doi":"10.1109/IITC.2005.1499922","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499922","url":null,"abstract":"With the scaling down of copper interconnects, the importance of interface engineering becomes more and more crucial. In this paper, we have studied the influence of the diffusion barriers on the electrical performance and dielectric reliability of porous ULK/Cu interconnects, in comparison with a reference dense SiCOH dielectric. The best reliability for the porous ULK is obtained with the thicker barrier, consisting of CVD TiN. With this barrier; the porous ULK can even outperform the dense dielectric in terms of time to failures and dielectric breakdown in certain cases. For the TaN barrier, an H/sub 2/ plasma after etch improves the breakdown voltage up to 34%. A voiding at the top Cu comers after storage in the 110/spl deg/C-150/spl deg/C range under N/sub 2/ has been identified as a possible contribution to the fracture of the SiCN top capping layer. Therefore the Cu itself is critical for the dielectric reliability.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123850421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499912
J. Debord, T. Grice, R. Garcia, G. Yeric, E. Cohen, A. Sutandi, J. Garcia, G. Green
BEOL yield characterization is increasingly difficult on advanced technology nodes using traditional short flow devices. A new BEOL technology development read only memory (TDROM/spl trade/) has been used to successfully drive BEOL yield learning on the 65 nm node. The addressable nature of the TDROM/spl trade/ allows isolation of all fails to within 2 um/sup 2/ using known memory testing techniques which has resulted in accelerated yield learning, and PFA utilization. The eight megabit array size allows exhaustive DOE for all design rules and margins.
{"title":"Infrastructure for successful BEOL characterization and yield ramp at the 65 nm node and below","authors":"J. Debord, T. Grice, R. Garcia, G. Yeric, E. Cohen, A. Sutandi, J. Garcia, G. Green","doi":"10.1109/IITC.2005.1499912","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499912","url":null,"abstract":"BEOL yield characterization is increasingly difficult on advanced technology nodes using traditional short flow devices. A new BEOL technology development read only memory (TDROM/spl trade/) has been used to successfully drive BEOL yield learning on the 65 nm node. The addressable nature of the TDROM/spl trade/ allows isolation of all fails to within 2 um/sup 2/ using known memory testing techniques which has resulted in accelerated yield learning, and PFA utilization. The eight megabit array size allows exhaustive DOE for all design rules and margins.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127353840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499989
K. Yoneda, M. Kato, S. Kondo, N. Kobayashi, N. Matsuki, K. Matsushita, N. Ohara, A. Fukazawa, T. Kimura
An ultra violet (UV) cure was investigated to improve the mechanical and electrical properties of porous carbon-doped PECVD (plasma enhanced chemical vapor deposition) oxide film (k<2.4) for the 45 nm node technology and beyond. Drastic improvement in the film modulus and leakage current between Cu interconnects was observed. The formation of Si-O chemical bonds by breaking Si-CH/sub 3/ bonds after UV irradiation is thought to be an origin for the results of Si-O-C-H networks in p-SIOC films.
为了改善45 nm及以上节点技术的多孔碳掺杂PECVD(等离子体增强化学气相沉积)氧化膜(k<2.4)的力学和电学性能，研究了紫外线固化方法。观察到铜互连之间的薄膜模量和泄漏电流的显著改善。紫外光照射后通过破坏Si-CH/sub - 3/键形成Si-O化学键被认为是p-SIOC薄膜中Si-O- c - h网络结果的来源。
{"title":"Impacts of UV cure for reliable porous PECVD SiOC integration [IC interconnect applications]","authors":"K. Yoneda, M. Kato, S. Kondo, N. Kobayashi, N. Matsuki, K. Matsushita, N. Ohara, A. Fukazawa, T. Kimura","doi":"10.1109/IITC.2005.1499989","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499989","url":null,"abstract":"An ultra violet (UV) cure was investigated to improve the mechanical and electrical properties of porous carbon-doped PECVD (plasma enhanced chemical vapor deposition) oxide film (k<2.4) for the 45 nm node technology and beyond. Drastic improvement in the film modulus and leakage current between Cu interconnects was observed. The formation of Si-O chemical bonds by breaking Si-CH/sub 3/ bonds after UV irradiation is thought to be an origin for the results of Si-O-C-H networks in p-SIOC films.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121694563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499918
T. Furusawa, N. Miura, M. Matsumoto, K. Goto, S. Hashii, Y. Fujiwara, K. Yoshikawa, K. Yonekura, Y. Asano, T. Ichiki, N. Kawanabe, T. Matsuzawa, M. Matsuura
A UV-hardened high-modulus ULK (ultra low-k) material is proposed for 45-nm-node Cu/low-k interconnects with homogeneous dielectric structures. An elastic modulus as high as 16 GPa was achieved for the ULK material with k=2.65. By combining this material with an advanced dielectric barrier (k=3.7), interconnect test devices with 65-nm-node dimensions were fabricated. The UV-hardened high-modulus ULK material is shown to be effective in improving electrical performance while maintaining sufficient mechanical integrity.
{"title":"UV-hardened high-modulus CVD-ULK material for 45-nm node Cu/low-k interconnects with homogeneous dielectric structures","authors":"T. Furusawa, N. Miura, M. Matsumoto, K. Goto, S. Hashii, Y. Fujiwara, K. Yoshikawa, K. Yonekura, Y. Asano, T. Ichiki, N. Kawanabe, T. Matsuzawa, M. Matsuura","doi":"10.1109/IITC.2005.1499918","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499918","url":null,"abstract":"A UV-hardened high-modulus ULK (ultra low-k) material is proposed for 45-nm-node Cu/low-k interconnects with homogeneous dielectric structures. An elastic modulus as high as 16 GPa was achieved for the ULK material with k=2.65. By combining this material with an advanced dielectric barrier (k=3.7), interconnect test devices with 65-nm-node dimensions were fabricated. The UV-hardened high-modulus ULK material is shown to be effective in improving electrical performance while maintaining sufficient mechanical integrity.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131480790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499953
P. Dumont-Girard, L. Gosset, S. Chhun, M. Juhel, V. Girault, G. Bryce, C. Prindle, J. Torres
The paper deals with the introduction of an innovative self-aligned capping layer leading to the formation of a Cu/Si/N mixed interface. The process was first developed targeting the aggressive 65 nm technology node and below. After optimisation, the process was successfully introduced in a well known Cu/FSG integration scheme prior to SiN etch stop layer deposition; process interest and maturity was demonstrated on 300 mm wafers in a 110 nm technology node by showing both its full compatibility with industrial requirements for stabilized technology and clear performance improvements in terms of electrical performance, defectivity and resistance to electromigration. These results open large perspectives for the integration of a Si-based self-aligned barrier on Cu lines, the process capability covering several technology nodes used either in addition to thin dielectric barriers or as a single capping of the copper lines.
{"title":"Investigation of an advanced SiH/sub 4/ based self-aligned barrier process for Cu BEOL reliability performance improvement on industrial 110 nm technology","authors":"P. Dumont-Girard, L. Gosset, S. Chhun, M. Juhel, V. Girault, G. Bryce, C. Prindle, J. Torres","doi":"10.1109/IITC.2005.1499953","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499953","url":null,"abstract":"The paper deals with the introduction of an innovative self-aligned capping layer leading to the formation of a Cu/Si/N mixed interface. The process was first developed targeting the aggressive 65 nm technology node and below. After optimisation, the process was successfully introduced in a well known Cu/FSG integration scheme prior to SiN etch stop layer deposition; process interest and maturity was demonstrated on 300 mm wafers in a 110 nm technology node by showing both its full compatibility with industrial requirements for stabilized technology and clear performance improvements in terms of electrical performance, defectivity and resistance to electromigration. These results open large perspectives for the integration of a Si-based self-aligned barrier on Cu lines, the process capability covering several technology nodes used either in addition to thin dielectric barriers or as a single capping of the copper lines.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129532412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499911
M. Naik, A. Shanmugasundram, T. Weidman, H. Fang, Z. Zhu, F. Mei, Y. Wang, K. Wijekoon, D. Lubomirsky, I. Pancham, M. Armacost
Electroless CoWP was integrated with k/spl sim/3.0 carbon doped oxide using SiCN as the post CMP dielectric barrier. Process parameters that impacted leakage performance and line resistance increase were identified and resolved. Leakage performance equivalent to uncapped samples was obtained with minimal increase (0-2%) in line resistance for 90 nm node critical dimension. Via chain yields of >95% were obtained for 1 million via count chain with via resistance similar to uncapped samples. A >20x improvement in electromigration median time (T/sub 50/) was obtained at twice the current density of uncapped samples. Feasibility of direct low k deposition on CoWP is explored.
{"title":"Process development and integration of electroless cobalt cap with low k carbon doped oxide","authors":"M. Naik, A. Shanmugasundram, T. Weidman, H. Fang, Z. Zhu, F. Mei, Y. Wang, K. Wijekoon, D. Lubomirsky, I. Pancham, M. Armacost","doi":"10.1109/IITC.2005.1499911","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499911","url":null,"abstract":"Electroless CoWP was integrated with k/spl sim/3.0 carbon doped oxide using SiCN as the post CMP dielectric barrier. Process parameters that impacted leakage performance and line resistance increase were identified and resolved. Leakage performance equivalent to uncapped samples was obtained with minimal increase (0-2%) in line resistance for 90 nm node critical dimension. Via chain yields of >95% were obtained for 1 million via count chain with via resistance similar to uncapped samples. A >20x improvement in electromigration median time (T/sub 50/) was obtained at twice the current density of uncapped samples. Feasibility of direct low k deposition on CoWP is explored.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132701813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499904
M. Fukasawa, S. Lane, M. Angyal, K. Chanda, F. Chen, C. Christiansen, J. Fitzsimmons, J. Gill, K. Ida, K. Inoue, K. Kumar, B. Li, P. McLaughlin, I. Melville, M. Minami, S. Nguyen, C. Penny, A. Sakamoto, Y. Shimooka, M. Ono, D. Mcherron, T. Nogami, T. Ivers
This paper describes a comprehensive characterization of a 65 nm, 300 mm wafer size interconnect technology with SiCOH material (k=2.8). Excellent film properties of the SiCOH material and precise process optimization enable the minimization of layer damage during etching and strip processes. 3D modeling reveals that the k-value of the SiCOH material was maintained at its initial value after the integration. Electrical yield, reliability and chip-to-package (CPI) evaluation are also presented. The results were comparable with the conventional SiCOH integration scheme.
{"title":"BEOL process integration with Cu/SiCOH (k=2.8) low-k interconnects at 65 nm groundrules","authors":"M. Fukasawa, S. Lane, M. Angyal, K. Chanda, F. Chen, C. Christiansen, J. Fitzsimmons, J. Gill, K. Ida, K. Inoue, K. Kumar, B. Li, P. McLaughlin, I. Melville, M. Minami, S. Nguyen, C. Penny, A. Sakamoto, Y. Shimooka, M. Ono, D. Mcherron, T. Nogami, T. Ivers","doi":"10.1109/IITC.2005.1499904","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499904","url":null,"abstract":"This paper describes a comprehensive characterization of a 65 nm, 300 mm wafer size interconnect technology with SiCOH material (k=2.8). Excellent film properties of the SiCOH material and precise process optimization enable the minimization of layer damage during etching and strip processes. 3D modeling reveals that the k-value of the SiCOH material was maintained at its initial value after the integration. Electrical yield, reliability and chip-to-package (CPI) evaluation are also presented. The results were comparable with the conventional SiCOH integration scheme.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114206994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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