Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499961
A. Naeemi, J. Meindl
It is shown that sub-ambient cooling can enhance the performance of GSI interconnects significantly if their design is re-optimized accordingly. Liquid-air cooling improves the latency of local interconnects significantly (e.g. 35% and 60% for 20 /spl mu/m long interconnects at 45 nm and 22 nm technology nodes, respectively), and makes semiglobal interconnects more than 150% faster. It also increases the number of bits per second that global interconnects can potentially transfer by more than 100%.
{"title":"Impact of deep sub-ambient cooling on GSI interconnect performance","authors":"A. Naeemi, J. Meindl","doi":"10.1109/IITC.2005.1499961","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499961","url":null,"abstract":"It is shown that sub-ambient cooling can enhance the performance of GSI interconnects significantly if their design is re-optimized accordingly. Liquid-air cooling improves the latency of local interconnects significantly (e.g. 35% and 60% for 20 /spl mu/m long interconnects at 45 nm and 22 nm technology nodes, respectively), and makes semiglobal interconnects more than 150% faster. It also increases the number of bits per second that global interconnects can potentially transfer by more than 100%.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132177665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499988
F. Iacopi, S. Brongersma, A. Mazurenko, H. Struyf, G. Mannaert, Y. Travaly, A. Maznev, T. Abell, J. Tower, K. Maex
A surface acoustic wave technique was successfully applied for monitoring modification/damage of low-k dielectrics resulting from plasma-based patterning in a non-destructive and non-contact fashion. It is shown that this technique can be used to assess and compare dielectric damage, due to different processing conditions, in patterned structures.
{"title":"Surface acoustic waves as a technique for in-line detection of processing damage to low-k dielectrics","authors":"F. Iacopi, S. Brongersma, A. Mazurenko, H. Struyf, G. Mannaert, Y. Travaly, A. Maznev, T. Abell, J. Tower, K. Maex","doi":"10.1109/IITC.2005.1499988","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499988","url":null,"abstract":"A surface acoustic wave technique was successfully applied for monitoring modification/damage of low-k dielectrics resulting from plasma-based patterning in a non-destructive and non-contact fashion. It is shown that this technique can be used to assess and compare dielectric damage, due to different processing conditions, in patterned structures.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126306803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499962
H. Thacker, O. Ogunsola, M. Bakir, J. Meindl
The design, fabrication, and demonstration of a high-density probe substrate (100 /spl mu/m pitch) for testing chips with electrical and optical input/output (I/O) interconnects are presented. The primary purpose of this substrate is to provide nondamaging, temporary interconnections between the device-under-test (DUT) and the automated test equipment (ATE) during wafer probing - an essential step in the system-on-chip (SOC) manufacturing process. Optical probing of an array of polymer pillar-based optical I/O interconnects is demonstrated for the first time, to the authors' knowledge.
介绍了一种高密度探针基板(100 /spl μ m /m间距)的设计、制造和演示，用于测试具有电和光输入/输出(I/O)互连的芯片。该基板的主要目的是在晶圆探测期间，在被测设备(DUT)和自动测试设备(ATE)之间提供非破坏性的临时互连，这是片上系统(SOC)制造过程中的重要步骤。据作者所知，首次展示了基于聚合物柱的光学I/O互连阵列的光学探测。
{"title":"High-density probe substrate for testing optical interconnects","authors":"H. Thacker, O. Ogunsola, M. Bakir, J. Meindl","doi":"10.1109/IITC.2005.1499962","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499962","url":null,"abstract":"The design, fabrication, and demonstration of a high-density probe substrate (100 /spl mu/m pitch) for testing chips with electrical and optical input/output (I/O) interconnects are presented. The primary purpose of this substrate is to provide nondamaging, temporary interconnections between the device-under-test (DUT) and the automated test equipment (ATE) during wafer probing - an essential step in the system-on-chip (SOC) manufacturing process. Optical probing of an array of polymer pillar-based optical I/O interconnects is demonstrated for the first time, to the authors' knowledge.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121813307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499975
T. Usui, H. Nasu, J. Koike, M. Wada, S. Takahashi, N. Shimizu, T. Nishikawa, A. Yoshimaru, H. Shibata
Copper (Cu) dual-damascene interconnects with self-formed MnSi/sub x/O/sub y/ barrier layer using a copper-manganese (Cu-Mn) alloy seed layer is successfully fabricated for the first time. No delamination is found in the chemical mechanical polishing process, probably because of better adhesion strength between the MnSi/sub x/O/sub y/ barrier and dielectric. More than 90% yield is obtained for a 1 million via chain. Microstructure analysis by transmission electron microscopy shows that an approximately 2 nm thick and continuous MnSi/sub x/O/sub y/ layer is formed at the interface between Cu and dielectric of the via and trench and there is no barrier at the via bottom. This via structure without the bottom barrier provides these essential advantages: reduced via resistance; significant via-electromigration lifetime improvement due to there being no flux divergence site at the via; excellent stress-induced voiding performance.
{"title":"Low resistive and highly reliable Cu dual-damascene interconnect technology using self-formed MnSi/sub x/O/sub y/ barrier layer","authors":"T. Usui, H. Nasu, J. Koike, M. Wada, S. Takahashi, N. Shimizu, T. Nishikawa, A. Yoshimaru, H. Shibata","doi":"10.1109/IITC.2005.1499975","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499975","url":null,"abstract":"Copper (Cu) dual-damascene interconnects with self-formed MnSi/sub x/O/sub y/ barrier layer using a copper-manganese (Cu-Mn) alloy seed layer is successfully fabricated for the first time. No delamination is found in the chemical mechanical polishing process, probably because of better adhesion strength between the MnSi/sub x/O/sub y/ barrier and dielectric. More than 90% yield is obtained for a 1 million via chain. Microstructure analysis by transmission electron microscopy shows that an approximately 2 nm thick and continuous MnSi/sub x/O/sub y/ layer is formed at the interface between Cu and dielectric of the via and trench and there is no barrier at the via bottom. This via structure without the bottom barrier provides these essential advantages: reduced via resistance; significant via-electromigration lifetime improvement due to there being no flux divergence site at the via; excellent stress-induced voiding performance.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121387011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499970
H. Cho, P. Kapur, K. Saraswat
The impact of technology scaling - in the form of transistor performance improvement and a higher demand in bit rate - on power dissipation of short distance electrical and optical interconnects is extensively quantified. We find that: 1) the transistor performance improvement has a similar impact on both types of interconnects, leaving critical length (length above which optical interconnects dissipate lower power) relatively unchanged; 2) the increase in bit rate significantly reduces critical length, favoring optics; 3) at the 32 nm technology node (and beyond) with its commensurate bandwidth requirement, optical interconnect becomes favorable for distances as low as 10 cm corresponding to inter-chip communication; 4) most critical factors in making optical interconnects favorable are reduction in coupling losses and optical detector capacitance.
{"title":"The impact of technology on power for high-speed electrical and optical interconnects","authors":"H. Cho, P. Kapur, K. Saraswat","doi":"10.1109/IITC.2005.1499970","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499970","url":null,"abstract":"The impact of technology scaling - in the form of transistor performance improvement and a higher demand in bit rate - on power dissipation of short distance electrical and optical interconnects is extensively quantified. We find that: 1) the transistor performance improvement has a similar impact on both types of interconnects, leaving critical length (length above which optical interconnects dissipate lower power) relatively unchanged; 2) the increase in bit rate significantly reduces critical length, favoring optics; 3) at the 32 nm technology node (and beyond) with its commensurate bandwidth requirement, optical interconnect becomes favorable for distances as low as 10 cm corresponding to inter-chip communication; 4) most critical factors in making optical interconnects favorable are reduction in coupling losses and optical detector capacitance.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"410 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133727969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499936
K. Takeda, T. Mine, T. Ishikawa, T. Imai, T. Fujiwara
The successful integration of a metal-insulator-metal (MIM) capacitor with an AlO/TaO/AlO stack is demonstrated. High capacitance density of more than 10 fF//spl mu/m/sup 2/ at 3.3 V and superior high-frequency characteristics are confirmed. The TDDB lifetime of the capacitor is strongly dependent on the electric field strength in the AlO layer, so the lifetime can be predicted by using the TDDB lifetime of a single-layer AlO capacitor. The capacitance voltage dependence of the AlO/TaO/AlO capacitor is dominated by the change in capacitance in the AlO layer. Thus, the voltage-linearity coefficients of single-layer AlO capacitors can be used to predict the coefficients of AlO/TaO/AlO capacitors.
{"title":"High-performance AlO-laminated TaO MIM capacitors for RF-IC applications: effects of the AlO layer on electrical characteristics","authors":"K. Takeda, T. Mine, T. Ishikawa, T. Imai, T. Fujiwara","doi":"10.1109/IITC.2005.1499936","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499936","url":null,"abstract":"The successful integration of a metal-insulator-metal (MIM) capacitor with an AlO/TaO/AlO stack is demonstrated. High capacitance density of more than 10 fF//spl mu/m/sup 2/ at 3.3 V and superior high-frequency characteristics are confirmed. The TDDB lifetime of the capacitor is strongly dependent on the electric field strength in the AlO layer, so the lifetime can be predicted by using the TDDB lifetime of a single-layer AlO capacitor. The capacitance voltage dependence of the AlO/TaO/AlO capacitor is dominated by the change in capacitance in the AlO layer. Thus, the voltage-linearity coefficients of single-layer AlO capacitors can be used to predict the coefficients of AlO/TaO/AlO capacitors.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124791153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499964
W. Tseng, C.M. Yang, W.J. Wu, C. Wang, J.C. Hu, C. Hsiung, Y.L. Lin, T. Bao, J.L. Yang, J. Shieh, C. Jeng, J.C. Lin, I.L. Huang, H. Chen, H. Lo, J. Wang, C. Yu, M. Liang
Supercritical CO/sub 2/ (SCCO/sub 2/) clean/modification performance on a 300 mm tool with promising physical, electrical and reliability results for 65 nm low k dual damascene is successfully demonstrated in this work. The process is optimized to remove post-ash residues and modify the dielectric film damaged by O/sub 2/ plasma ash. The low-k value dielectric (LKD) surface is modified from hydrophilic to hydrophobic by the SCCO/sub 2/ treatment. Dielectric constant measurements before and after treatment show effective modification only on porous CVD LKD films. Leakage performance with 55% reduction and capacitance performance with 11% reduction by the process with respect to the conventional process demonstrate the benefits. The process is compatible with the 8 layer scheme. Promising electro-migration (EM), stress migration (SM) performance and better time-dependent dielectric breakdown (TDDB) results indicate that the process is more robust than the conventional one for future interconnects. For 65 nm generation and beyond, SCCO/sub 2/, clean/modification is demonstrated as a promising solution for Cu/low k integration.
{"title":"Supercritical CO/sub 2/ clean with novel solution for 65 nm and beyond BEOL performance improvement","authors":"W. Tseng, C.M. Yang, W.J. Wu, C. Wang, J.C. Hu, C. Hsiung, Y.L. Lin, T. Bao, J.L. Yang, J. Shieh, C. Jeng, J.C. Lin, I.L. Huang, H. Chen, H. Lo, J. Wang, C. Yu, M. Liang","doi":"10.1109/IITC.2005.1499964","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499964","url":null,"abstract":"Supercritical CO/sub 2/ (SCCO/sub 2/) clean/modification performance on a 300 mm tool with promising physical, electrical and reliability results for 65 nm low k dual damascene is successfully demonstrated in this work. The process is optimized to remove post-ash residues and modify the dielectric film damaged by O/sub 2/ plasma ash. The low-k value dielectric (LKD) surface is modified from hydrophilic to hydrophobic by the SCCO/sub 2/ treatment. Dielectric constant measurements before and after treatment show effective modification only on porous CVD LKD films. Leakage performance with 55% reduction and capacitance performance with 11% reduction by the process with respect to the conventional process demonstrate the benefits. The process is compatible with the 8 layer scheme. Promising electro-migration (EM), stress migration (SM) performance and better time-dependent dielectric breakdown (TDDB) results indicate that the process is more robust than the conventional one for future interconnects. For 65 nm generation and beyond, SCCO/sub 2/, clean/modification is demonstrated as a promising solution for Cu/low k integration.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132928516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499930
Gang Huang, A. Naeemi, J. Meindl
Tuning down the signal voltage swing can be used to save energy for on-board interconnects. In this paper, we demonstrate that energy-per-bit, the energy to transfer a signal bit of data, could be minimized by selecting an optimum signal swing voltage for a given noise condition. The maximum energy saving and area overhead for this technique are derived. By using a proper power supply scheme, the energy-per-bit can be decreased by 2.5/spl times/ while consuming about 1.5/spl times/ more on-board wiring area.
{"title":"Minimizing energy-per-bit for on-board LC transmission lines","authors":"Gang Huang, A. Naeemi, J. Meindl","doi":"10.1109/IITC.2005.1499930","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499930","url":null,"abstract":"Tuning down the signal voltage swing can be used to save energy for on-board interconnects. In this paper, we demonstrate that energy-per-bit, the energy to transfer a signal bit of data, could be minimized by selecting an optimum signal swing voltage for a given noise condition. The maximum energy saving and area overhead for this technique are derived. By using a proper power supply scheme, the energy-per-bit can be decreased by 2.5/spl times/ while consuming about 1.5/spl times/ more on-board wiring area.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116243296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499955
B. Suh, Seungwook Choi, Y. Wee, Jung-Eun Lee, Junho Lee, Sun-jung Lee, Soo-Geun Lee, Hong-jae Shin, N. Lee, Ho-Kyu Kang, K. Suh
We have investigated TiZr alloy as a new Cu barrier material for low cost and high performance Cu/low-k interconnects. TiZrN ternary nitride was used as a Cu diffusion barrier and TiZr as an adhesion promotion layer. The issue of metal line resistance shift was suppressed using a novel 2-step annealing procedure. Multi-level Cu metal wiring integration was successfully carried out and the enhanced electrical performance of low via resistance with high via yield was obtained. Improved electromigration and stress-induced voiding resistances also have been demonstrated.
{"title":"Integration and reliability of a noble TiZr/TiZrN alloy barrier for Cu/low-k interconnects","authors":"B. Suh, Seungwook Choi, Y. Wee, Jung-Eun Lee, Junho Lee, Sun-jung Lee, Soo-Geun Lee, Hong-jae Shin, N. Lee, Ho-Kyu Kang, K. Suh","doi":"10.1109/IITC.2005.1499955","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499955","url":null,"abstract":"We have investigated TiZr alloy as a new Cu barrier material for low cost and high performance Cu/low-k interconnects. TiZrN ternary nitride was used as a Cu diffusion barrier and TiZr as an adhesion promotion layer. The issue of metal line resistance shift was suppressed using a novel 2-step annealing procedure. Multi-level Cu metal wiring integration was successfully carried out and the enhanced electrical performance of low via resistance with high via yield was obtained. Improved electromigration and stress-induced voiding resistances also have been demonstrated.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129351921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499991
D. Geraud, T. Magbitang, W. Volksen, E. Simonyi, R. Miller
Bridged oxycarbosilane monomers are excellent precursors for the formation of spin on porous low-k materials using sacrificial pore generators. The measured Young's modulus numbers for the as-synthesized thin films without any post porosity toughening are the highest by far of any that we have observed for porous films generated using the sacrificial porogen route. For a given dielectric constant, the Young's modulus of these oxycarbosilane films are 4-5 times higher than available organosilicates and at least 2 times higher than UV treated organosilicate materials.
{"title":"New spin-on oxycarbosilane low-k dielectric materials with exceptional mechanical properties","authors":"D. Geraud, T. Magbitang, W. Volksen, E. Simonyi, R. Miller","doi":"10.1109/IITC.2005.1499991","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499991","url":null,"abstract":"Bridged oxycarbosilane monomers are excellent precursors for the formation of spin on porous low-k materials using sacrificial pore generators. The measured Young's modulus numbers for the as-synthesized thin films without any post porosity toughening are the highest by far of any that we have observed for porous films generated using the sacrificial porogen route. For a given dielectric constant, the Young's modulus of these oxycarbosilane films are 4-5 times higher than available organosilicates and at least 2 times higher than UV treated organosilicate materials.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122789412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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