Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499949
E. Seok, K. O. Kenneth
The impact of on-chip metal interference structures, such as a power grid, local clock trees and data lines, on on-chip antenna performance has been investigated. A power grid significantly changes the input impedance and the phase of S/sub 12/ for an antenna pair, and reduces |S/sub 12/|. However, the addition of extra metal structures in the presence of a power grid has a much attenuated impact on the antenna characteristics. The reduction in |S/sub 12/| can be traded for increased predictability of antenna performance. Exploiting this observation, a set of design rules for increasing the predictability of on-chip antenna characteristics is proposed.
{"title":"Design rules for improving predictability of on-chip antenna characteristics in the presence of other metal structures","authors":"E. Seok, K. O. Kenneth","doi":"10.1109/IITC.2005.1499949","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499949","url":null,"abstract":"The impact of on-chip metal interference structures, such as a power grid, local clock trees and data lines, on on-chip antenna performance has been investigated. A power grid significantly changes the input impedance and the phase of S/sub 12/ for an antenna pair, and reduces |S/sub 12/|. However, the addition of extra metal structures in the presence of a power grid has a much attenuated impact on the antenna characteristics. The reduction in |S/sub 12/| can be traded for increased predictability of antenna performance. Exploiting this observation, a set of design rules for increasing the predictability of on-chip antenna characteristics is proposed.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134582356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499931
A. Triantafyllou, A. Farcy, P. Benech, F. Ndagijimana, J. Torres, O. Exshaw, C. Tinella, O. Richard, C. Raynaud
Alternative interconnect systems were recently proposed in order to overcome the problems of time delay, surface, and power consumption related to global traditional ones. The feasibility of wireless intra chip interconnects is studied, by focusing on system transmission properties and parasitic effects between integrated antennas and nearby interconnects. Technological processes were considered in order to deduce innovative design concepts that combine improved transmitted power and reduced interferences between antenna and nearby components on a SOI substrate using CMOS 120 nm technology. As a result, it is shown that moving away locally surrounding metallization greatly improves transmission and that crosstalk effects are of the same order with those of conventional interconnect systems. Wireless interconnect performances and compatibility with standard BEOL are demonstrated.
{"title":"High transmission performance integrated antennas on SOI substrate for VLSI wireless interconnects","authors":"A. Triantafyllou, A. Farcy, P. Benech, F. Ndagijimana, J. Torres, O. Exshaw, C. Tinella, O. Richard, C. Raynaud","doi":"10.1109/IITC.2005.1499931","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499931","url":null,"abstract":"Alternative interconnect systems were recently proposed in order to overcome the problems of time delay, surface, and power consumption related to global traditional ones. The feasibility of wireless intra chip interconnects is studied, by focusing on system transmission properties and parasitic effects between integrated antennas and nearby interconnects. Technological processes were considered in order to deduce innovative design concepts that combine improved transmitted power and reduced interferences between antenna and nearby components on a SOI substrate using CMOS 120 nm technology. As a result, it is shown that moving away locally surrounding metallization greatly improves transmission and that crosstalk effects are of the same order with those of conventional interconnect systems. Wireless interconnect performances and compatibility with standard BEOL are demonstrated.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130538494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499976
V. H. Nguyen, P. Christie, A. Heringa, A. Kumar, R. Ng
The paper presents a method for assessing the impact of interconnects on dynamic system level performance. The method is applied to the analysis of the impact of interconnect parasitic resistance and capacitance on the performance of different circuit types at the 45-nm technology node. It is observed that the interconnect capacitance dominates circuit performance at short interconnect lengths. The interconnect resistance influences low-power (high-speed) circuit speed only for critical wire lengths longer than 360 /spl mu/m (180 /spl mu/m). Within the investigated interconnect lengths, the interconnect resistance has virtually no impact on the switching energy of the test circuit. The results indicate that for low-power circuits, the high interconnect resistance is not a serious issue at the 45-nm technology node.
{"title":"An analysis of the effect of wire resistance on circuit level performance at the 45-nm technology node","authors":"V. H. Nguyen, P. Christie, A. Heringa, A. Kumar, R. Ng","doi":"10.1109/IITC.2005.1499976","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499976","url":null,"abstract":"The paper presents a method for assessing the impact of interconnects on dynamic system level performance. The method is applied to the analysis of the impact of interconnect parasitic resistance and capacitance on the performance of different circuit types at the 45-nm technology node. It is observed that the interconnect capacitance dominates circuit performance at short interconnect lengths. The interconnect resistance influences low-power (high-speed) circuit speed only for critical wire lengths longer than 360 /spl mu/m (180 /spl mu/m). Within the investigated interconnect lengths, the interconnect resistance has virtually no impact on the switching energy of the test circuit. The results indicate that for low-power circuits, the high interconnect resistance is not a serious issue at the 45-nm technology node.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127598716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499963
Y. Matsui, G. Minamihaba, Y. Tateyama, K. Takahata, A. Shigeta, T. Nishioka, H. Yano, N. Hayasaka
In order to reduce the focus error for the stacked mask process (SMAP) used in Cu/low-k dual damascene (DD) interconnect, a planarization technology of the under layer film by CMP was developed. Photo-resist was used for the under layer film. CMP slurry with resin abrasive was investigated for the photo-resist planarization. The slurry showed better planarity, lower risk to particle residue, and high selectivity to SiO/sub 2/ film. These advantages are attributable to the effects of the particle size and the material characteristics similar to photo-resist. Furthermore, it was found that it is effective for a higher CMP rate to turn the platen and head with lower rotational speed. Using the photo-resist planarization technology, application to via first DD process was investigated. It became clear that focus error reduction of 0.1 /spl mu/m is confirmed compared with conventional SMAP. The depth of focus (DOF) margin loss due to resist thickness variation caused by via density variation is completely canceled by photo-resist planarization.
{"title":"Focus error reduction by photo-resist planarization in via-first dual damascene process","authors":"Y. Matsui, G. Minamihaba, Y. Tateyama, K. Takahata, A. Shigeta, T. Nishioka, H. Yano, N. Hayasaka","doi":"10.1109/IITC.2005.1499963","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499963","url":null,"abstract":"In order to reduce the focus error for the stacked mask process (SMAP) used in Cu/low-k dual damascene (DD) interconnect, a planarization technology of the under layer film by CMP was developed. Photo-resist was used for the under layer film. CMP slurry with resin abrasive was investigated for the photo-resist planarization. The slurry showed better planarity, lower risk to particle residue, and high selectivity to SiO/sub 2/ film. These advantages are attributable to the effects of the particle size and the material characteristics similar to photo-resist. Furthermore, it was found that it is effective for a higher CMP rate to turn the platen and head with lower rotational speed. Using the photo-resist planarization technology, application to via first DD process was investigated. It became clear that focus error reduction of 0.1 /spl mu/m is confirmed compared with conventional SMAP. The depth of focus (DOF) margin loss due to resist thickness variation caused by via density variation is completely canceled by photo-resist planarization.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121166735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499906
I. Sugiura, Y. Nakata, N. Misawa, S. Otsuka, N. Nishikawa, Y. Iba, F. Sugimoto, Y. Setta, H. Sakai, Y. Mizushima, Y. Kotaka, C. Uchibori, T. Suzuki, H. Kitada, Y. Koura, K. Nakano, T. Karasawa, Y. Ohkura, H. Watatani, M. Sato, S. Nakai, M. Nakaishi, N. Shimizu, S. Fukuyama, M. Miyajima, T. Nakamura, E. Yano, K. Watanabe
45 nm-node multilevel Cu interconnects with porous-ultra-low-k have successfully been integrated. Key features to realize 45 nm-node interconnects are as follows: 1) porous ultra-low-k material NCS (nano-clustering silica) has been applied to both wire-level and via-level dielectrics (what we call full-NCS structure), and its sufficient robustness has been demonstrated; 2) 70-nm vias have been formed by high-NA 193 nm lithography with fine-tuned model-based OPC and multi-hard-mask dual-damascene process - more than 90% yields of 1 M via chains have been obtained; 3) good TDDB (time-dependent dielectric breakdown) characteristics of 70 nm wire spacing filled with NCS has been achieved. Because it is considered that the applied-voltage (Vdd) of a 45 nm-node technology will be almost the same as that of the previous technology, the dielectrics have to endure the high electrical field. NCS in Cu wiring has excellent insulating properties without any pore sealing materials which cause either the k/sub eff/ value or actual wire width to be worse.
{"title":"45 nm-node BEOL integration featuring porous-ultra-low-k/Cu multilevel interconnects","authors":"I. Sugiura, Y. Nakata, N. Misawa, S. Otsuka, N. Nishikawa, Y. Iba, F. Sugimoto, Y. Setta, H. Sakai, Y. Mizushima, Y. Kotaka, C. Uchibori, T. Suzuki, H. Kitada, Y. Koura, K. Nakano, T. Karasawa, Y. Ohkura, H. Watatani, M. Sato, S. Nakai, M. Nakaishi, N. Shimizu, S. Fukuyama, M. Miyajima, T. Nakamura, E. Yano, K. Watanabe","doi":"10.1109/IITC.2005.1499906","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499906","url":null,"abstract":"45 nm-node multilevel Cu interconnects with porous-ultra-low-k have successfully been integrated. Key features to realize 45 nm-node interconnects are as follows: 1) porous ultra-low-k material NCS (nano-clustering silica) has been applied to both wire-level and via-level dielectrics (what we call full-NCS structure), and its sufficient robustness has been demonstrated; 2) 70-nm vias have been formed by high-NA 193 nm lithography with fine-tuned model-based OPC and multi-hard-mask dual-damascene process - more than 90% yields of 1 M via chains have been obtained; 3) good TDDB (time-dependent dielectric breakdown) characteristics of 70 nm wire spacing filled with NCS has been achieved. Because it is considered that the applied-voltage (Vdd) of a 45 nm-node technology will be almost the same as that of the previous technology, the dielectrics have to endure the high electrical field. NCS in Cu wiring has excellent insulating properties without any pore sealing materials which cause either the k/sub eff/ value or actual wire width to be worse.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121350795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499913
H. Struyf, D. Hendrickx, J. Van Olmen, F. Iacopi, O. Richard, Y. Travaly, M. Van Hove, W. Boullart, S. Vanhaelemeersch
Etch and strip plasma-induced damage is well-known to make the integration of sensitive low-k dielectrics in damascene schemes cumbersome. In this paper, three metal hardmask-based single-damascene patterning approaches are compared. EFTEM analysis and integrated k-value extraction show that the use of a metal hardmask-based scheme with optimized plasma chemistries and etch/strip sequencing results in very low damage to the SiOC(H) low-k dielectric.
{"title":"Low-damage damascene patterning of SiOC(H) low-k dielectrics","authors":"H. Struyf, D. Hendrickx, J. Van Olmen, F. Iacopi, O. Richard, Y. Travaly, M. Van Hove, W. Boullart, S. Vanhaelemeersch","doi":"10.1109/IITC.2005.1499913","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499913","url":null,"abstract":"Etch and strip plasma-induced damage is well-known to make the integration of sensitive low-k dielectrics in damascene schemes cumbersome. In this paper, three metal hardmask-based single-damascene patterning approaches are compared. EFTEM analysis and integrated k-value extraction show that the use of a metal hardmask-based scheme with optimized plasma chemistries and etch/strip sequencing results in very low damage to the SiOC(H) low-k dielectric.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130149633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499935
M. Shimada, Y. Otsuka, T. Harada, A. Tsutsumida, K. Inukai, H. Hashimoto, S. Ogawa
2D distribution of dielectric constants or damage in porous low-k trench structures have been characterized with nm-order space resolution by valence electron energy loss spectroscopy (V-EELS) combined with scanning transmission electron microscopy (STEM) for the first time. Kramers-Kronig analysis (KKA) was carried out to estimate dielectric constants from V-EELS spectra. The results derived from the STEM/V-EELS technique showed that the dielectric constant at a side wall was higher than that at a central region in a trench patterned porous poly-methylsilsequioxane (MSQ) film. It is shown that the STEM/V-EELS technique combined with KKA is a unique technique to investigate changes in local structures and dielectric constants of low-k films, caused by such as plasma treatments, in fine structures.
{"title":"2-dimensional distribution of dielectric constants in patterned low-k structures by a nm-probe STEM/valence EELS (V-EELS) technique","authors":"M. Shimada, Y. Otsuka, T. Harada, A. Tsutsumida, K. Inukai, H. Hashimoto, S. Ogawa","doi":"10.1109/IITC.2005.1499935","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499935","url":null,"abstract":"2D distribution of dielectric constants or damage in porous low-k trench structures have been characterized with nm-order space resolution by valence electron energy loss spectroscopy (V-EELS) combined with scanning transmission electron microscopy (STEM) for the first time. Kramers-Kronig analysis (KKA) was carried out to estimate dielectric constants from V-EELS spectra. The results derived from the STEM/V-EELS technique showed that the dielectric constant at a side wall was higher than that at a central region in a trench patterned porous poly-methylsilsequioxane (MSQ) film. It is shown that the STEM/V-EELS technique combined with KKA is a unique technique to investigate changes in local structures and dielectric constants of low-k films, caused by such as plasma treatments, in fine structures.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131406578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499942
D. Ney, X. Federspiel, V. Girault, O. Thomas, P. Gergaud
Electromigration in interconnects is a major reliability concern for integrated circuits, which leads to aggressive design rules. These rules can be lightened by taking advantage of the Blech effect in extrapolated lifetimes. In the present paper is reported the critical product (jL)/sub c/ for copper-oxide interconnects measured at 250/spl deg/C, 300/spl deg/C and 350/spl deg/C from electron-migration lifetime tests. The existence of this threshold product implies an increase of n values from Black's model with decreasing (current density-line length) products. This increase significantly changes the extrapolated lifetime at operating conditions.
{"title":"Electromigration threshold in copper interconnects and consequences on lifetime extrapolations","authors":"D. Ney, X. Federspiel, V. Girault, O. Thomas, P. Gergaud","doi":"10.1109/IITC.2005.1499942","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499942","url":null,"abstract":"Electromigration in interconnects is a major reliability concern for integrated circuits, which leads to aggressive design rules. These rules can be lightened by taking advantage of the Blech effect in extrapolated lifetimes. In the present paper is reported the critical product (jL)/sub c/ for copper-oxide interconnects measured at 250/spl deg/C, 300/spl deg/C and 350/spl deg/C from electron-migration lifetime tests. The existence of this threshold product implies an increase of n values from Black's model with decreasing (current density-line length) products. This increase significantly changes the extrapolated lifetime at operating conditions.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134188891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499995
M. Nihei, D. Kondo, A. Kawabata, S. Sato, H. Shioya, M. Sakaue, T. Iwai, M. Ohfuti, Y. Awano
We have succeeded in lowering the resistance of multi-walled carbon nanotube (MWNT) vias, using parallel channel conduction of each tube's inner shells. By optimizing the structure of the interface between MWNTs and Ti bottom contact layers, we could obtain a via resistance of 0.7 /spl Omega/ for a 2-/spl mu/m-diameter via consisting of about 1000 MWNTs. The corresponding resistance of about 0.7 k/spl Omega/ per MWNT indicates that most of the inner shells contribute to carrier conduction as an additional channel. The total resistance of the CNT vias that we fabricated is in the same order of magnitude as the theoretical value of W plugs and one order of magnitude higher than the theoretical value of Cu vias.
{"title":"Low-resistance multi-walled carbon nanotube vias with parallel channel conduction of inner shells [IC interconnect applications]","authors":"M. Nihei, D. Kondo, A. Kawabata, S. Sato, H. Shioya, M. Sakaue, T. Iwai, M. Ohfuti, Y. Awano","doi":"10.1109/IITC.2005.1499995","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499995","url":null,"abstract":"We have succeeded in lowering the resistance of multi-walled carbon nanotube (MWNT) vias, using parallel channel conduction of each tube's inner shells. By optimizing the structure of the interface between MWNTs and Ti bottom contact layers, we could obtain a via resistance of 0.7 /spl Omega/ for a 2-/spl mu/m-diameter via consisting of about 1000 MWNTs. The corresponding resistance of about 0.7 k/spl Omega/ per MWNT indicates that most of the inner shells contribute to carrier conduction as an additional channel. The total resistance of the CNT vias that we fabricated is in the same order of magnitude as the theoretical value of W plugs and one order of magnitude higher than the theoretical value of Cu vias.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134025720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499925
N. Tajima, T. Hamada, T. Ohno, K. Yoneda, N. Kobayashi, T. Hasaka, M. Fnoue
The microstructure of PECVD carbon-doped oxide (SiOCH) film has been obtained for the first time by using a theoretical method to create molecular models of amorphous polymers with cross-links. This method generates atomic coordinates of chemically possible SiOCH film structures from a given atomic composition. We have confirmed that this method creates reasonable SiOCH film structures that explain the experimental results of IR spectrum, dielectric constant, and Young's modulus. Consequently, this method gives us a guideline for decreasing the density of PECVD SiOCH films having acceptable mechanical properties for interconnect applications.
{"title":"First-principle molecular model of PECVD SiOCH film for the mechanical and dielectric property investigation","authors":"N. Tajima, T. Hamada, T. Ohno, K. Yoneda, N. Kobayashi, T. Hasaka, M. Fnoue","doi":"10.1109/IITC.2005.1499925","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499925","url":null,"abstract":"The microstructure of PECVD carbon-doped oxide (SiOCH) film has been obtained for the first time by using a theoretical method to create molecular models of amorphous polymers with cross-links. This method generates atomic coordinates of chemically possible SiOCH film structures from a given atomic composition. We have confirmed that this method creates reasonable SiOCH film structures that explain the experimental results of IR spectrum, dielectric constant, and Young's modulus. Consequently, this method gives us a guideline for decreasing the density of PECVD SiOCH films having acceptable mechanical properties for interconnect applications.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122318976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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