Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499994
K. Wang, A. Khitun, A. Flood
In the nanoelectronics era with ever smaller devices and higher densities, there are challenges of signal transmission and information communications via interconnects. We examine the interconnect issues for both charge-based and spin-based information systems. For charge-based systems, since there are substantial activities in optical interconnect, this paper focuses on other concepts and approaches. Self-assembled molecular wires, carbon nanotubes/nanowires and virus engineered metallic wires can be used for interconnects. The use of new nano-architectures such as cellular automata, which use mostly nearest neighbors, make the use of self-assembled interconnects even more attractive. These techniques may be applied readily to molecular devices. Spin-based devices offer a new opportunity for low power, high functional throughput applications. We analyze the use of spin waves for information transmission buses referred to as spin wave bus. By introducing these novel circuits built on the spin-based devices and spin wave interconnect, we anticipate enhanced logic functionality. The challenges and issues are discussed.
{"title":"Interconnects for nanoelectronics","authors":"K. Wang, A. Khitun, A. Flood","doi":"10.1109/IITC.2005.1499994","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499994","url":null,"abstract":"In the nanoelectronics era with ever smaller devices and higher densities, there are challenges of signal transmission and information communications via interconnects. We examine the interconnect issues for both charge-based and spin-based information systems. For charge-based systems, since there are substantial activities in optical interconnect, this paper focuses on other concepts and approaches. Self-assembled molecular wires, carbon nanotubes/nanowires and virus engineered metallic wires can be used for interconnects. The use of new nano-architectures such as cellular automata, which use mostly nearest neighbors, make the use of self-assembled interconnects even more attractive. These techniques may be applied readily to molecular devices. Spin-based devices offer a new opportunity for low power, high functional throughput applications. We analyze the use of spin waves for information transmission buses referred to as spin wave bus. By introducing these novel circuits built on the spin-based devices and spin wave interconnect, we anticipate enhanced logic functionality. The challenges and issues are discussed.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128027463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499959
J. de Mussy, C. Bruynsereade, Z. Tokeil, G. Beyer, K. Maex
In the present work, we demonstrate a novel selective process for airgap formation at the interconnect sidewalls for single damascene interconnects. The proposed single step scheme is simpler than the currently existing airgap approaches. This process has been shown to be scalable down to spacings of 60 nm and allows capacitance drops in the range of 6%-39% with only a marginal increase in leakage current.
{"title":"Novel selective sidewall airgap process [single damascene interconnects]","authors":"J. de Mussy, C. Bruynsereade, Z. Tokeil, G. Beyer, K. Maex","doi":"10.1109/IITC.2005.1499959","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499959","url":null,"abstract":"In the present work, we demonstrate a novel selective process for airgap formation at the interconnect sidewalls for single damascene interconnects. The proposed single step scheme is simpler than the currently existing airgap approaches. This process has been shown to be scalable down to spacings of 60 nm and allows capacitance drops in the range of 6%-39% with only a marginal increase in leakage current.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116894209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IITC.2005.1499920
C. C. Ko, C.H. Lin, L.P. Li, K.C. Lin, Y.C. Lu, S. Jeng, C. Yu, M. Liang
A porous k=2.5 low-k material (LK2.5) with its pore size distribution and mechanical properties comparable to the ones of k=3.0 low-k materials (LK3.0) was developed by a novel quasi-porogen approach for 65 nm BEOL Cu dual damascene (DD) interconnects. As compared to the Cu/LK3.0 DD, the Cu/LK2.5 DD, processed using similar etching and ashing processes and chemistries, showed a 14% line-to-line (L-L) capacitance reduction at S=0.1 /spl mu/m. Other physical, electrical and reliability results show that the Cu/LK2.5 DD is comparable to the Cu/LK3.0 DD with no degradations commonly associated with conventional porous LK2.5s formed using porogens, such as peeling or LK recess in CMP, k increase or trench bottom roughening in patterning, high L-L leakage, low L-L Vbd or low SM resistance. Further process extendibility studies revealed that k<2.0 is also achievable using this quasi-porogen approach which strongly enables its applicability to current and future Cu/LK BEOL technologies.
{"title":"Using a low-k material with k=2.5 formed by a novel quasi-porogen approach for 65 nm Cu/LK interconnects","authors":"C. C. Ko, C.H. Lin, L.P. Li, K.C. Lin, Y.C. Lu, S. Jeng, C. Yu, M. Liang","doi":"10.1109/IITC.2005.1499920","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499920","url":null,"abstract":"A porous k=2.5 low-k material (LK2.5) with its pore size distribution and mechanical properties comparable to the ones of k=3.0 low-k materials (LK3.0) was developed by a novel quasi-porogen approach for 65 nm BEOL Cu dual damascene (DD) interconnects. As compared to the Cu/LK3.0 DD, the Cu/LK2.5 DD, processed using similar etching and ashing processes and chemistries, showed a 14% line-to-line (L-L) capacitance reduction at S=0.1 /spl mu/m. Other physical, electrical and reliability results show that the Cu/LK2.5 DD is comparable to the Cu/LK3.0 DD with no degradations commonly associated with conventional porous LK2.5s formed using porogens, such as peeling or LK recess in CMP, k increase or trench bottom roughening in patterning, high L-L leakage, low L-L Vbd or low SM resistance. Further process extendibility studies revealed that k<2.0 is also achievable using this quasi-porogen approach which strongly enables its applicability to current and future Cu/LK BEOL technologies.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124063890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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