Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499924
T. Tsui, A. J. Griffin, J. Jacques, R. Fields, A. Mckerrow, R. Kraft
A model that predicts channel-crack propagation behavior in silica-based low-/spl kappa/ dielectrics (low-/spl kappa/) was developed. A solid-mechanics theory that governs fracture behavior was used to obtain low-/spl kappa/ material constants. These fracture parameters were used to predict crack behaviors in five low-/spl kappa/ films with distinct elastic moduli. The model developed demonstrates that crack propagation rate is extremely sensitive to modulus, especially when the material is compliant.
{"title":"Effects of elastic modulus on the fracture behavior of low-dielectric constant films","authors":"T. Tsui, A. J. Griffin, J. Jacques, R. Fields, A. Mckerrow, R. Kraft","doi":"10.1109/IITC.2005.1499924","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499924","url":null,"abstract":"A model that predicts channel-crack propagation behavior in silica-based low-/spl kappa/ dielectrics (low-/spl kappa/) was developed. A solid-mechanics theory that governs fracture behavior was used to obtain low-/spl kappa/ material constants. These fracture parameters were used to predict crack behaviors in five low-/spl kappa/ films with distinct elastic moduli. The model developed demonstrates that crack propagation rate is extremely sensitive to modulus, especially when the material is compliant.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123680683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499984
P. Leduc, M. Savoye, S. Maitrejean, D. Scevola, V. Jousseaume, G. Passemard
In-situ friction characterization during chemical-mechanical polishing (CMP) was investigated to understand delamination mechanisms of a porous ultra low-k (ULK)/Cu stack. By quantifying the delaminated area within the wafer, it was shown that adhesion failure is driven by the work done against the CMP-induced friction force, and is correlated to the adhesion strength of the weakest interface. A low-stress CMP was successfully achieved on a first level of ULK/Cu interconnects having a low adhesion SiC/ULK interface (Gc=1.3 J/m/sup 2/) and a porous dielectric material with low mechanical properties (Young's modulus E=3.5 GPa, hardness H=0.7 GPa).
{"title":"Understanding CMP-induced delamination in ultra low-k/Cu integration","authors":"P. Leduc, M. Savoye, S. Maitrejean, D. Scevola, V. Jousseaume, G. Passemard","doi":"10.1109/IITC.2005.1499984","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499984","url":null,"abstract":"In-situ friction characterization during chemical-mechanical polishing (CMP) was investigated to understand delamination mechanisms of a porous ultra low-k (ULK)/Cu stack. By quantifying the delaminated area within the wafer, it was shown that adhesion failure is driven by the work done against the CMP-induced friction force, and is correlated to the adhesion strength of the weakest interface. A low-stress CMP was successfully achieved on a first level of ULK/Cu interconnects having a low adhesion SiC/ULK interface (Gc=1.3 J/m/sup 2/) and a porous dielectric material with low mechanical properties (Young's modulus E=3.5 GPa, hardness H=0.7 GPa).","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123400362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499982
S. Kondo, S. Tominaga, A. Namiki, K. Yamada, D. Abe, K. Fukaya, M. Shimada, N. Kobayashi
We developed a novel electro-chemical mechanical planarization (e-CMP) method that uses a conductive carbon pad for polishing 300-mm wafers. More than one hundred electro-cells were fabricated into the carbon pad, and the method resolved issues with conventional e-CMP, such as scratching caused by metal electrodes, copper residues, and process complexity of cathode regeneration. By using an e-CMP process followed by TaN-CMP, porous low-k/Cu interconnects were successfully fabricated.
{"title":"Novel electro-chemical mechanical planarization using carbon polishing pad to achieve robust ultra low-k/Cu integration","authors":"S. Kondo, S. Tominaga, A. Namiki, K. Yamada, D. Abe, K. Fukaya, M. Shimada, N. Kobayashi","doi":"10.1109/IITC.2005.1499982","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499982","url":null,"abstract":"We developed a novel electro-chemical mechanical planarization (e-CMP) method that uses a conductive carbon pad for polishing 300-mm wafers. More than one hundred electro-cells were fabricated into the carbon pad, and the method resolved issues with conventional e-CMP, such as scratching caused by metal electrodes, copper residues, and process complexity of cathode regeneration. By using an e-CMP process followed by TaN-CMP, porous low-k/Cu interconnects were successfully fabricated.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128794409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499985
M. Kodera, S. Uekusa, S. Kakinuma, Y. Saijo, A. Fukunaga, M. Tsujimura, G. Pezzotti
Engineering of the residual stress fields related to the backend process of LSI devices with Cu interconnects is required together with the adoption of low-k materials that have quite low Young's modulus. We measured the nano-scale residual stresses stored within interlayer dielectric (ILD) films according to a cathodoluminescence piezospectroscopic technique. We confirmed that stresses in ILD could be successfully detected with less than 50 nm resolution and that a higher chemical mechanical polishing (CMP) downward pressure led to a shift toward the tensile side of the residual stress field stored in the ILD film.
{"title":"Effect of CMP downward pressure on nano-scale residual stresses in dielectric films with Cu interconnects assessed by cathodoluminescence spectroscopy","authors":"M. Kodera, S. Uekusa, S. Kakinuma, Y. Saijo, A. Fukunaga, M. Tsujimura, G. Pezzotti","doi":"10.1109/IITC.2005.1499985","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499985","url":null,"abstract":"Engineering of the residual stress fields related to the backend process of LSI devices with Cu interconnects is required together with the adoption of low-k materials that have quite low Young's modulus. We measured the nano-scale residual stresses stored within interlayer dielectric (ILD) films according to a cathodoluminescence piezospectroscopic technique. We confirmed that stresses in ILD could be successfully detected with less than 50 nm resolution and that a higher chemical mechanical polishing (CMP) downward pressure led to a shift toward the tensile side of the residual stress field stored in the ILD film.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121227329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499919
S. Chikaki, A. Shimoyama, R. Yagi, T. Yoshino, T. Ono, A. Ishikawa, N. Fujii, N. Hata, T. Nakayama, K. Kohmura, H. Tanaka, T. Goto, J. Kawahara, Y. Sonoda, H. Matsuo, Y. Seino, S. Takada, N. Kunimi, Y. Uchida, S. Hishiya, Y. Shishida, K. Kinoshita, T. Kikkawa
Self-assembled porous-silica ultra low-k films (k=2.1) were integrated for 45-32 nm technology node low-k/Cu dual damascene interconnects. Porosity and pore size distributions of the low-k film were controlled by controlling the concentration of the surfactant so that a tight distribution of dielectric constant was achieved. Self-assembled porous silica low-k/Cu damascene interconnects were successfully formed by developing dry etching, low pressure CMP, post CMP cleaning, Cu electroplating solution as well as a TMCTS process recovery treatment. The feasibility of low-k/Cu damascene was confirmed. Electrical characteristics showed a potential capability of the self-assembled porous-silica low-k film for the 45-32 nm technology node.
{"title":"Hybrid low-k/Cu dual damascene process for 45-32 nm technology node using self-assembled porous-silica ultra low-k films","authors":"S. Chikaki, A. Shimoyama, R. Yagi, T. Yoshino, T. Ono, A. Ishikawa, N. Fujii, N. Hata, T. Nakayama, K. Kohmura, H. Tanaka, T. Goto, J. Kawahara, Y. Sonoda, H. Matsuo, Y. Seino, S. Takada, N. Kunimi, Y. Uchida, S. Hishiya, Y. Shishida, K. Kinoshita, T. Kikkawa","doi":"10.1109/IITC.2005.1499919","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499919","url":null,"abstract":"Self-assembled porous-silica ultra low-k films (k=2.1) were integrated for 45-32 nm technology node low-k/Cu dual damascene interconnects. Porosity and pore size distributions of the low-k film were controlled by controlling the concentration of the surfactant so that a tight distribution of dielectric constant was achieved. Self-assembled porous silica low-k/Cu damascene interconnects were successfully formed by developing dry etching, low pressure CMP, post CMP cleaning, Cu electroplating solution as well as a TMCTS process recovery treatment. The feasibility of low-k/Cu damascene was confirmed. Electrical characteristics showed a potential capability of the self-assembled porous-silica low-k film for the 45-32 nm technology node.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126819053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499948
B. Blampey, B. Fléchet, A. Farcy, U. Bermond, O. Cueto, J. Torres, G. Angénieux
The placement and size of square dummies degrade electrical performances mainly in terms of interconnect capacitance and propagation delay time. Electrical parameters for an isolated interconnect are obtained in a whole spectrum (up to 40 GHz) by electromagnetic modeling. Parasitic effects could be traduced by a fictitious increase of the relative permittivity k-value of inter-level dielectric cutting down performances of porous ULK integration for future 65 and 45 nm technology nodes. The capacitive effect of dummies on the interconnect test structure with a dielectric at k=2.7 was found, in some situations, to be equivalent to that obtained with a dielectric at k=3.2 without dummies. The capacitive effect of dummy distribution was also shown to be generally inhomogeneous, dramatically depending on dummy size and local interconnect design. However, an optimal size of dummies could be determined, leading to an homogeneous capacitive degradation effect, independent of the local interconnect dummy surrounding situation.
{"title":"Capacitive impacts of dummies on interconnect propagation performances for integrated circuits of the 65 nm node and below","authors":"B. Blampey, B. Fléchet, A. Farcy, U. Bermond, O. Cueto, J. Torres, G. Angénieux","doi":"10.1109/IITC.2005.1499948","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499948","url":null,"abstract":"The placement and size of square dummies degrade electrical performances mainly in terms of interconnect capacitance and propagation delay time. Electrical parameters for an isolated interconnect are obtained in a whole spectrum (up to 40 GHz) by electromagnetic modeling. Parasitic effects could be traduced by a fictitious increase of the relative permittivity k-value of inter-level dielectric cutting down performances of porous ULK integration for future 65 and 45 nm technology nodes. The capacitive effect of dummies on the interconnect test structure with a dielectric at k=2.7 was found, in some situations, to be equivalent to that obtained with a dielectric at k=3.2 without dummies. The capacitive effect of dummy distribution was also shown to be generally inhomogeneous, dramatically depending on dummy size and local interconnect design. However, an optimal size of dummies could be determined, leading to an homogeneous capacitive degradation effect, independent of the local interconnect dummy surrounding situation.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133001548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499997
R. Daamen, G. Verheijden, P. Bancken, T. Vandeweyer, J. Michelon, V. Nguyễn Hoàng, R. Hoofman, M. Gallagher
First promising results including reliability and electromigration of an extendable air gap integration approach obtaining mechanically stable air cavities at the inter-metal dielectric (IMD) level are presented. Extraction of the effective dielectric constant (k/sub eff/) is demonstrated to be 1.45 for non-passivated single damascene structures. Using 45 nm node specifications and the proposed integration scheme, two metal levels are simulated showing a k/sub eff/ of less than 2.0 after full integration, fulfilling multiple future interconnect node requirements.
{"title":"Air gap integration for the 45nm node and beyond","authors":"R. Daamen, G. Verheijden, P. Bancken, T. Vandeweyer, J. Michelon, V. Nguyễn Hoàng, R. Hoofman, M. Gallagher","doi":"10.1109/IITC.2005.1499997","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499997","url":null,"abstract":"First promising results including reliability and electromigration of an extendable air gap integration approach obtaining mechanically stable air cavities at the inter-metal dielectric (IMD) level are presented. Extraction of the effective dielectric constant (k/sub eff/) is demonstrated to be 1.45 for non-passivated single damascene structures. Using 45 nm node specifications and the proposed integration scheme, two metal levels are simulated showing a k/sub eff/ of less than 2.0 after full integration, fulfilling multiple future interconnect node requirements.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114912075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499978
R. Sarvari, A. Naeemi, R. Venkatesan, J. Meindl
The impact of surface and grain boundary scattering on the design of multi-level interconnect networks and their latency distributions is reported. For the 18-nm technology node (year 2018), it is shown that, despite more than 4/spl times/ increase in resistivity of copper for minimum size interconnects, the increase in the number of metal levels is negligible (less than 6.7%), and interconnects that will be affected most are so short that their impact on the chip performance is inconsequential.
{"title":"Impact of size effects on the resistivity of copper wires and consequently the design and performance of metal interconnect networks","authors":"R. Sarvari, A. Naeemi, R. Venkatesan, J. Meindl","doi":"10.1109/IITC.2005.1499978","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499978","url":null,"abstract":"The impact of surface and grain boundary scattering on the design of multi-level interconnect networks and their latency distributions is reported. For the 18-nm technology node (year 2018), it is shown that, despite more than 4/spl times/ increase in resistivity of copper for minimum size interconnects, the increase in the number of metal levels is negligible (less than 6.7%), and interconnects that will be affected most are so short that their impact on the chip performance is inconsequential.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116322551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499950
N. Konishi, Y. Yamada, J. Noguchi, T. Jimbo, O. Inoue
The relationship between the TDDB (time-dependent dielectric breakdown) reliability and defects in the Cu CMP (chemical-mechanical polishing) process, such as corrosions, scratches and pittings, was investigated using Cu/SiOC interconnects. Cu corrosions generate at edges of wires and this results in the TDDB degradation. Scratches on the SiOC surface also degrade the TDDB lifetime even if other defects are removed. The slurry without the BTA solutions causes not only pittings, but also Cu dissolution. In this condition, some dissolved Cu atoms remain on the SiOC surface between adjacent Cu wires. This also leads to the TDDB degradation. It is essential to prevent corrosions, scratches and pittings to improve the TDDB reliability.
{"title":"Influence of CMP process on defects in SiOC films and TDDB reliability","authors":"N. Konishi, Y. Yamada, J. Noguchi, T. Jimbo, O. Inoue","doi":"10.1109/IITC.2005.1499950","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499950","url":null,"abstract":"The relationship between the TDDB (time-dependent dielectric breakdown) reliability and defects in the Cu CMP (chemical-mechanical polishing) process, such as corrosions, scratches and pittings, was investigated using Cu/SiOC interconnects. Cu corrosions generate at edges of wires and this results in the TDDB degradation. Scratches on the SiOC surface also degrade the TDDB lifetime even if other defects are removed. The slurry without the BTA solutions causes not only pittings, but also Cu dissolution. In this condition, some dissolved Cu atoms remain on the SiOC surface between adjacent Cu wires. This also leads to the TDDB degradation. It is essential to prevent corrosions, scratches and pittings to improve the TDDB reliability.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127528154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499917
D. M. Gage, Kyunghoon Kim, C. Litteken, R. Dauskardt
The four-point bend method has become an established metrology for quantitatively examining interfacial fracture energies of thin film multi-layers. However, despite the widespread use of the technique, relatively little is known about how four-point measurements are affected by loading point friction and variations in readily adjustable loading parameters. In this study, we demonstrate that four-point measurements can be sensitive to applied loading geometry and factors that affect the rate of steady state debond propagation. These effects can be experimentally significant, particularly for fracture energy measurements above /spl sim/5 J/m/sup 2/. We show that this behavior is due to a combination of Coulomb friction and stress corrosion effects. Good practice testing guidelines are suggested to systematically improve accuracy and consistency of four-point data.
{"title":"Effects of friction and loading parameters on four-point bend adhesion measurements of low-k thin film interconnect structures","authors":"D. M. Gage, Kyunghoon Kim, C. Litteken, R. Dauskardt","doi":"10.1109/IITC.2005.1499917","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499917","url":null,"abstract":"The four-point bend method has become an established metrology for quantitatively examining interfacial fracture energies of thin film multi-layers. However, despite the widespread use of the technique, relatively little is known about how four-point measurements are affected by loading point friction and variations in readily adjustable loading parameters. In this study, we demonstrate that four-point measurements can be sensitive to applied loading geometry and factors that affect the rate of steady state debond propagation. These effects can be experimentally significant, particularly for fracture energy measurements above /spl sim/5 J/m/sup 2/. We show that this behavior is due to a combination of Coulomb friction and stress corrosion effects. Good practice testing guidelines are suggested to systematically improve accuracy and consistency of four-point data.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129881720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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