Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499921
Y. Su, J. Shieh, B. Perng, S. Jang, M. Liang
We have developed an integrated approach for Cu/hybrid low k interconnects. Implementation of this method to 65/45 nm dual damascene was performed using a hybrid film stack consisting of porous SiLK (p-SiLK, k=2.2) and CVD SiOC (k=3.0). The damage to p-SiLK in plasma clean is prevented by pore sealing and an effective k value as low as 2.6 was extracted from the bias temperature stress (BTS) experiments. From BTS, it is found that Frenkel-Poole (FP) emission dominates the leakage mechanism in p-SiLK. The proposed hybrid approach demonstrates /spl sim/21% reduction in RC product and shows excellent electrical and reliability (EM and SM) performance comparable to the conventional Cu/SiOC (k=3.0) damascene.
{"title":"Reliability and conduction mechanism study on organic ultra low-k (k=2.2) for 65/45 nm hybrid Cu damascene technology","authors":"Y. Su, J. Shieh, B. Perng, S. Jang, M. Liang","doi":"10.1109/IITC.2005.1499921","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499921","url":null,"abstract":"We have developed an integrated approach for Cu/hybrid low k interconnects. Implementation of this method to 65/45 nm dual damascene was performed using a hybrid film stack consisting of porous SiLK (p-SiLK, k=2.2) and CVD SiOC (k=3.0). The damage to p-SiLK in plasma clean is prevented by pore sealing and an effective k value as low as 2.6 was extracted from the bias temperature stress (BTS) experiments. From BTS, it is found that Frenkel-Poole (FP) emission dominates the leakage mechanism in p-SiLK. The proposed hybrid approach demonstrates /spl sim/21% reduction in RC product and shows excellent electrical and reliability (EM and SM) performance comparable to the conventional Cu/SiOC (k=3.0) damascene.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114487369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499941
C.H. Shih, S.W. Chou, C. Lin, T. Ko, H.W. Su, C. Wu, M. Tsai, W. Shue, C. Yu, M. Liang
In this work, the design criteria of ECP additives on Cu BEOL reliability are revealed. By varying the ECP additive structures and concentrations, we demonstrate how gap filling performance and impurity level of the bulk copper can influence the electromigration lifetime and stress induced void (SIV) formation. It was found that the impurity in the grain boundary could act as an effective vacancy diffusion barrier to inhibit SIV formation. However, ECP additive conditions that produce highly impure Cu was found to increase the gap filling pits on top of the sub-micron features that would reduce the electromigration (EM) lifetime performance. By proper design of ECP additives, high impurity incorporation in the wide metal line without gap filling pit formation can be achieved. The stress SIV formation was inhibited with excellent EM resistance.
{"title":"Design of ECP additive for 65 nm-node technology Cu BEOL reliability","authors":"C.H. Shih, S.W. Chou, C. Lin, T. Ko, H.W. Su, C. Wu, M. Tsai, W. Shue, C. Yu, M. Liang","doi":"10.1109/IITC.2005.1499941","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499941","url":null,"abstract":"In this work, the design criteria of ECP additives on Cu BEOL reliability are revealed. By varying the ECP additive structures and concentrations, we demonstrate how gap filling performance and impurity level of the bulk copper can influence the electromigration lifetime and stress induced void (SIV) formation. It was found that the impurity in the grain boundary could act as an effective vacancy diffusion barrier to inhibit SIV formation. However, ECP additive conditions that produce highly impure Cu was found to increase the gap filling pits on top of the sub-micron features that would reduce the electromigration (EM) lifetime performance. By proper design of ECP additives, high impurity incorporation in the wide metal line without gap filling pit formation can be achieved. The stress SIV formation was inhibited with excellent EM resistance.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133826216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499902
C. Goldberg, S. Downey, V. Fiori, R. Fox, K. Hess, O. Hinsinger, A. Humbert, J. Jacquemin, S. Lee, J. Lhuillier, S. Orain, S. Pozder, L. Proença, F. Quercia, E. Sabouret, T. Tran, T. Uehling
Mechanical reliability is widely recognized as the primary obstacle to productionization of porous low-k materials. The combination of weak bulk and interfacial properties with increasingly complex geometries poses a considerable challenge at the 65-nm node. The final solution must be sufficiently robust so as to ensure compatibility with multiple substrate types, interconnect configurations and packages. In this work, material engineering, modeling, design rule tailoring, and assembly optimization are employed to achieve required assembly reliability for both wirebond and flip-chip packages, for both bulk and SOI substrates.
{"title":"Integration of a mechanically reliable 65-nm node technology for low-k and ULK interconnects with various substrate and package types","authors":"C. Goldberg, S. Downey, V. Fiori, R. Fox, K. Hess, O. Hinsinger, A. Humbert, J. Jacquemin, S. Lee, J. Lhuillier, S. Orain, S. Pozder, L. Proença, F. Quercia, E. Sabouret, T. Tran, T. Uehling","doi":"10.1109/IITC.2005.1499902","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499902","url":null,"abstract":"Mechanical reliability is widely recognized as the primary obstacle to productionization of porous low-k materials. The combination of weak bulk and interfacial properties with increasingly complex geometries poses a considerable challenge at the 65-nm node. The final solution must be sufficiently robust so as to ensure compatibility with multiple substrate types, interconnect configurations and packages. In this work, material engineering, modeling, design rule tailoring, and assembly optimization are employed to achieve required assembly reliability for both wirebond and flip-chip packages, for both bulk and SOI substrates.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"447 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116756020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499915
M. Grégoire, S. Kordic, M. Ignat, X. Federspiel, P. Vannier, S. Courtas
Stress voiding (SV) in Cu vias and lines is investigated on 300 mm wafers after storage at temperatures ranging from 175/spl deg/C to 400/spl deg/C. Sensitivity to SV in lines decreases with metal pattern density. Microstructural analysis of Cu lines shows that voids are not only found at grain boundaries, but also within the grains, indicating bulk and/or surface diffusion of vacancies. Via resistance increase well above 10% is observed. Both via and line SV is observed below and above zero-stress temperature, indicating two mechanisms: vacancy diffusion in combination with tensile stress, and Cu densification under compressive stress. SEM and pattern recognition observations on Cu lines are presented. Line void volume distribution is lognormal, while the distribution of the increase in via resistances is bimodal.
{"title":"New stress voiding observations in Cu interconnects","authors":"M. Grégoire, S. Kordic, M. Ignat, X. Federspiel, P. Vannier, S. Courtas","doi":"10.1109/IITC.2005.1499915","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499915","url":null,"abstract":"Stress voiding (SV) in Cu vias and lines is investigated on 300 mm wafers after storage at temperatures ranging from 175/spl deg/C to 400/spl deg/C. Sensitivity to SV in lines decreases with metal pattern density. Microstructural analysis of Cu lines shows that voids are not only found at grain boundaries, but also within the grains, indicating bulk and/or surface diffusion of vacancies. Via resistance increase well above 10% is observed. Both via and line SV is observed below and above zero-stress temperature, indicating two mechanisms: vacancy diffusion in combination with tensile stress, and Cu densification under compressive stress. SEM and pattern recognition observations on Cu lines are presented. Line void volume distribution is lognormal, while the distribution of the increase in via resistances is bimodal.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124129677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499910
A. Ishii, S. Matsumoto, T. Hattori, S. Suzuki, S. Isono, A. Iwasaki, K. Tomita, K. Hashimoto, S. Tawa, T. Furusawa, D. Kodama, S. Ogawa, S. Suzumura, M. Tsutsue, K. Goto, K. Kobayashi, H. Ohshita, M. Hamada, N. Amoh, H. Okamura, K. Yonekura, T. Hamatani, T. Kobayshi, K. Tsukamoto, M. Matsuura
Interface engineering technologies are developed for highly-reliable 65 nm-node Cu/low-k interconnect integration using a ULK dielectric (k=2.6) in a hybrid ILD structure. For electromigration (EM) reliability, the mechanical integrity at the SiOC/SiC(N,O) interface exposed on the via sidewalls is found to be critical. For TDDB reliability, reduction in Cu-containing defects at the SiC(N,O)/SiOC interface at the top of the metal line is critical. By optimizing these interfaces, the EM and the TDDB lifetimes are significantly improved.
{"title":"Interface engineering for highly-reliable 65 nm-node Cu/ULK (k=2.6) interconnect integration","authors":"A. Ishii, S. Matsumoto, T. Hattori, S. Suzuki, S. Isono, A. Iwasaki, K. Tomita, K. Hashimoto, S. Tawa, T. Furusawa, D. Kodama, S. Ogawa, S. Suzumura, M. Tsutsue, K. Goto, K. Kobayashi, H. Ohshita, M. Hamada, N. Amoh, H. Okamura, K. Yonekura, T. Hamatani, T. Kobayshi, K. Tsukamoto, M. Matsuura","doi":"10.1109/IITC.2005.1499910","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499910","url":null,"abstract":"Interface engineering technologies are developed for highly-reliable 65 nm-node Cu/low-k interconnect integration using a ULK dielectric (k=2.6) in a hybrid ILD structure. For electromigration (EM) reliability, the mechanical integrity at the SiOC/SiC(N,O) interface exposed on the via sidewalls is found to be critical. For TDDB reliability, reduction in Cu-containing defects at the SiC(N,O)/SiOC interface at the top of the metal line is critical. By optimizing these interfaces, the EM and the TDDB lifetimes are significantly improved.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121458278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499956
Jong Won Hong, Jong Myeong Lee, K. Choi, Youngsu Chung, Sang woo Lee, G. Choi, Sung Tae Kim, U. Chung, Tae Moon, B. Ryu
CVD-TaN thin films derived from a new noble precursor, tert-amylimidotrisdim-ethylamidotantalum (TAIMATA), for the diffusion barrier in Cu interconnects were studied. The effects of CVD-TaN on dual damascene interconnect (DDI) for Cu metallization were investigated on SiOC (k=2.9) dielectrics with 4 K via chains. The via resistances were measured as a function of TaN thickness (10/spl sim/45 /spl Aring/), compared to PVD TaN. Diffusion barrier properties (bias temperature stress) and delamination length (adhesion test) were studied as a function of TaN thickness. Ar and H/sub 2/ post-plasma after CVD-TaN was introduced to improve the properties of the barrier materials. After applying post-plasma, the via resistances and delamination length of CVD-TaN were investigated and compared to those without post-plasma.
{"title":"Evaluation of adhesion and barrier properties for CVD-TaN on dual damascene copper interconnects","authors":"Jong Won Hong, Jong Myeong Lee, K. Choi, Youngsu Chung, Sang woo Lee, G. Choi, Sung Tae Kim, U. Chung, Tae Moon, B. Ryu","doi":"10.1109/IITC.2005.1499956","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499956","url":null,"abstract":"CVD-TaN thin films derived from a new noble precursor, tert-amylimidotrisdim-ethylamidotantalum (TAIMATA), for the diffusion barrier in Cu interconnects were studied. The effects of CVD-TaN on dual damascene interconnect (DDI) for Cu metallization were investigated on SiOC (k=2.9) dielectrics with 4 K via chains. The via resistances were measured as a function of TaN thickness (10/spl sim/45 /spl Aring/), compared to PVD TaN. Diffusion barrier properties (bias temperature stress) and delamination length (adhesion test) were studied as a function of TaN thickness. Ar and H/sub 2/ post-plasma after CVD-TaN was introduced to improve the properties of the barrier materials. After applying post-plasma, the via resistances and delamination length of CVD-TaN were investigated and compared to those without post-plasma.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122469686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499977
Makoto Honda, K. Tsutsumi, H. Harakawa, A. Nomachi, K. Murakami, K. Ooya, T. Kudou, T. Nagamatsu, H. Ezawa
Nickel silicide (NiSi/sub x/) is being considered as a replacement for the currently used silicides. A native oxide film on the nickel silicide surface causes high contact resistance. The cleaning technology for removal of the oxide film on NiSi/sub x/ is a critical issue for 65 nm generation CMOS devices. The effect of a chemical dry treatment prior to contact metallization was studied. It was confirmed that the chemical dry treatment is effective for obtaining low stable contact resistance, and is a key technology for the high yield manufacture of CMOS devices.
{"title":"Chemical dry cleaning technology for reliable 65 nm CMOS contact to NiSi/sub x/","authors":"Makoto Honda, K. Tsutsumi, H. Harakawa, A. Nomachi, K. Murakami, K. Ooya, T. Kudou, T. Nagamatsu, H. Ezawa","doi":"10.1109/IITC.2005.1499977","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499977","url":null,"abstract":"Nickel silicide (NiSi/sub x/) is being considered as a replacement for the currently used silicides. A native oxide film on the nickel silicide surface causes high contact resistance. The cleaning technology for removal of the oxide film on NiSi/sub x/ is a critical issue for 65 nm generation CMOS devices. The effect of a chemical dry treatment prior to contact metallization was studied. It was confirmed that the chemical dry treatment is effective for obtaining low stable contact resistance, and is a key technology for the high yield manufacture of CMOS devices.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123141736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499957
K. Jenkins, C. Patel
The inductance of through-wafer vias in a new via technology in silicon is reported. The technology uses copper filled vias with 70 /spl mu/m diameters. Measurements by network analyzer up to 40 GHz show that the vias have an inductance of approximately 0.15 pH//spl mu/m, the smallest reported value for vias in silicon.
报道了一种新型硅晶圆通孔技术的电感。该技术采用直径为70 μ m /spl μ m的铜填充过孔。通过高达40 GHz的网络分析仪测量表明，该过孔的电感约为0.15 pH//spl mu/m，这是硅过孔的最小值。
{"title":"Copper-filled through wafer vias with very low inductance","authors":"K. Jenkins, C. Patel","doi":"10.1109/IITC.2005.1499957","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499957","url":null,"abstract":"The inductance of through-wafer vias in a new via technology in silicon is reported. The technology uses copper filled vias with 70 /spl mu/m diameters. Measurements by network analyzer up to 40 GHz show that the vias have an inductance of approximately 0.15 pH//spl mu/m, the smallest reported value for vias in silicon.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131132045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499898
M. Brillouet
As the dimensions scale down, the importance of the interconnections in a circuit is growing tremendously. This paper addresses the shifting challenges of connecting millions of gates in a functional pattern and interfacing it with the outside world. The optimization of this network in terms of connectivity, integration density, performance and manufacturability is a major task where breakthroughs are expected from a synergetic development of the technology and of the design methodology, with more exploratory concepts taken from the biological world.
{"title":"Shifting challenges in the integrated interconnection systems","authors":"M. Brillouet","doi":"10.1109/IITC.2005.1499898","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499898","url":null,"abstract":"As the dimensions scale down, the importance of the interconnections in a circuit is growing tremendously. This paper addresses the shifting challenges of connecting millions of gates in a functional pattern and interfacing it with the outside world. The optimization of this network in terms of connectivity, integration density, performance and manufacturability is a major task where breakthroughs are expected from a synergetic development of the technology and of the design methodology, with more exploratory concepts taken from the biological world.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125613567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-06DOI: 10.1109/IITC.2005.1499960
Q. Ngo, A. Cassell, Jun Li, S. Krishnan, M. Meyyappan, C. Yang
Recent advances in the growth of carbon nanofibers (CNF) using plasma-enhanced chemical vapor deposition (PECVD) allows for the potential use of these novel structures in backend-of-line (BEOL) interconnect applications. Reliability data is presented for vertically aligned CNF array structures as well as temperature-dependent electrical conductance measurements of both CNF arrays and CNF heterojunction structures. CNF arrays are presented as a possible new via material, while CNF heterojunctions present a promising new architecture for diode array and memory applications.
{"title":"Vertically aligned carbon nanofiber arrays for on-chip interconnect applications","authors":"Q. Ngo, A. Cassell, Jun Li, S. Krishnan, M. Meyyappan, C. Yang","doi":"10.1109/IITC.2005.1499960","DOIUrl":"https://doi.org/10.1109/IITC.2005.1499960","url":null,"abstract":"Recent advances in the growth of carbon nanofibers (CNF) using plasma-enhanced chemical vapor deposition (PECVD) allows for the potential use of these novel structures in backend-of-line (BEOL) interconnect applications. Reliability data is presented for vertically aligned CNF array structures as well as temperature-dependent electrical conductance measurements of both CNF arrays and CNF heterojunction structures. CNF arrays are presented as a possible new via material, while CNF heterojunctions present a promising new architecture for diode array and memory applications.","PeriodicalId":156268,"journal":{"name":"Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.","volume":"582 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123210999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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