Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013155
Ruiqi Lim, Ramona B. Damalerio, J. Vw, Ming-Yuan Cheng
Smart catheters integrated with multiple sensors measure and provide surgeons with physiological data such as temperature, heart rate, pH value, blood flow or pressure. This feedback information enabled surgeons to better monitor and evaluate a patient's condition during the procedure. Thus, surgeons will be able to make accurate medical intervention and lead to a better health outcome for the patient. However, there is a growing trend to employ smaller catheters for certain procedures. Challenges faced by smart catheters include limited space for sensors integration which promotes the initiative to minimize sensor packaging. This led to secondary challenge of radiopaque visibility and biocompatibility for such sensor package. In this work, radiopaque visibility studies have been conducted and a minimum tungsten thickness of 100um is required for a sample size of 1.8mm (L) x 0.7mm (W). Additional radiopaque ink can be used as an alternative for die attach adhesive. The sensor package includes a polyimide-nitinol based flexible circuitry substrate with silicon-based sensor chip, radiopaque material (tungsten) and epoxy encapsulant has been verified to be biocompatible and suitable for catheter-based application.
集成了多个传感器的智能导管测量并为外科医生提供生理数据，如温度、心率、pH值、血流量或压力。这些反馈信息使外科医生能够在手术过程中更好地监测和评估患者的病情。因此，外科医生将能够做出准确的医疗干预，并为患者带来更好的健康结果。然而，在某些手术中使用更小的导管的趋势正在增长。智能导尿管面临的挑战包括传感器集成空间有限，这推动了最小化传感器封装的倡议。这导致了这种传感器封装的不透射线可见性和生物相容性的次要挑战。在这项工作中，进行了不透射线可见性研究，对于1.8mm (L) x 0.7mm (W)的样品尺寸，钨的最小厚度要求为100um。额外的不透射线油墨可以用作模贴粘合剂的替代品。传感器封装包括基于聚酰亚胺-镍钛诺的柔性电路衬底，带有硅基传感器芯片，不透射线材料(钨)和环氧密封剂，已被证实具有生物相容性，适合导管应用。
{"title":"Evaluation of Radiopacity and Biocompatibility of Sensor Package for Smart Catheter Application","authors":"Ruiqi Lim, Ramona B. Damalerio, J. Vw, Ming-Yuan Cheng","doi":"10.1109/EPTC56328.2022.10013155","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013155","url":null,"abstract":"Smart catheters integrated with multiple sensors measure and provide surgeons with physiological data such as temperature, heart rate, pH value, blood flow or pressure. This feedback information enabled surgeons to better monitor and evaluate a patient's condition during the procedure. Thus, surgeons will be able to make accurate medical intervention and lead to a better health outcome for the patient. However, there is a growing trend to employ smaller catheters for certain procedures. Challenges faced by smart catheters include limited space for sensors integration which promotes the initiative to minimize sensor packaging. This led to secondary challenge of radiopaque visibility and biocompatibility for such sensor package. In this work, radiopaque visibility studies have been conducted and a minimum tungsten thickness of 100um is required for a sample size of 1.8mm (L) x 0.7mm (W). Additional radiopaque ink can be used as an alternative for die attach adhesive. The sensor package includes a polyimide-nitinol based flexible circuitry substrate with silicon-based sensor chip, radiopaque material (tungsten) and epoxy encapsulant has been verified to be biocompatible and suitable for catheter-based application.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126948135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013262
Cliff Sandstrom, Benedict A. San Jose, Jen-Kuang Fang, Ping-Feng Yang, Sheng Feng-Huang, Ping-Ching Shen
The semiconductor industry is turning to advanced heterogeneous integration to achieve significant system-level performance improvements. The industry is looking to replace current packaging technologies such as flip-chip ball grid array (FC-BGA) and wafer-level chip scale packaging (WLCSP) with fanout wafer level packaging (FOWLP) due to its ability to allow for higher density interconnects in a smaller form factor with lower cost and better electrical performance. The combination of smaller devices and the desire for thousands of chip-to-chip connections are driving an unprecedented need for shrinking the device bond pad pitch. Currently running at volumes in the millions per day on 300mm round format, Deca's M-Series™ fan-out technology and Adaptive Patterning® (AP) are being scaled up to 600mm for production at ASE. The extension of the first and introduction of our second-generation M -Series & AP technologies will be explored as they deliver ultra-high-density 20µm area array bond pad pitch through a unique design-during-manufacturing process using Laser Direct Imaging (LDI) with 250nm digital patterns.
{"title":"Mask-less Laser Direct Imaging & Adaptive Patterning Solution for Fan-Out Heterogeneous Integration on 600mm","authors":"Cliff Sandstrom, Benedict A. San Jose, Jen-Kuang Fang, Ping-Feng Yang, Sheng Feng-Huang, Ping-Ching Shen","doi":"10.1109/EPTC56328.2022.10013262","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013262","url":null,"abstract":"The semiconductor industry is turning to advanced heterogeneous integration to achieve significant system-level performance improvements. The industry is looking to replace current packaging technologies such as flip-chip ball grid array (FC-BGA) and wafer-level chip scale packaging (WLCSP) with fanout wafer level packaging (FOWLP) due to its ability to allow for higher density interconnects in a smaller form factor with lower cost and better electrical performance. The combination of smaller devices and the desire for thousands of chip-to-chip connections are driving an unprecedented need for shrinking the device bond pad pitch. Currently running at volumes in the millions per day on 300mm round format, Deca's M-Series™ fan-out technology and Adaptive Patterning® (AP) are being scaled up to 600mm for production at ASE. The extension of the first and introduction of our second-generation M -Series & AP technologies will be explored as they deliver ultra-high-density 20µm area array bond pad pitch through a unique design-during-manufacturing process using Laser Direct Imaging (LDI) with 250nm digital patterns.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130238830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013129
Eleazar Q. Novenario, Senen O. Lachica, Rex Dao Ayan
Silicon wafers are becoming thinner with layers of metallization of different chemistries and material properties added on the saw lane and at the backside of the wafer. Such structures are imposing novel challenges to sawing process application. To satisfy the separation requirements of both material layers on top and backside, wafer dicing employs step cut process to control the induced stress by proportional sharing of loads between the two individual blades, namely, ZI(bladel) and Z2(blade2). The cut width or kerf of the second blade (Z2) should be relatively narrower than Z1 's kerf to avoid double cutting characterized by the condition when Z2 is touching the kerf's wall made by Z1. The difference in kerfs width of these two blades is called kerf delta AMP defect Pareto showed that the top chip on silicon dice has always been in the top 3 defects in Wafer Saw Process. The monthly reject rate showed this defect is posting high reject contribution to the defined business target for year 2021 operation. By structural problem-solving approach, root causes were identified. The primary corrective action of increasing the blade's kerf delta to 1.55: 1 (Z1:Z2 thickness ratio) in combination with the optimized settings, of 50/50 (%Z1/%Z2 cut depth), top chipping defects had significantly reduced and managed within the target rejection rate.
{"title":"Z1 AND Z2 Kerf Delta: A Key Blade Parameter for Top Chipping Control","authors":"Eleazar Q. Novenario, Senen O. Lachica, Rex Dao Ayan","doi":"10.1109/EPTC56328.2022.10013129","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013129","url":null,"abstract":"Silicon wafers are becoming thinner with layers of metallization of different chemistries and material properties added on the saw lane and at the backside of the wafer. Such structures are imposing novel challenges to sawing process application. To satisfy the separation requirements of both material layers on top and backside, wafer dicing employs step cut process to control the induced stress by proportional sharing of loads between the two individual blades, namely, ZI(bladel) and Z2(blade2). The cut width or kerf of the second blade (Z2) should be relatively narrower than Z1 's kerf to avoid double cutting characterized by the condition when Z2 is touching the kerf's wall made by Z1. The difference in kerfs width of these two blades is called kerf delta AMP defect Pareto showed that the top chip on silicon dice has always been in the top 3 defects in Wafer Saw Process. The monthly reject rate showed this defect is posting high reject contribution to the defined business target for year 2021 operation. By structural problem-solving approach, root causes were identified. The primary corrective action of increasing the blade's kerf delta to 1.55: 1 (Z1:Z2 thickness ratio) in combination with the optimized settings, of 50/50 (%Z1/%Z2 cut depth), top chipping defects had significantly reduced and managed within the target rejection rate.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128826084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013188
Daniel Ismael Cereno, C. Choong, Hsiao Hsiang-Yao
To realize continuous miniaturization, improved performance and efficiency while minimizing cost of emerging new and highly functional electronic devices, the semiconductor industry continues to develop packaging solutions and rely on the advancement and methods of interconnecting and integrating several parts into one highly mobile and robust device [1]. FOWLP and WLCSP packaging plays a role in a shift of getting more mobility from handheld smartphones devices to autonomous driven cars or air drone utility vehicles of the future. This packaging technology requires sensitive devices to be encapsulated to protect its components from the environment such as injection molding or with a laminated resin applied on front and backside. With the device encapsulation, there is a need for the devices to be connected between packages or be stacked from another device to be functional. Thru mold via technology had emerged where laser drilling on mold surface is carried out for via formation on underlying thick Cu interconnects from FOWLP packaging standpoint which usually uses high filler size materials to overcome interlayer's mechanical characteristics mismatch [2]. Other chip scale packaging on the other hand requires further compacting such that fine filler resins are employed acting as dielectric between interconnects and land on thinner aluminum pads. This fine formation of vias however is where the challenge enters primarily on how to create smaller via size features without damaging the thin aluminum so as not to compromise reliability of under bump metallization. This paper will show an optimization results of laser drilling process parameters for various filler size insulating resin, the effects of UV laser process on Aluminum pad damage or metal penetration, and dimension of the formed vias. Laser drilling is based on a 365nm UV laser source focused into the surface of the resin material on top of the underlying aluminum pad to ablate and turn it into gaseous by-products with minimal heat conversion to achieve highly efficient via formation process. A DOE was performed on the etching rate of the encapsulating material and determine the energy density requirement to efficiently remove the bulk of resin and leave minimal or no residue without damage or puncture on the underlying aluminum pad surface. The experiments also encompass the optimization of laser beam size, selection of drilling method and sequential steps that is required to form the desired via diameter. Ultimately, the desired no damage with minimal residue on underlying aluminum pad to form a contact can be achieve which is important for excellent electrical connectivity, efficient current flow, and reliability of the package. This forms the laser via machining process can integrate well on fan-out panel based embedded packaging technology and provide solution to enable laser via machine to create via for traces routing as it is still not common in the market.
{"title":"Process Development of Via Formation by Laser Drilling on Insulating Resin","authors":"Daniel Ismael Cereno, C. Choong, Hsiao Hsiang-Yao","doi":"10.1109/EPTC56328.2022.10013188","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013188","url":null,"abstract":"To realize continuous miniaturization, improved performance and efficiency while minimizing cost of emerging new and highly functional electronic devices, the semiconductor industry continues to develop packaging solutions and rely on the advancement and methods of interconnecting and integrating several parts into one highly mobile and robust device [1]. FOWLP and WLCSP packaging plays a role in a shift of getting more mobility from handheld smartphones devices to autonomous driven cars or air drone utility vehicles of the future. This packaging technology requires sensitive devices to be encapsulated to protect its components from the environment such as injection molding or with a laminated resin applied on front and backside. With the device encapsulation, there is a need for the devices to be connected between packages or be stacked from another device to be functional. Thru mold via technology had emerged where laser drilling on mold surface is carried out for via formation on underlying thick Cu interconnects from FOWLP packaging standpoint which usually uses high filler size materials to overcome interlayer's mechanical characteristics mismatch [2]. Other chip scale packaging on the other hand requires further compacting such that fine filler resins are employed acting as dielectric between interconnects and land on thinner aluminum pads. This fine formation of vias however is where the challenge enters primarily on how to create smaller via size features without damaging the thin aluminum so as not to compromise reliability of under bump metallization. This paper will show an optimization results of laser drilling process parameters for various filler size insulating resin, the effects of UV laser process on Aluminum pad damage or metal penetration, and dimension of the formed vias. Laser drilling is based on a 365nm UV laser source focused into the surface of the resin material on top of the underlying aluminum pad to ablate and turn it into gaseous by-products with minimal heat conversion to achieve highly efficient via formation process. A DOE was performed on the etching rate of the encapsulating material and determine the energy density requirement to efficiently remove the bulk of resin and leave minimal or no residue without damage or puncture on the underlying aluminum pad surface. The experiments also encompass the optimization of laser beam size, selection of drilling method and sequential steps that is required to form the desired via diameter. Ultimately, the desired no damage with minimal residue on underlying aluminum pad to form a contact can be achieve which is important for excellent electrical connectivity, efficient current flow, and reliability of the package. This forms the laser via machining process can integrate well on fan-out panel based embedded packaging technology and provide solution to enable laser via machine to create via for traces routing as it is still not common in the market.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125508568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013168
Jong Eun Park, Misun Hwang, Chan Jin Park, Burhan Ali, Sunki Cho, JungHyun Kim, C. Kim
In this paper, we will compare the use of various optical inspection technologies to find critical defects in IC substrates during the manufacturing process with the goal of improving yield. We will also introduce a unique inspection technology for the detection of critical defects which are difficult to identify using traditional technologies.
{"title":"Inspection Solutions for Advanced IC Substrate Process Control","authors":"Jong Eun Park, Misun Hwang, Chan Jin Park, Burhan Ali, Sunki Cho, JungHyun Kim, C. Kim","doi":"10.1109/EPTC56328.2022.10013168","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013168","url":null,"abstract":"In this paper, we will compare the use of various optical inspection technologies to find critical defects in IC substrates during the manufacturing process with the goal of improving yield. We will also introduce a unique inspection technology for the detection of critical defects which are difficult to identify using traditional technologies.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121614613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013125
Lau Boon Long, D. Ho, Lim Teck Guan, Sun Mei, Hsiao Hsiang Yao
Double molding fan-out wafer level packaging process integration flow was introduced in this paper to achieve miniature scale Antenna-in-package AiP at low transition loss with long distance communication and beam steering capabilities. The size of this package as 12mm × 12mm × 0.40mm. The main components of this package are three redistribution layers (RDL), two mold-compound layers and a through mold via (TMV) structure at 100um depth. A bare silicon chip at 4mm × 4mm was embedded into mold compound layers, with copper metal and polyimide dielectric RDL layers built to interconnect the PCB and the opposite metal ground via Metal TMV structure. Copper antenna was fabricated on top of thick, second-molded-compound layer via IME technology on double molding FOWLP process architectures. This paper demonstrated a double molding fan-out approach to build RDL layers on first-mold reconfigured silicon surfaces; and second mold as the objectives of filling up TMV structures and dielectric interlayer between RF metal and antenna metal layers. The major process challenges and the respective solutions were discussed. The development of critical process parameters was identified to ensure good process specifications and uniformity.
{"title":"Double Mold Fan-Out Wafer Level Packaging for AiP Applications","authors":"Lau Boon Long, D. Ho, Lim Teck Guan, Sun Mei, Hsiao Hsiang Yao","doi":"10.1109/EPTC56328.2022.10013125","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013125","url":null,"abstract":"Double molding fan-out wafer level packaging process integration flow was introduced in this paper to achieve miniature scale Antenna-in-package AiP at low transition loss with long distance communication and beam steering capabilities. The size of this package as 12mm × 12mm × 0.40mm. The main components of this package are three redistribution layers (RDL), two mold-compound layers and a through mold via (TMV) structure at 100um depth. A bare silicon chip at 4mm × 4mm was embedded into mold compound layers, with copper metal and polyimide dielectric RDL layers built to interconnect the PCB and the opposite metal ground via Metal TMV structure. Copper antenna was fabricated on top of thick, second-molded-compound layer via IME technology on double molding FOWLP process architectures. This paper demonstrated a double molding fan-out approach to build RDL layers on first-mold reconfigured silicon surfaces; and second mold as the objectives of filling up TMV structures and dielectric interlayer between RF metal and antenna metal layers. The major process challenges and the respective solutions were discussed. The development of critical process parameters was identified to ensure good process specifications and uniformity.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126052676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013177
C. Dehon, Laura Lecomte, Jonathan Cetier
Contamination of electronic assemblies can occur at any process steps and can be of different natures such as oxides, organic residues, or dusts. Those contaminations could reduce the reliability of PCBA through time. At the same time, miniaturization and new component typologies require ever-higher performances with ever-increasing functionality. Moreover, the industry is looking for solutions to improve cleaning efficiency, reduce costs and limit environmental impact. Thus, developing cleaning solutions become a challenge to guarantee the reliability of the electronics assemblies. This paper introduces a new technology of cleaning solution developed to be compatible in several processes. After a short description of co-solvent and aqueous process, the cleaning results concerning the new technology are shared. The cleaning efficiency is evaluated using IPC standards: visual inspection under microscope, ionic contamination, and SIR test. Surface tension is also measured. Then, a scoring method based on the GHS labelling system and REACH regulation is used to evaluate the environmental impact of this innovative cleaner technology. As a conclusion, the new cleaning solution does show promising results. For aqueous processes, this improvement allows to lower the cleaning time and/or the cleaning temperature. For co-solvent processes, the cleaning performance is similar with an improvement of the safety and the environmental footprint.
{"title":"An Efficient and Innovative Cleaning Solution with Low Environmental Impact","authors":"C. Dehon, Laura Lecomte, Jonathan Cetier","doi":"10.1109/EPTC56328.2022.10013177","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013177","url":null,"abstract":"Contamination of electronic assemblies can occur at any process steps and can be of different natures such as oxides, organic residues, or dusts. Those contaminations could reduce the reliability of PCBA through time. At the same time, miniaturization and new component typologies require ever-higher performances with ever-increasing functionality. Moreover, the industry is looking for solutions to improve cleaning efficiency, reduce costs and limit environmental impact. Thus, developing cleaning solutions become a challenge to guarantee the reliability of the electronics assemblies. This paper introduces a new technology of cleaning solution developed to be compatible in several processes. After a short description of co-solvent and aqueous process, the cleaning results concerning the new technology are shared. The cleaning efficiency is evaluated using IPC standards: visual inspection under microscope, ionic contamination, and SIR test. Surface tension is also measured. Then, a scoring method based on the GHS labelling system and REACH regulation is used to evaluate the environmental impact of this innovative cleaner technology. As a conclusion, the new cleaning solution does show promising results. For aqueous processes, this improvement allows to lower the cleaning time and/or the cleaning temperature. For co-solvent processes, the cleaning performance is similar with an improvement of the safety and the environmental footprint.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121100238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013241
Xiangy-Yu Wang, M. D. Rotaru, Yu Haitao, C. T. Chong, K. Chui
This paper demonstrates the 3D heterogenous integration of integrated circuit chips through a vertical stack-up (of SiPs) approach to achieve significant reduction in form factor with improved performance. In this paper, the process integration of high aspect ratio via-last TSV in a LNA SOI wafer will be described. The final aim of this work is to allow a 3D integration for RF front ends as schematically shown in Fig. 1. The front side metallization on the LNA device wafer includes one layer of Cu BEOL while the backside of the wafer consists of one Cu re-distribution layer (RDL) interconnect layer. The RF testing will be performed to verify the TSV and interconnections on LNA SOI wafer. Fig. 1 shows the schematic of test vehicle with filter chip assembled on LNA wafer with TSV for demonstration purpose.
{"title":"Via-Last TSV (From Top) Fabrication on a LNA SOI Wafer for 3D Heterogeneous Chiplet Integration","authors":"Xiangy-Yu Wang, M. D. Rotaru, Yu Haitao, C. T. Chong, K. Chui","doi":"10.1109/EPTC56328.2022.10013241","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013241","url":null,"abstract":"This paper demonstrates the 3D heterogenous integration of integrated circuit chips through a vertical stack-up (of SiPs) approach to achieve significant reduction in form factor with improved performance. In this paper, the process integration of high aspect ratio via-last TSV in a LNA SOI wafer will be described. The final aim of this work is to allow a 3D integration for RF front ends as schematically shown in Fig. 1. The front side metallization on the LNA device wafer includes one layer of Cu BEOL while the backside of the wafer consists of one Cu re-distribution layer (RDL) interconnect layer. The RF testing will be performed to verify the TSV and interconnections on LNA SOI wafer. Fig. 1 shows the schematic of test vehicle with filter chip assembled on LNA wafer with TSV for demonstration purpose.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"110 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121003669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013113
Haima Santican, Ilyas Dchar, Ding Yandoc, F. Le, Laudemer Latido
Solder paste is a susceptible material that requires extensive study to ensure meeting the desired manufacturability responses. The stencil printing process allowed a consistent amount of solder transfer onto a pad during the die attach process. Continuous development in solder application is done to ensure high-quality products are being produced. Critical responses such as maintaining uniform bond line thickness (BLT) and even die tilting have been the focus of this study. With available technologies in the market for die tilting improvement, this study focuses on exploring copper spacers technology in the solder paste printing material. Fillers are added into the paste which will serve as standoff and dictate the solder height underneath the die.
{"title":"Die Tilt Improvement Through Copper Spacers in Solder Paste Printing","authors":"Haima Santican, Ilyas Dchar, Ding Yandoc, F. Le, Laudemer Latido","doi":"10.1109/EPTC56328.2022.10013113","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013113","url":null,"abstract":"Solder paste is a susceptible material that requires extensive study to ensure meeting the desired manufacturability responses. The stencil printing process allowed a consistent amount of solder transfer onto a pad during the die attach process. Continuous development in solder application is done to ensure high-quality products are being produced. Critical responses such as maintaining uniform bond line thickness (BLT) and even die tilting have been the focus of this study. With available technologies in the market for die tilting improvement, this study focuses on exploring copper spacers technology in the solder paste printing material. Fillers are added into the paste which will serve as standoff and dictate the solder height underneath the die.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116561823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013231
M. Bellaredj, N. Andrianov, R. Kaufhold, G. Miskovic
In this work, an alternative dry etching approach for parylene AF4 is presented based on a photoresist soft mask, which results in a relatively simpler, faster, cheaper and environmentally friendly process in comparison to the typical dry etching process with a hard mask. 2.5 µm thick parylene AF4 was deposited on a silicon (Si) substrate by vapor deposition polymerization (VDP). A 5 µm thick photoresist was used as a soft mask, while parylene AF4 patterning was done using an oxygen (O2)-argon (Ar) inductively coupled plasma reactive ion etching (ICP-RIE) process. The AF4:photoresist selectivity was around 1 while the AF 4 etching rate was roughly 275 nm/min for an Ar/02 ratio of 0.1 at 20mTorr and ICP:CCP powers of 1000W:50W respectively. The influence of the ICP plasma parameters on the AF 4 etching rate was investigated and the results suggested a predominant oxygen radicals-based reactive chemical etching mechanism.
{"title":"Soft mask-based dry etching of parylene AF4 for advanced packaging applications","authors":"M. Bellaredj, N. Andrianov, R. Kaufhold, G. Miskovic","doi":"10.1109/EPTC56328.2022.10013231","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013231","url":null,"abstract":"In this work, an alternative dry etching approach for parylene AF4 is presented based on a photoresist soft mask, which results in a relatively simpler, faster, cheaper and environmentally friendly process in comparison to the typical dry etching process with a hard mask. 2.5 µm thick parylene AF4 was deposited on a silicon (Si) substrate by vapor deposition polymerization (VDP). A 5 µm thick photoresist was used as a soft mask, while parylene AF4 patterning was done using an oxygen (O2)-argon (Ar) inductively coupled plasma reactive ion etching (ICP-RIE) process. The AF4:photoresist selectivity was around 1 while the AF 4 etching rate was roughly 275 nm/min for an Ar/02 ratio of 0.1 at 20mTorr and ICP:CCP powers of 1000W:50W respectively. The influence of the ICP plasma parameters on the AF 4 etching rate was investigated and the results suggested a predominant oxygen radicals-based reactive chemical etching mechanism.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"14 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114037433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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