Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013302
Cheng-Yu Ho, Sheng-Chi Hsieh, Hong-Sheng Huang, Chia-Ching Chu, Chen-Chao Wang
This work discusses that the manufacturing tolerances and material characteristic of 4+2+4 multi-layer substrate impact on performance of Millimeter-wave (mmWave) antenna-in/on-package (AiP/AoP). The designed test kits to extract the material characteristic of multi-layer substrate including T -resonator, microstrip transmission line, and microstrip patch antenna. The stacking patch antenna implemented on 4+2+4 multi-layer substrate, and also discusses the manufacturing tolerances impact on performance of mmWave AiP/AiM. The correlation between measurement and simulation with extracted material characteristic and manufacturing tolerance shows that the frequency response is less than 0.1GHz from 24GHz to 30GHz. This simulation result has good correlation with the measurement result.
{"title":"Performance Analysis and Impact of Manufacturing Tolerances of multi-layers package substrate for 5G mmWave Antenna in Package/Module (AiP/AiM)","authors":"Cheng-Yu Ho, Sheng-Chi Hsieh, Hong-Sheng Huang, Chia-Ching Chu, Chen-Chao Wang","doi":"10.1109/EPTC56328.2022.10013302","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013302","url":null,"abstract":"This work discusses that the manufacturing tolerances and material characteristic of 4+2+4 multi-layer substrate impact on performance of Millimeter-wave (mmWave) antenna-in/on-package (AiP/AoP). The designed test kits to extract the material characteristic of multi-layer substrate including T -resonator, microstrip transmission line, and microstrip patch antenna. The stacking patch antenna implemented on 4+2+4 multi-layer substrate, and also discusses the manufacturing tolerances impact on performance of mmWave AiP/AiM. The correlation between measurement and simulation with extracted material characteristic and manufacturing tolerance shows that the frequency response is less than 0.1GHz from 24GHz to 30GHz. This simulation result has good correlation with the measurement result.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134543334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013174
Jiakai Chen, Yong Chyn Ng, D. K. Mishra, K. Chui
With the advancement of 3D packaging, hybrid bonding is the most widely explored technology for heterogeneous integration and stacking of dies. For the hybrid bonding, prior measurement of the surface roughness, dielectric erosion, and dishing/protrusion of the copper bond pads is critical to check the quality of the fabricated wafers. Generally, atomic force microscopy (AFM) is used to collect the surface morphology of the wafers, and then the manual measurement is done for each scanned file which is quite time-consuming. Therefore, in this article, an automated method of analysis of AFM data was developed in Python to measure critical surface parameters on the wafers used in hybrid bonding. The Python code was used to measure the surface roughness, dishing/protrusion of bond pads with different shapes, i.e., circular and square. The use of the code provides a quick, efficient, first-order analysis methodology for evaluating the quality of the bonding surface, thereby, significantly reducing the manual time required in data crunching.
{"title":"Automated Analysis of AFM Data of High-Density Cu Pad for Fine Pitch Wafer-to-Wafer (W2W) and Chip-to-Wafer (C2W) Hybrid Bonding","authors":"Jiakai Chen, Yong Chyn Ng, D. K. Mishra, K. Chui","doi":"10.1109/EPTC56328.2022.10013174","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013174","url":null,"abstract":"With the advancement of 3D packaging, hybrid bonding is the most widely explored technology for heterogeneous integration and stacking of dies. For the hybrid bonding, prior measurement of the surface roughness, dielectric erosion, and dishing/protrusion of the copper bond pads is critical to check the quality of the fabricated wafers. Generally, atomic force microscopy (AFM) is used to collect the surface morphology of the wafers, and then the manual measurement is done for each scanned file which is quite time-consuming. Therefore, in this article, an automated method of analysis of AFM data was developed in Python to measure critical surface parameters on the wafers used in hybrid bonding. The Python code was used to measure the surface roughness, dishing/protrusion of bond pads with different shapes, i.e., circular and square. The use of the code provides a quick, efficient, first-order analysis methodology for evaluating the quality of the bonding surface, thereby, significantly reducing the manual time required in data crunching.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132841818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013282
DaeYoung Park, HyeongIl Jeon, G. Kim, JiYeon Yang, KwangSoo Sang, B. Kim, JinYoung Khim
This paper discusses a highly integrated multi -chip module (MCM) routable (thin) MicroLeadFrame® (rtMLF®) packaging for multi-functional high-performance applications. The MCM rtMLF package includes internal routing leads to connect die to die within the package. These routing leads let the package enhance the small form factor and are compared with two single quad flat no-lead (QFN) packages where the dice were connected by board traces. Feasibility of the MCM rtMLF package was confirmed using a conventional QFN-process and the MCM rtMLF package passed the Automotive Electronics Council Q006 (AEC-Q006) reliability test. Die to die interconnections through routing leads showed higher electric performances in terms of resistance, inductance, capacitance parasitic and insertion loss than the on-board interconnections of the two single QFN packages. Lastly, thermal resistances of the MCM rtMLF package measured by thermal simulation were lower than those of MCM two-layer chip scale packages (CSPs).
{"title":"High Performance Multi-Chip Leadframe Package with Internal Connection","authors":"DaeYoung Park, HyeongIl Jeon, G. Kim, JiYeon Yang, KwangSoo Sang, B. Kim, JinYoung Khim","doi":"10.1109/EPTC56328.2022.10013282","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013282","url":null,"abstract":"This paper discusses a highly integrated multi -chip module (MCM) routable (thin) MicroLeadFrame® (rtMLF®) packaging for multi-functional high-performance applications. The MCM rtMLF package includes internal routing leads to connect die to die within the package. These routing leads let the package enhance the small form factor and are compared with two single quad flat no-lead (QFN) packages where the dice were connected by board traces. Feasibility of the MCM rtMLF package was confirmed using a conventional QFN-process and the MCM rtMLF package passed the Automotive Electronics Council Q006 (AEC-Q006) reliability test. Die to die interconnections through routing leads showed higher electric performances in terms of resistance, inductance, capacitance parasitic and insertion loss than the on-board interconnections of the two single QFN packages. Lastly, thermal resistances of the MCM rtMLF package measured by thermal simulation were lower than those of MCM two-layer chip scale packages (CSPs).","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133199112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013221
S. J. Gräfner, J.H. Huang, P. Shih, V. Renganathan, P. Kung, Y.A. Chen, C.H. Huang, C. Chen, C. Kao
Current chip packaging technologies for fine-pitch interconnections require high heat and pressure which could lead to failures on the surrounding delicate parts in the scaling-down process. By using electroless plating instead, these limitations could be avoided which already has been demonstrated in various experiments. However, the transition from experiments in the laboratory to the industrial fabrication has to face various challenges. A numerical multi-physics model to investigate the fluidic-chemical aspects while scaling-down the geometry for a possible mass production is developed. By the usage of this model, possible limitations, theoretical requirements and optimizations on the packaging system can be estimated and investigated. The results show that the pressure gradient of the model follows Darcy's law for porous medium. Furthermore, pillar couplings with gap usually have a non-uniform grow behavior. This non-uniformity can be optimized by applying a dome-shaped pillar-tip. Moreover, the convectional flux is in most of the samples of the domain dominant. Only by approaching the reactions surface, diffusion becomes a relevant part of the mass transport. The investigation of the Cu-ion concentration gradient shows that more Cu-ions are consumed while scaling down.
{"title":"Numerical fluidic-chemical multi-physics simulation of a mass production model for electroless plating of fine-pitch interconnections in a microchannel for chip packaging applications","authors":"S. J. Gräfner, J.H. Huang, P. Shih, V. Renganathan, P. Kung, Y.A. Chen, C.H. Huang, C. Chen, C. Kao","doi":"10.1109/EPTC56328.2022.10013221","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013221","url":null,"abstract":"Current chip packaging technologies for fine-pitch interconnections require high heat and pressure which could lead to failures on the surrounding delicate parts in the scaling-down process. By using electroless plating instead, these limitations could be avoided which already has been demonstrated in various experiments. However, the transition from experiments in the laboratory to the industrial fabrication has to face various challenges. A numerical multi-physics model to investigate the fluidic-chemical aspects while scaling-down the geometry for a possible mass production is developed. By the usage of this model, possible limitations, theoretical requirements and optimizations on the packaging system can be estimated and investigated. The results show that the pressure gradient of the model follows Darcy's law for porous medium. Furthermore, pillar couplings with gap usually have a non-uniform grow behavior. This non-uniformity can be optimized by applying a dome-shaped pillar-tip. Moreover, the convectional flux is in most of the samples of the domain dominant. Only by approaching the reactions surface, diffusion becomes a relevant part of the mass transport. The investigation of the Cu-ion concentration gradient shows that more Cu-ions are consumed while scaling down.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127429606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013281
K. Erbacher, Joao Alves Marques, Malte von Krshiwoblozki, Lixiang Wu, H. Ngo, M. Schneider-Ramelow
The paper describes the integration of novel developed acoustic MEMS sensors, in an ultra-thin and flexible substrate for use in aerospace applications, such as wind tunnel test (WTT) and flight test (FT). The technology allows the fabrication of a large area array with flush mounted microphone sensors without any topography interfering with the flow. The final array contains more than 80 piezoresistive and piezoelectric MEMS sensors, at a dimension of 300×400 mm2. The thickness of the bare die array is 600 µm, the array with the packaged sensors below 1550 µm.
{"title":"Aero Acoustic MEMS Microphone Integration in Ultra-Thin and Flexible Substrate","authors":"K. Erbacher, Joao Alves Marques, Malte von Krshiwoblozki, Lixiang Wu, H. Ngo, M. Schneider-Ramelow","doi":"10.1109/EPTC56328.2022.10013281","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013281","url":null,"abstract":"The paper describes the integration of novel developed acoustic MEMS sensors, in an ultra-thin and flexible substrate for use in aerospace applications, such as wind tunnel test (WTT) and flight test (FT). The technology allows the fabrication of a large area array with flush mounted microphone sensors without any topography interfering with the flow. The final array contains more than 80 piezoresistive and piezoelectric MEMS sensors, at a dimension of 300×400 mm2. The thickness of the bare die array is 600 µm, the array with the packaged sensors below 1550 µm.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114479711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013141
B. Dielacher, S. Schmölzer, T. Matthias, B. Považay, F. Bögelsack, R. Holly, T. Zenger, T. Uhrmann, B. Thallner
As heterogeneous integration is increasingly adopted for semiconductor development and innovation, back-end lithography requirements are growing. More redistribution layers (RDLs) within the package are driving the need for finer RDL line/spacing (L/S) as well as smaller critical dimensions for micro-bumps and micro-pillars. In this work, digital lithography was used to demonstrate an efficient dual damascene process implementation with respect to RDL and interconnect scaling. Multi-level exposure was used to reduce 50 % of lithographic steps and to allow for simultaneous generation of RDL and via structures without alignment. The results showed well-defined patterns with lateral dimensions < 5 µm which enable a new manufacturing scheme for the dual-damascene process with significant reduction in complexity and process time.
{"title":"Digital Lithography for Advanced Packaging and Heterogenous Integration","authors":"B. Dielacher, S. Schmölzer, T. Matthias, B. Považay, F. Bögelsack, R. Holly, T. Zenger, T. Uhrmann, B. Thallner","doi":"10.1109/EPTC56328.2022.10013141","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013141","url":null,"abstract":"As heterogeneous integration is increasingly adopted for semiconductor development and innovation, back-end lithography requirements are growing. More redistribution layers (RDLs) within the package are driving the need for finer RDL line/spacing (L/S) as well as smaller critical dimensions for micro-bumps and micro-pillars. In this work, digital lithography was used to demonstrate an efficient dual damascene process implementation with respect to RDL and interconnect scaling. Multi-level exposure was used to reduce 50 % of lithographic steps and to allow for simultaneous generation of RDL and via structures without alignment. The results showed well-defined patterns with lateral dimensions < 5 µm which enable a new manufacturing scheme for the dual-damascene process with significant reduction in complexity and process time.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114618385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013306
S. Merugu, S. A. Sek, Navab Singh
This work demonstrates wafer-level thin film encapsulation (TFE) [1], [2] of a radio-frequency microelectromechanical systems (RF MEMS) device with rerouting of contacts and pads for flip-chip compatibility to a much smaller CMOS chip. RF MEMS devices are a key market driver for growth in the MEMS industry. This article enunciates the optimization of lithography steps in defining redistribution layers (RDL) and opening bond pads on high topography RFMEMS wafer to reduce RC delay and match bond pad locations for Heterogeneous integration of MEMS with ASIC.
{"title":"Lithography process optimization to realize RDL layers on high topography wafers for heterogeneous integration","authors":"S. Merugu, S. A. Sek, Navab Singh","doi":"10.1109/EPTC56328.2022.10013306","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013306","url":null,"abstract":"This work demonstrates wafer-level thin film encapsulation (TFE) [1], [2] of a radio-frequency microelectromechanical systems (RF MEMS) device with rerouting of contacts and pads for flip-chip compatibility to a much smaller CMOS chip. RF MEMS devices are a key market driver for growth in the MEMS industry. This article enunciates the optimization of lithography steps in defining redistribution layers (RDL) and opening bond pads on high topography RFMEMS wafer to reduce RC delay and match bond pad locations for Heterogeneous integration of MEMS with ASIC.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125738570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013161
S. Chong, Ismael Cereno Daniel, V. N. Sekhar, S. Lim, V. Srinivas
Chip to wafer hybrid bonding is the prefer choice for high performance 2.5D application as it offered very high dense I/O population down to 10¼m pitch with 5¼m pad diameter. This type of pitch and pad diameter cannot be obtained with conventional copper bump with solder cap. The conventional copper bump with solder cap had issue with solder merging, void and cracked solder. We had demonstrated good Cu-Cu interface with 10¼m pitch with 5¼m Cu pad diameter.
{"title":"Chip-to-Wafer Hybrid Bonding for high performance 2.5D applications","authors":"S. Chong, Ismael Cereno Daniel, V. N. Sekhar, S. Lim, V. Srinivas","doi":"10.1109/EPTC56328.2022.10013161","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013161","url":null,"abstract":"Chip to wafer hybrid bonding is the prefer choice for high performance 2.5D application as it offered very high dense I/O population down to 10¼m pitch with 5¼m pad diameter. This type of pitch and pad diameter cannot be obtained with conventional copper bump with solder cap. The conventional copper bump with solder cap had issue with solder merging, void and cracked solder. We had demonstrated good Cu-Cu interface with 10¼m pitch with 5¼m Cu pad diameter.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126149482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013143
Sasi Kumar Tippabhotla, L. Ji, C. Choong
Development of chip to wafer hybrid bonding (C2W-HB) process is essential to achieve direct bonding of fine pitch (≤ 10 μm) Cu interconnects for heterogeneous integration. As the polymer mechanical behavior is more complex, C2W-HB with direct bonding of Cu/polymer-dielectrics requires significant experimental efforts, resources, and time to design the test vehicles and formulate the process recipe for high quality and yield. In this work, numerical simulations are performed to evaluate the bonding progression for a special case where SiO2 dielectric is used for the bottom wafer and polymer dielectric is used for the top dies. As these two materials are quite different in their thermomechanical behaviour, bonding of the Cu/Cu interfaces depends on the relative expansion/contraction of the surrounding SiO2 (bottom wafer) and dielectric polymer (top die) interface. Our simulations help to elucidate the mechanics at the bonding interface and explain the reasons for the bonding failures observed in the experimental runs. The simulation results show that Cu pad dishing is not suitable for this configuration and protrusion of Cu pads is required to get a successful Cu/Cu direct bonding.
{"title":"Numerical Simulations to Assist Chip-to-Wafer Hybrid Bonding Process Development","authors":"Sasi Kumar Tippabhotla, L. Ji, C. Choong","doi":"10.1109/EPTC56328.2022.10013143","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013143","url":null,"abstract":"Development of chip to wafer hybrid bonding (C2W-HB) process is essential to achieve direct bonding of fine pitch (≤ 10 μm) Cu interconnects for heterogeneous integration. As the polymer mechanical behavior is more complex, C2W-HB with direct bonding of Cu/polymer-dielectrics requires significant experimental efforts, resources, and time to design the test vehicles and formulate the process recipe for high quality and yield. In this work, numerical simulations are performed to evaluate the bonding progression for a special case where SiO2 dielectric is used for the bottom wafer and polymer dielectric is used for the top dies. As these two materials are quite different in their thermomechanical behaviour, bonding of the Cu/Cu interfaces depends on the relative expansion/contraction of the surrounding SiO2 (bottom wafer) and dielectric polymer (top die) interface. Our simulations help to elucidate the mechanics at the bonding interface and explain the reasons for the bonding failures observed in the experimental runs. The simulation results show that Cu pad dishing is not suitable for this configuration and protrusion of Cu pads is required to get a successful Cu/Cu direct bonding.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128462304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013245
J. Sharma, Yul Koh, Sagnik Ghosh, Han Xuan Wong, L. Joshua
The integration of novel process flows for the fabrication of microelectromechanical system (MEMS) and nanoelectromechanical system (NEMS) devices invariably requires an initial round of short loops to qualify the critical process steps prior to full device fabrication. This paper presents some of the initial short loop based in-line qualification results obtained during the fabrication of zero-power wake-up acceleration switches fabricated on silicon-on-insulator (SOI) wafers with 1µm buried oxide (BOX) for a range of active silicon thicknesses. Narrow trench openings in the silicon device layer is a common requirements in the fabrication of MEMS and NEMS devices in SOI. Isolation across narrow gaps was verified in-line through electrical measurements, corroborated by cross-sectional inspections from scanning electron micrographs (SEM). Similarly, the release of MEMS structures by vapor hydrofluoric acid (VHF) was verified by in-line infrared (IR) inspection metrology tool after removing the metal from the test structures to be inspected. These test structures for in-line metrology inspection help shorten the fabrication time and improve the yield of the final fabricated device.
{"title":"In-line test structures for yield improvement in MEMS/NEMS device","authors":"J. Sharma, Yul Koh, Sagnik Ghosh, Han Xuan Wong, L. Joshua","doi":"10.1109/EPTC56328.2022.10013245","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013245","url":null,"abstract":"The integration of novel process flows for the fabrication of microelectromechanical system (MEMS) and nanoelectromechanical system (NEMS) devices invariably requires an initial round of short loops to qualify the critical process steps prior to full device fabrication. This paper presents some of the initial short loop based in-line qualification results obtained during the fabrication of zero-power wake-up acceleration switches fabricated on silicon-on-insulator (SOI) wafers with 1µm buried oxide (BOX) for a range of active silicon thicknesses. Narrow trench openings in the silicon device layer is a common requirements in the fabrication of MEMS and NEMS devices in SOI. Isolation across narrow gaps was verified in-line through electrical measurements, corroborated by cross-sectional inspections from scanning electron micrographs (SEM). Similarly, the release of MEMS structures by vapor hydrofluoric acid (VHF) was verified by in-line infrared (IR) inspection metrology tool after removing the metal from the test structures to be inspected. These test structures for in-line metrology inspection help shorten the fabrication time and improve the yield of the final fabricated device.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131030160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：