Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013307
Jiale Peng, Wei-Hao Lan, Fulong Wei, Chao Deng, Xiaobing Luo
The logging tools detecting the hydrocarbon resources are obliged to operate for several hours under high temperature downhole environment. However, the internal electronics, especially the high-power electronics, cannot function for such long time limited by their temperature resistance. In previous thermal management, the heat conduction thermal resistance between the heat source and the PCM was high, resulting in a large temperature difference between them and the operating time of the electronics limited. To solve this problem, a thermal management for high-power downhole electronics combining liquid cooling with PCM under high temperature environment was proposed. Numerical simulation of the proposed thermal management method was calculated by finite element method. The results show that compared to conventional thermal management, the final temperature of the heat source is reduced by 29°C, the average equivalent thermal resistance is reduced by more than 0.5°C/W, and the PCM utilization is improved by 1.9%. Moreover, the heat flow from the heat source to PCM is enhanced compared to the convention thermal management.
{"title":"Thermal management for high-power downhole electronics using liquid cooling and PCM under high temperature environment","authors":"Jiale Peng, Wei-Hao Lan, Fulong Wei, Chao Deng, Xiaobing Luo","doi":"10.1109/EPTC56328.2022.10013307","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013307","url":null,"abstract":"The logging tools detecting the hydrocarbon resources are obliged to operate for several hours under high temperature downhole environment. However, the internal electronics, especially the high-power electronics, cannot function for such long time limited by their temperature resistance. In previous thermal management, the heat conduction thermal resistance between the heat source and the PCM was high, resulting in a large temperature difference between them and the operating time of the electronics limited. To solve this problem, a thermal management for high-power downhole electronics combining liquid cooling with PCM under high temperature environment was proposed. Numerical simulation of the proposed thermal management method was calculated by finite element method. The results show that compared to conventional thermal management, the final temperature of the heat source is reduced by 29°C, the average equivalent thermal resistance is reduced by more than 0.5°C/W, and the PCM utilization is improved by 1.9%. Moreover, the heat flow from the heat source to PCM is enhanced compared to the convention thermal management.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131988644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013149
Lee Hou Jang Steven, Liu Peng Patrick, Li Huamao
Silane-based silicon oxides with deposition temperatures ranging from 80°C to 300°C have been studied using Plasma Enhance Chemical Vapor Deposition (PECVD). The oxides were deposited using high frequency (HF, 13.56MHz) as well as low frequency (LF, 380KHz) Radio Frequency (RF) power sources in a capacitively-coupled plasma reactor. The high frequency and low frequency silicon oxides exhibited different film stresses and etch rates. The high frequency silicon oxide at 150°C was chosen for the encapsulation of Micro-Electro-Mechanical Systems (MEMS) devices due to its lower film stress and smoother surface roughness.
{"title":"Low Temperature Silane-Based Silicon Oxides for MEMS and Packaging Applications","authors":"Lee Hou Jang Steven, Liu Peng Patrick, Li Huamao","doi":"10.1109/EPTC56328.2022.10013149","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013149","url":null,"abstract":"Silane-based silicon oxides with deposition temperatures ranging from 80°C to 300°C have been studied using Plasma Enhance Chemical Vapor Deposition (PECVD). The oxides were deposited using high frequency (HF, 13.56MHz) as well as low frequency (LF, 380KHz) Radio Frequency (RF) power sources in a capacitively-coupled plasma reactor. The high frequency and low frequency silicon oxides exhibited different film stresses and etch rates. The high frequency silicon oxide at 150°C was chosen for the encapsulation of Micro-Electro-Mechanical Systems (MEMS) devices due to its lower film stress and smoother surface roughness.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134145355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013258
Yoshinori Matsuura, T. Yoshida, Yukiko Komiya, Toshimi Nakamura, Takenori Yanai, Kazuhiro Okuyama, Kyohei Kuwahara, Yukiko Kitabatake, Rintaro Ishii, Katsuyuki Hayashi, Takashi Kubota, Joji Fujii, V. B. Dutta
Rigid carrier substrates are essential to support assembly of advanced ultra-thin high-density packages and modules on wafer and panel format. An organic bonding-debonding layer is applied on the carrier which remains all through assembly and detached/released once package assembly is completed. Today borosilicate glass is used as carrier material. With the need for advanced package architecture, the organic bonding/debonding materials have reached their limits, with process and yield related issues. Further, besides the restriction to use high-cost borosilicate glass as carrier material, there are several other technical issues associated with organic bonding-debonding release material. In this paper these details have been discussed and an alternate material set is described. A new “Rigid carrier with composite inorganic release layer” is introduced. It overcomes the current assembly issues along with the opportunity to reduce total manufacturing cost, with availability of several low-cost rigid substrate carrier materials. This novel material set is referred as HRDP® (High Resolution Debondable Panel) and is available in large size wafer and panel formats. The HRDP serves as a drop-in solution to existing assembly flow. This paper describes the new material set, process details to achieve ultra-fine line/space (<1um), impact on warpage and debonding release force, chemical and thermal resistance results as well as cost comparison data.
{"title":"Introducing novel “Rigid Carrier with Composite Release Layer” to assemble ultra-high density Advanced Packages & Substrates in wafer and panel format","authors":"Yoshinori Matsuura, T. Yoshida, Yukiko Komiya, Toshimi Nakamura, Takenori Yanai, Kazuhiro Okuyama, Kyohei Kuwahara, Yukiko Kitabatake, Rintaro Ishii, Katsuyuki Hayashi, Takashi Kubota, Joji Fujii, V. B. Dutta","doi":"10.1109/EPTC56328.2022.10013258","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013258","url":null,"abstract":"Rigid carrier substrates are essential to support assembly of advanced ultra-thin high-density packages and modules on wafer and panel format. An organic bonding-debonding layer is applied on the carrier which remains all through assembly and detached/released once package assembly is completed. Today borosilicate glass is used as carrier material. With the need for advanced package architecture, the organic bonding/debonding materials have reached their limits, with process and yield related issues. Further, besides the restriction to use high-cost borosilicate glass as carrier material, there are several other technical issues associated with organic bonding-debonding release material. In this paper these details have been discussed and an alternate material set is described. A new “Rigid carrier with composite inorganic release layer” is introduced. It overcomes the current assembly issues along with the opportunity to reduce total manufacturing cost, with availability of several low-cost rigid substrate carrier materials. This novel material set is referred as HRDP® (High Resolution Debondable Panel) and is available in large size wafer and panel formats. The HRDP serves as a drop-in solution to existing assembly flow. This paper describes the new material set, process details to achieve ultra-fine line/space (<1um), impact on warpage and debonding release force, chemical and thermal resistance results as well as cost comparison data.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122409704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013236
Chuanguo Xiong, Baoshan Zeng, Yuhua Huang, F. Zhu
Electronic components may fail because of non-uniform thermal load, different Coefficients of Thermal Expansion (CTE) among packaging materials, or solder curing shrinkage. Common failures include substrate warpage, structure delamination, and cracking, which reflect the signification of thermal deformation detection for packaging structures. To illustrate the thermo mechanical properties of electronic packages, a non-destructive inspection method combining the projected speckle three-dimensional digital image correlation (3D DIC) technique and infrared thermography (IRT) is proposed. The temperature of each point on the sample surface is obtained by camera calibration, thereby realizing the coupling of mechanical and thermal information. This method can measure out-of-plane displacement without contaminating the sample and adjust the projected speckle flexibly in different applied situations. The inspection system is validated by displacement measurement and chip-heating experiments, and the standard deviation of displacement can be controlled within 1µm.
{"title":"A non-destructive inspection method for electronic packaging reliability incorporating mechanical and thermal information","authors":"Chuanguo Xiong, Baoshan Zeng, Yuhua Huang, F. Zhu","doi":"10.1109/EPTC56328.2022.10013236","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013236","url":null,"abstract":"Electronic components may fail because of non-uniform thermal load, different Coefficients of Thermal Expansion (CTE) among packaging materials, or solder curing shrinkage. Common failures include substrate warpage, structure delamination, and cracking, which reflect the signification of thermal deformation detection for packaging structures. To illustrate the thermo mechanical properties of electronic packages, a non-destructive inspection method combining the projected speckle three-dimensional digital image correlation (3D DIC) technique and infrared thermography (IRT) is proposed. The temperature of each point on the sample surface is obtained by camera calibration, thereby realizing the coupling of mechanical and thermal information. This method can measure out-of-plane displacement without contaminating the sample and adjust the projected speckle flexibly in different applied situations. The inspection system is validated by displacement measurement and chip-heating experiments, and the standard deviation of displacement can be controlled within 1µm.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127679444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013219
L. Chua, Hui Qin Woo, Khai Seen Yong, Wu-Hu Li, L. P. Tan, C. Gan
In this paper, the properties of silica-epoxy interface and effect of deep traps on the dielectric breakdown performance of Epoxy Moulding Compounds (EMC) were investigated to address the lack of understanding on how the higher voltages and frequencies, affect the encapsulation material of the devices. The interfacial properties, trap properties and dielectric breakdown strength of EMC formulations modified by a type of coupling agent, named AS, were studied. This paper found that the improvement in filler dispersion (i.e. a reduction of filler aggregation rate and an improvement of filler size distribution) and the increase in deep trap depth and density could improve the AC dielectric breakdown strength. The changes in the silica-epoxy interface via the addition of AS can be explained using the Maxwell-Wagner-Sillars (MWS) polarisation mechanism. EMC with 100% AS-treated silica was found to have the best dielectric breakdown performance due to its high dielectric breakdown strength of $21.41pm 0.20 text{kV}/text{mm}$ measured.
{"title":"Role of Silica-Epoxy Interface and Deep Traps on the Dielectric Breakdown Performance of Epoxy Moulding Compounds (EMC)","authors":"L. Chua, Hui Qin Woo, Khai Seen Yong, Wu-Hu Li, L. P. Tan, C. Gan","doi":"10.1109/EPTC56328.2022.10013219","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013219","url":null,"abstract":"In this paper, the properties of silica-epoxy interface and effect of deep traps on the dielectric breakdown performance of Epoxy Moulding Compounds (EMC) were investigated to address the lack of understanding on how the higher voltages and frequencies, affect the encapsulation material of the devices. The interfacial properties, trap properties and dielectric breakdown strength of EMC formulations modified by a type of coupling agent, named AS, were studied. This paper found that the improvement in filler dispersion (i.e. a reduction of filler aggregation rate and an improvement of filler size distribution) and the increase in deep trap depth and density could improve the AC dielectric breakdown strength. The changes in the silica-epoxy interface via the addition of AS can be explained using the Maxwell-Wagner-Sillars (MWS) polarisation mechanism. EMC with 100% AS-treated silica was found to have the best dielectric breakdown performance due to its high dielectric breakdown strength of $21.41pm 0.20 text{kV}/text{mm}$ measured.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127943483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013223
Nils-Malte Jahn, M. Pfost
In this work, a method for the detection of detached bond wires from the chip of a discrete power semiconductor is presented. For this, differences in the thermal behavior caused by manipulated bond wires are detected with four external temperature sensors adjacent to the device. For experimental verification of this method, multiple test devices with varying bond wire faults are subjected to a power pulse and the temperature response is recorded. Two different concepts for the interpretation of the measured data are presented. The suitability of both concepts is discussed and the sensor requirements for a successful fault detection are evaluated.
{"title":"Detection of Bond Wire Failure in Power Semiconductors by Adjacent Temperature Sensors","authors":"Nils-Malte Jahn, M. Pfost","doi":"10.1109/EPTC56328.2022.10013223","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013223","url":null,"abstract":"In this work, a method for the detection of detached bond wires from the chip of a discrete power semiconductor is presented. For this, differences in the thermal behavior caused by manipulated bond wires are detected with four external temperature sensors adjacent to the device. For experimental verification of this method, multiple test devices with varying bond wire faults are subjected to a power pulse and the temperature response is recorded. Two different concepts for the interpretation of the measured data are presented. The suitability of both concepts is discussed and the sensor requirements for a successful fault detection are evaluated.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129328855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013121
Ran Yin, K. Nieweglowski, K. Meier, K. Bock
The demand for flexible electronic packaging technologies enabling reliable flexible high-frequency applications is increasing. Embedding of fully integrated wireless transceivers (mm-wave ICs - MMIC) operating at high frequencies needs to be developed. As part of this, to ensure the required embedding technology and the direct contact technology have a proper performance, it is necessary to perform electrical characterization of the embedded chips. In this paper, 1 × 1 mm2 sized silicon test chips with daisy chains were designed and built on thin 200 μm Si-wafer. Subsequently, test chips were embedded in SMC for electrical tests and, in the future, high frequency characterization. The RDL layer is constructed by means of a semi-additive procedure to connect RDL test pads with the daisy chain consisting of chip-level pads and traces, RDL through vias and traces. Metallization is done by PVD and galvanic plating. Measurements were performed primarily to verify a proper interconnection between the metal lines of the RDL layer and the pads on the embedded chip. The resistance-based characterization shows promising results, indicating the interconnects from the embedded chip to the RDL using Cu pillars to be less sensitive against process uncertainties and better defined compared to flip-chip bonding with Au stud- bumps, verifying the prospect of this novel fabrication technique.
{"title":"Embedding of Thinned RF Chips and Electrical Redistribution Layer Characterization","authors":"Ran Yin, K. Nieweglowski, K. Meier, K. Bock","doi":"10.1109/EPTC56328.2022.10013121","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013121","url":null,"abstract":"The demand for flexible electronic packaging technologies enabling reliable flexible high-frequency applications is increasing. Embedding of fully integrated wireless transceivers (mm-wave ICs - MMIC) operating at high frequencies needs to be developed. As part of this, to ensure the required embedding technology and the direct contact technology have a proper performance, it is necessary to perform electrical characterization of the embedded chips. In this paper, 1 × 1 mm2 sized silicon test chips with daisy chains were designed and built on thin 200 μm Si-wafer. Subsequently, test chips were embedded in SMC for electrical tests and, in the future, high frequency characterization. The RDL layer is constructed by means of a semi-additive procedure to connect RDL test pads with the daisy chain consisting of chip-level pads and traces, RDL through vias and traces. Metallization is done by PVD and galvanic plating. Measurements were performed primarily to verify a proper interconnection between the metal lines of the RDL layer and the pads on the embedded chip. The resistance-based characterization shows promising results, indicating the interconnects from the embedded chip to the RDL using Cu pillars to be less sensitive against process uncertainties and better defined compared to flip-chip bonding with Au stud- bumps, verifying the prospect of this novel fabrication technique.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129362256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013287
Shushil Kumar Penumaka, R. Pamidighantam, Rohin Kumar Yeluripati, Mohammad Ubed, J. Bhandari
As parallel optical data rates are increasing from tens of Gbps to twenty-five Gbps and beyond[2], Vertical cavity surface emission lasers(VCSELs) and Photo Detectors(PDs) are evolving to accommodate these bandwidths as more channels are being accommodated in a small form factor, there is a need to maintain the coupling efficiency and the performance of the system as the tolerance become tighter due to accommodating channels, To overcome the issues regarding the alignment of these small Optical Modules handling huge amounts of data we require a Mechanical Optical Interface(MOI) which should be capable of handling the tolerance up to tens of microns. This paper describes a small form factor high-speed optical interconnect module called LightKonnectTM built in-house that is capable of up to 192Gbps with 12 channels, having very minute dimensions of 7.0mmx4.9mmx2.76mm±0.lmm. The developed MOI is a custom design prototype to test LightKonnectTM Transmitter(LKTM TX) and LightKonnectTM Receiver (LKTM RX) by a loopback test. This MOI provides a base for a mountable Dove Prism and is capable to provide freedom to the prism in XYZ directions for alignment tolerance of 50 microns, which is tested for the efficient coupling between the VCSEL TOSA(Transmitter optical subassembly)(LKTM TX) and PD ROSA(Receiver optical subassembly)(LKTM RX) which results for the alignment of 12 channels from transmitter to receiver, with maximum coupling performance and low BER for each channel.
{"title":"Development of Test Hardware with Optomechanical Alignment for 200Gbps free space TOSA/ROSA","authors":"Shushil Kumar Penumaka, R. Pamidighantam, Rohin Kumar Yeluripati, Mohammad Ubed, J. Bhandari","doi":"10.1109/EPTC56328.2022.10013287","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013287","url":null,"abstract":"As parallel optical data rates are increasing from tens of Gbps to twenty-five Gbps and beyond[2], Vertical cavity surface emission lasers(VCSELs) and Photo Detectors(PDs) are evolving to accommodate these bandwidths as more channels are being accommodated in a small form factor, there is a need to maintain the coupling efficiency and the performance of the system as the tolerance become tighter due to accommodating channels, To overcome the issues regarding the alignment of these small Optical Modules handling huge amounts of data we require a Mechanical Optical Interface(MOI) which should be capable of handling the tolerance up to tens of microns. This paper describes a small form factor high-speed optical interconnect module called LightKonnectTM built in-house that is capable of up to 192Gbps with 12 channels, having very minute dimensions of 7.0mmx4.9mmx2.76mm±0.lmm. The developed MOI is a custom design prototype to test LightKonnectTM Transmitter(LKTM TX) and LightKonnectTM Receiver (LKTM RX) by a loopback test. This MOI provides a base for a mountable Dove Prism and is capable to provide freedom to the prism in XYZ directions for alignment tolerance of 50 microns, which is tested for the efficient coupling between the VCSEL TOSA(Transmitter optical subassembly)(LKTM TX) and PD ROSA(Receiver optical subassembly)(LKTM RX) which results for the alignment of 12 channels from transmitter to receiver, with maximum coupling performance and low BER for each channel.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128535004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013154
F. Yen, V. Lin, Yu-Po Wang
The microelectronics products of Flip Chip-Chip Scale Package (FCCSP) with more increasing challenges are faced to assure molding capability with rapid advances in flip chip technology such as decreasing stand-off height and fine bump pitch (high bump density), especially when Molded Underfill (MUF) is used during transfer molding process. There is one important challenge that faced severe air void entrapment underneath the die region (air void concentrate among bumps region). Generally, the experiments involving a lot of DOE matrixes which spend a lot of time and materials (dummy die, substrate, mold compound…etc.) to solve this air void issue. As above reasons, the moldflow simulation can be used to apply molding parameters to find out optimum solutions for air void risk free of MUF FCCSP with different substrate solder mask pattern design which can reduce development cycle time before mass production. In this paper, 3D moldflow simulation software which can apply transfer molding process parameters is used. There is substrate solder mask with different opening area percentage (finger like) design within die region and molding compound flow to die region that solder mask opening area with 20um depth structure to perform different melt-front behavior. From this study, we can conclude some results for improvement molding performance of FCCSP(MUF) during transfer molding process. The FCCSP(MUF) with the 65um stand-off height structure performs low air void risk due to mold compound could easily flow under die region with more flow space. In addition, mold compound also performs well melt-front flow when the substrate solder mask with opening area as 25% and opening pattern design as horizontal as flow direction that both can get more space and smooth flow underneath die region to reduce void risk during molding process.
{"title":"Substrate Design Optimization of Fine Pitch FCCSP for Molded Underfill Void Free Evaluation","authors":"F. Yen, V. Lin, Yu-Po Wang","doi":"10.1109/EPTC56328.2022.10013154","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013154","url":null,"abstract":"The microelectronics products of Flip Chip-Chip Scale Package (FCCSP) with more increasing challenges are faced to assure molding capability with rapid advances in flip chip technology such as decreasing stand-off height and fine bump pitch (high bump density), especially when Molded Underfill (MUF) is used during transfer molding process. There is one important challenge that faced severe air void entrapment underneath the die region (air void concentrate among bumps region). Generally, the experiments involving a lot of DOE matrixes which spend a lot of time and materials (dummy die, substrate, mold compound…etc.) to solve this air void issue. As above reasons, the moldflow simulation can be used to apply molding parameters to find out optimum solutions for air void risk free of MUF FCCSP with different substrate solder mask pattern design which can reduce development cycle time before mass production. In this paper, 3D moldflow simulation software which can apply transfer molding process parameters is used. There is substrate solder mask with different opening area percentage (finger like) design within die region and molding compound flow to die region that solder mask opening area with 20um depth structure to perform different melt-front behavior. From this study, we can conclude some results for improvement molding performance of FCCSP(MUF) during transfer molding process. The FCCSP(MUF) with the 65um stand-off height structure performs low air void risk due to mold compound could easily flow under die region with more flow space. In addition, mold compound also performs well melt-front flow when the substrate solder mask with opening area as 25% and opening pattern design as horizontal as flow direction that both can get more space and smooth flow underneath die region to reduce void risk during molding process.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129408944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-07DOI: 10.1109/EPTC56328.2022.10013135
Hiu Hay Nichole Lam, Chi Ho Leung, Chi Leung Chui, Shun Tik Yeung
As the semiconductor market grows, the industry is pushing for cheaper and better process that could ensure product integrity and quality. While blade saw singulation is the dominant method in package singulation, laser has proven through various trials to be a better alternative by enhancing the quality in terms of package integrity and improving lead frame density. This technical paper looks into laser package singulation and examines its feasibility in providing a better solution in singulation. The major goal in this project is defined to maintain the rigidity and integrity of the encapsulated lead frame after singulation as required by electroplating process afterwards, while addressing the problems induced by blade saw using laser. Trials are done on DFNs using UV laser, a relatively “cold” laser which provides excellent results of devices free of delamination, burr and smear for both CSAM checking and cross-sectioning examination. Lead frame density can also be increased as the saw lane width is significantly reduced. Moreover, laser package singulation could also be a new cost-down opportunity, as consumable materials such as tape and blade which is prone to wear and tear are not required in this method. Nevertheless, the key challenges ahead in this approach are the carbonization problem due to the intense heat from laser, which can hinder the electroplating process, shorted leads and a low singulation speed. After analysis stage, these problems are found to be solved by changing the parameters of laser and by chemical surface cleaning. It is important to note that the results are interrelated to several parameters simultaneously, and thus the settings have to be optimized for the best result. The application of laser singulation can be extended to all packages. And this paper illustrates the possibility and feasibility of laser package singulation.
{"title":"Laser Package Singulation: A Promising Singulation Method for Better Package Integrity and Quality","authors":"Hiu Hay Nichole Lam, Chi Ho Leung, Chi Leung Chui, Shun Tik Yeung","doi":"10.1109/EPTC56328.2022.10013135","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013135","url":null,"abstract":"As the semiconductor market grows, the industry is pushing for cheaper and better process that could ensure product integrity and quality. While blade saw singulation is the dominant method in package singulation, laser has proven through various trials to be a better alternative by enhancing the quality in terms of package integrity and improving lead frame density. This technical paper looks into laser package singulation and examines its feasibility in providing a better solution in singulation. The major goal in this project is defined to maintain the rigidity and integrity of the encapsulated lead frame after singulation as required by electroplating process afterwards, while addressing the problems induced by blade saw using laser. Trials are done on DFNs using UV laser, a relatively “cold” laser which provides excellent results of devices free of delamination, burr and smear for both CSAM checking and cross-sectioning examination. Lead frame density can also be increased as the saw lane width is significantly reduced. Moreover, laser package singulation could also be a new cost-down opportunity, as consumable materials such as tape and blade which is prone to wear and tear are not required in this method. Nevertheless, the key challenges ahead in this approach are the carbonization problem due to the intense heat from laser, which can hinder the electroplating process, shorted leads and a low singulation speed. After analysis stage, these problems are found to be solved by changing the parameters of laser and by chemical surface cleaning. It is important to note that the results are interrelated to several parameters simultaneously, and thus the settings have to be optimized for the best result. The application of laser singulation can be extended to all packages. And this paper illustrates the possibility and feasibility of laser package singulation.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115373750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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